int
t114_set_dev_param(build_image_context *context,
u_int32_t index,
parse_token token,
u_int32_t value)
{
nvboot_config_table *bct = NULL;
bct = (nvboot_config_table *)(context->bct);
assert(context != NULL);
assert(bct != NULL);
bct->num_param_sets = NV_MAX(bct->num_param_sets, index + 1);
switch (token) {
CASE_SET_DEV_PARAM(sdmmc, clock_divider);
CASE_SET_DEV_PARAM(sdmmc, data_width);
CASE_SET_DEV_PARAM(sdmmc, max_power_class_supported);
CASE_SET_DEV_PARAM(sdmmc, multi_page_support);
CASE_SET_DEV_PARAM(spiflash, clock_source);
CASE_SET_DEV_PARAM(spiflash, clock_divider);
CASE_SET_DEV_PARAM(spiflash, read_command_type_fast);
CASE_SET_DEV_PARAM(spiflash, page_size_2k_or_16k);
case token_dev_type:
bct->dev_type[index] = value;
break;
default:
return -ENODATA;
}
return 0;
}
NvBool
NvRmPrivAp20DttClockUpdate(
NvRmDeviceHandle hRmDevice,
const NvRmTzonePolicy* pDttPolicy,
const NvRmDfsFrequencies* pCurrentKHz,
NvRmDfsFrequencies* pDfsKHz)
{
switch ((NvRmDttAp20PolicyRange)pDttPolicy->PolicyRange)
{
case NvRmDttAp20PolicyRange_ThrottleDown:
if (pDttPolicy->UpdateFlag)
s_CpuThrottleKHz -= NVRM_DTT_CPU_DELTA_KHZ;
s_CpuThrottleKHz = NV_MAX(s_CpuThrottleKHz, s_CpuThrottleMinKHz);
break;
// No throttling by default (just reset throttling limit to max)
default:
s_CpuThrottleKHz = s_CpuThrottleMaxKHz;
return NV_FALSE;
}
pDfsKHz->Domains[NvRmDfsClockId_Cpu] =
NV_MIN(pDfsKHz->Domains[NvRmDfsClockId_Cpu], s_CpuThrottleKHz);
// Throttling step is completed - no need to force extra DVFS update
return NV_FALSE;
}
static nv_matrix_t *
conv_image2vec(const nv_bgseg_t *bg,
const nv_matrix_t *image)
{
nv_matrix_t *vec;
nv_matrix_t *smooth;
nv_matrix_t *resize = NULL, *gray = NULL;
int i;
float scale = (float)bg->size / (float)NV_MAX(image->rows, image->cols);
if (scale != 1.0f) {
resize = nv_matrix3d_alloc(image->n,
NV_ROUND_INT(image->rows * scale),
NV_ROUND_INT(image->cols * scale));
nv_resize(resize, image);
image = resize;
}
if (image->n != 1) {
gray = nv_matrix3d_alloc(1, image->rows, image->cols);
nv_gray(gray, image);
image = gray;
}
vec = nv_matrix_alloc(image->rows * image->cols, 1);
smooth = nv_matrix_clone(image);
nv_gaussian5x5(smooth, 0, image, 0);
for (i = 0; i < image->m; ++i) {
NV_MAT_V(vec, 0, i) = NV_MAT_V(smooth, i, 0);
}
nv_matrix_free(&smooth);
nv_matrix_free(&gray);
nv_matrix_free(&resize);
return vec;
}
inline float
similarity(const nv_matrix_t *v1, int j1,
const nv_matrix_t *v2, int j2)
{
float dot = nv_vector_dot(v1, j1, v2, j2);
return NV_MAX(0.0f, dot);
}
nv_bgseg_t *
nv_bgseg_alloc(int frame_rows, int frame_cols,
float zeta, float bg_v, float fg_v,
int size
)
{
nv_bgseg_t *bg = nv_alloc_type(nv_bgseg_t, 1);
float scale = (float)size / (float)NV_MAX(frame_rows, frame_cols);
bg->init_1st = 0;
bg->init_2nd = 0;
bg->init_1st_finished = 0;
bg->init_2nd_finished = 0;
bg->frame_rows = frame_rows;
bg->frame_cols = frame_cols;
bg->rows = NV_ROUND_INT(frame_rows * scale);
bg->cols = NV_ROUND_INT(frame_cols * scale);
bg->zeta = zeta;
bg->bg_v = bg_v;
bg->fg_v = fg_v;
bg->size = size;
bg->av = nv_matrix_alloc(1 * bg->rows * bg->cols, 1);
nv_matrix_zero(bg->av);
bg->sgm = nv_matrix_dup(bg->av);
return bg;
}
void
extract_dense(nv_matrix_t *vlad, int j,
const nv_matrix_t *image,
nv_keypoint_dense_t *dense,
int ndense
)
{
NV_ASSERT(vlad->n == DIM);
int desc_m;
nv_matrix_t *key_vec;
nv_matrix_t *desc_vec;
nv_matrix_t *resize, *gray, *smooth;
int i;
int km = 0;
if (m_fit_area == 0) {
float scale = IMG_SIZE() / (float)NV_MAX(image->rows, image->cols);
resize = nv_matrix3d_alloc(3, (int)(image->rows * scale),
(int)(image->cols * scale));
} else {
float axis_ratio = (float)image->rows / image->cols;
int new_cols = (int)sqrtf(m_fit_area / axis_ratio);
int new_rows = (int)((float)m_fit_area / new_cols);
resize = nv_matrix3d_alloc(3, new_rows, new_cols);
}
gray = nv_matrix3d_alloc(1, resize->rows, resize->cols);
smooth = nv_matrix3d_alloc(1, resize->rows, resize->cols);
for (i = 0; i < ndense; ++i) {
km += dense[i].rows * dense[i].cols;
}
km *= 2;
key_vec = nv_matrix_alloc(NV_KEYPOINT_KEYPOINT_N, km);
desc_vec = nv_matrix_alloc(NV_KEYPOINT_DESC_N, km);
nv_resize(resize, image);
nv_gray(gray, resize);
nv_gaussian5x5(smooth, 0, gray, 0);
nv_matrix_zero(desc_vec);
nv_matrix_zero(key_vec);
desc_m = nv_keypoint_dense_ex(m_ctx, key_vec, desc_vec, smooth, 0,
dense, ndense);
feature_vector(vlad, j, key_vec, desc_vec, desc_m);
nv_matrix_free(&gray);
nv_matrix_free(&resize);
nv_matrix_free(&smooth);
nv_matrix_free(&key_vec);
nv_matrix_free(&desc_vec);
}
int
t30_set_dev_param(build_image_context *context,
uint32_t index,
parse_token token,
uint32_t value)
{
nvboot_config_table *bct = NULL;
bct = (nvboot_config_table *)(context->bct);
assert(context != NULL);
assert(bct != NULL);
bct->num_param_sets = NV_MAX(bct->num_param_sets, index + 1);
switch (token) {
CASE_SET_DEV_PARAM(nand, clock_divider);
CASE_SET_DEV_PARAM(nand, block_size_log2);
CASE_SET_DEV_PARAM(nand, page_size_log2);
CASE_SET_DEV_PARAM(nand, async_timing0);
CASE_SET_DEV_PARAM(nand, async_timing1);
CASE_SET_DEV_PARAM(nand, async_timing2);
CASE_SET_DEV_PARAM(nand, async_timing3);
CASE_SET_DEV_PARAM(nand, sddr_timing0);
CASE_SET_DEV_PARAM(nand, sddr_timing1);
CASE_SET_DEV_PARAM(nand, tddr_timing0);
CASE_SET_DEV_PARAM(nand, tddr_timing1);
CASE_SET_DEV_PARAM(nand, fbio_dqsib_dly_byte);
CASE_SET_DEV_PARAM(nand, fbio_quse_dly_byte);
CASE_SET_DEV_PARAM(nand, fbio_cfg_quse_late);
CASE_SET_DEV_PARAM(nand, disable_sync_ddr);
CASE_SET_DEV_PARAM(sdmmc, clock_divider);
CASE_SET_DEV_PARAM(sdmmc, data_width);
CASE_SET_DEV_PARAM(sdmmc, max_power_class_supported);
CASE_SET_DEV_PARAM(sdmmc, sd_controller);
CASE_SET_DEV_PARAM(spiflash, clock_source);
CASE_SET_DEV_PARAM(spiflash, clock_divider);
CASE_SET_DEV_PARAM(spiflash, read_command_type_fast);
case token_dev_type:
bct->dev_type[index] = value;
break;
default:
return -ENODATA;
}
return 0;
}
static void ctk_banner_size_request(
GtkWidget *widget,
GtkRequisition *requisition
)
{
CtkBanner *ctk_banner = CTK_BANNER(widget);
requisition->width = NV_MAX(400,
ctk_banner->logo->w +
ctk_banner->artwork.w +
ctk_banner->logo_pad_x +
ctk_banner->artwork_pad_x);
requisition->height = ctk_banner->background->h;
}
int
main(void)
{
nv_matrix_t *data = nv_load_matrix_bin("train_data.mat");
nv_matrix_t *labels = nv_load_matrix_bin("train_labels.mat");
nv_matrix_t *test_data = nv_load_matrix_bin("test_data.mat");
nv_matrix_t *test_labels = nv_load_matrix_bin("test_labels.mat");
int i, ok;
int k = 0;
nv_lr_t *lr;
printf("train: %d, %ddim\ntest: %d\n",
data->m,
data->n,
test_data->m
);
ok = 0;
for (i = 0; i < labels->m; ++i) {
k = NV_MAX(k, NV_MAT_VI(labels, i, 0));
}
k += 1;
lr = nv_lr_alloc(data->n, k);
nv_lr_progress(1);
nv_lr_init(lr, data);
nv_lr_train(lr,
data, labels,
NV_LR_PARAM(300, 0.0001f, NV_LR_REG_L2, 0.01f, 0));
//NV_LR_PARAM(100, 0.1e-10f, NV_LR_REG_L2, 0.01, 0));
ok = 0;
for (i = 0; i < test_data->m; ++i) {
if (nv_lr_predict_label(lr, test_data, i) == NV_MAT_VI(test_labels, i, 0)) {
++ok;
}
}
printf("Accuracy = %f%% (%d/%d)\n",
(float)ok / test_data->m * 100.0f,
ok, test_data->m);
nv_matrix_free(&data);
nv_matrix_free(&labels);
nv_matrix_free(&test_data);
nv_matrix_free(&test_labels);
nv_lr_free(&lr);
fflush(stdout);
return 0;
}
void
nv_histgram_equalization(nv_matrix_t *eq, const nv_matrix_t *img, int channel)
{
float freq[256] = {0};
float fm;
int m, i;
float min_freq = FLT_MAX;
NV_ASSERT(eq->m == img->m);
if (img->m == 0) {
nv_matrix_zero(eq);
return ;
}
// freq
fm = 1.0f / (float )img->m;
for (m = 0; m < img->m; ++m) {
int idx = (int)NV_MAT_V(img, m, channel);
freq[idx] += 1.0f;
}
for (i = 1; i < 256; ++i) {
freq[i] = freq[i] + freq[i - 1];
}
for (i = 0; i < 256; ++i) {
freq[i] *= fm;
if (freq[i] < min_freq) {
min_freq = freq[i];
}
}
if (min_freq == 1.0) {
min_freq = 0.999999f;
}
// equalization
for (m = 0; m < img->m; ++m) {
int idx = (int)NV_MAT_V(img, m, channel);
float v = (freq[idx] - min_freq) * 255.0f / (1.0f - min_freq);//255.0f * freq[idx];
v = NV_MIN(NV_MAX(v, 0.0f), 255.0f);
NV_MAT_V(eq, m, channel) = v;
}
}
void t114_init_bad_block_table(build_image_context *context)
{
u_int32_t bytes_per_entry;
nvboot_badblock_table *table;
nvboot_config_table *bct;
bct = (nvboot_config_table *)(context->bct);
assert(context != NULL);
assert(bct != NULL);
table = &bct->badblock_table;
bytes_per_entry = ICEIL(context->partition_size,
NVBOOT_BAD_BLOCK_TABLE_SIZE);
table->block_size_log2 = context->block_size_log2;
table->virtual_blk_size_log2 = NV_MAX(ceil_log2(bytes_per_entry),
table->block_size_log2);
table->entries_used = iceil_log2(context->partition_size,
table->virtual_blk_size_log2);
}
int
t114_set_sdram_param(build_image_context *context,
u_int32_t index,
parse_token token,
u_int32_t value)
{
nvboot_sdram_params *params;
nvboot_config_table *bct = NULL;
bct = (nvboot_config_table *)(context->bct);
assert(context != NULL);
assert(bct != NULL);
params = &(bct->sdram_params[index]);
/* Update the number of SDRAM parameter sets. */
bct->num_sdram_sets = NV_MAX(bct->num_sdram_sets, index + 1);
switch (token) {
CASE_SET_SDRAM_PARAM(memory_type);
CASE_SET_SDRAM_PARAM(pllm_input_divider);
CASE_SET_SDRAM_PARAM(pllm_feedback_divider);
CASE_SET_SDRAM_PARAM(pllm_stable_time);
CASE_SET_SDRAM_PARAM(pllm_setup_control);
CASE_SET_SDRAM_PARAM(pllm_select_div2);
CASE_SET_SDRAM_PARAM(pllm_pdlshift_ph45);
CASE_SET_SDRAM_PARAM(pllm_pdlshift_ph90);
CASE_SET_SDRAM_PARAM(pllm_pdlshift_ph135);
CASE_SET_SDRAM_PARAM(pllm_kcp);
CASE_SET_SDRAM_PARAM(pllm_kvco);
CASE_SET_SDRAM_PARAM(emc_bct_spare0);
CASE_SET_SDRAM_PARAM(emc_auto_cal_interval);
CASE_SET_SDRAM_PARAM(emc_auto_cal_config);
CASE_SET_SDRAM_PARAM(emc_auto_cal_config2);
CASE_SET_SDRAM_PARAM(emc_auto_cal_config3);
CASE_SET_SDRAM_PARAM(emc_auto_cal_wait);
CASE_SET_SDRAM_PARAM(emc_pin_program_wait);
CASE_SET_SDRAM_PARAM(emc_rc);
CASE_SET_SDRAM_PARAM(emc_rfc);
CASE_SET_SDRAM_PARAM(emc_rfc_slr);
CASE_SET_SDRAM_PARAM(emc_ras);
CASE_SET_SDRAM_PARAM(emc_rp);
CASE_SET_SDRAM_PARAM(emc_r2r);
CASE_SET_SDRAM_PARAM(emc_w2w);
CASE_SET_SDRAM_PARAM(emc_r2w);
CASE_SET_SDRAM_PARAM(emc_w2r);
CASE_SET_SDRAM_PARAM(emc_r2p);
CASE_SET_SDRAM_PARAM(emc_w2p);
CASE_SET_SDRAM_PARAM(emc_rd_rcd);
CASE_SET_SDRAM_PARAM(emc_wr_rcd);
CASE_SET_SDRAM_PARAM(emc_rrd);
CASE_SET_SDRAM_PARAM(emc_rext);
CASE_SET_SDRAM_PARAM(emc_wdv);
CASE_SET_SDRAM_PARAM(emc_wdv_mask);
CASE_SET_SDRAM_PARAM(emc_quse);
CASE_SET_SDRAM_PARAM(emc_ibdly);
CASE_SET_SDRAM_PARAM(emc_einput);
CASE_SET_SDRAM_PARAM(emc_einput_duration);
CASE_SET_SDRAM_PARAM(emc_puterm_extra);
CASE_SET_SDRAM_PARAM(emc_cdb_cntl1);
CASE_SET_SDRAM_PARAM(emc_cdb_cntl2);
CASE_SET_SDRAM_PARAM(emc_qrst);
CASE_SET_SDRAM_PARAM(emc_qsafe);
CASE_SET_SDRAM_PARAM(emc_rdv);
CASE_SET_SDRAM_PARAM(emc_rdv_mask);
CASE_SET_SDRAM_PARAM(emc_refresh);
CASE_SET_SDRAM_PARAM(emc_burst_refresh_num);
CASE_SET_SDRAM_PARAM(emc_pdex2wr);
CASE_SET_SDRAM_PARAM(emc_pdex2rd);
CASE_SET_SDRAM_PARAM(emc_pchg2pden);
CASE_SET_SDRAM_PARAM(emc_act2pden);
CASE_SET_SDRAM_PARAM(emc_ar2pden);
CASE_SET_SDRAM_PARAM(emc_rw2pden);
CASE_SET_SDRAM_PARAM(emc_txsr);
CASE_SET_SDRAM_PARAM(emc_tcke);
CASE_SET_SDRAM_PARAM(emc_tckesr);
CASE_SET_SDRAM_PARAM(emc_tpd);
CASE_SET_SDRAM_PARAM(emc_tfaw);
CASE_SET_SDRAM_PARAM(emc_trpab);
CASE_SET_SDRAM_PARAM(emc_tclkstable);
CASE_SET_SDRAM_PARAM(emc_tclkstop);
CASE_SET_SDRAM_PARAM(emc_trefbw);
CASE_SET_SDRAM_PARAM(emc_quse_extra);
CASE_SET_SDRAM_PARAM(emc_fbio_cfg5);
CASE_SET_SDRAM_PARAM(emc_fbio_cfg6);
CASE_SET_SDRAM_PARAM(emc_fbio_spare);
CASE_SET_SDRAM_PARAM(emc_mrs);
CASE_SET_SDRAM_PARAM(emc_emrs);
CASE_SET_SDRAM_PARAM(emc_emrs2);
CASE_SET_SDRAM_PARAM(emc_emrs3);
CASE_SET_SDRAM_PARAM(emc_mrw1);
CASE_SET_SDRAM_PARAM(emc_mrw2);
CASE_SET_SDRAM_PARAM(emc_mrw3);
CASE_SET_SDRAM_PARAM(emc_mrw4);
CASE_SET_SDRAM_PARAM(emc_mrw_reset_command);
CASE_SET_SDRAM_PARAM(emc_mrw_reset_ninit_wait);
CASE_SET_SDRAM_PARAM(emc_adr_cfg);
CASE_SET_SDRAM_PARAM(mc_emem_cfg);
CASE_SET_SDRAM_PARAM(emc_cfg);
CASE_SET_SDRAM_PARAM(emc_cfg2);
CASE_SET_SDRAM_PARAM(emc_dbg);
CASE_SET_SDRAM_PARAM(emc_cfg_dig_dll);
CASE_SET_SDRAM_PARAM(emc_cfg_dig_dll_period);
CASE_SET_SDRAM_PARAM(warm_boot_wait);
CASE_SET_SDRAM_PARAM(emc_ctt_term_ctrl);
CASE_SET_SDRAM_PARAM(emc_odt_write);
CASE_SET_SDRAM_PARAM(emc_odt_read);
CASE_SET_SDRAM_PARAM(emc_zcal_wait_cnt);
CASE_SET_SDRAM_PARAM(emc_zcal_mrw_cmd);
CASE_SET_SDRAM_PARAM(emc_mrs_reset_dll);
CASE_SET_SDRAM_PARAM(emc_mrs_reset_dll_wait);
CASE_SET_SDRAM_PARAM(emc_emrs_ddr2_dll_enable);
CASE_SET_SDRAM_PARAM(emc_mrs_ddr2_dll_reset);
CASE_SET_SDRAM_PARAM(emc_emrs_ddr2_ocd_calib);
CASE_SET_SDRAM_PARAM(emc_ddr2_wait);
CASE_SET_SDRAM_PARAM(pmc_ddr_pwr);
CASE_SET_SDRAM_PARAM(emc_clock_source);
CASE_SET_SDRAM_PARAM(emc_pin_extra_wait);
CASE_SET_SDRAM_PARAM(emc_timing_control_wait);
CASE_SET_SDRAM_PARAM(emc_wext);
CASE_SET_SDRAM_PARAM(emc_ctt);
CASE_SET_SDRAM_PARAM(emc_ctt_duration);
CASE_SET_SDRAM_PARAM(emc_prerefresh_req_cnt);
CASE_SET_SDRAM_PARAM(emc_txsr_dll);
CASE_SET_SDRAM_PARAM(emc_cfg_rsv);
CASE_SET_SDRAM_PARAM(emc_mrw_extra);
CASE_SET_SDRAM_PARAM(emc_warm_boot_mrw_extra);
CASE_SET_SDRAM_PARAM(emc_warm_boot_extramode_reg_write_enable);
CASE_SET_SDRAM_PARAM(emc_extramode_reg_write_enable);
CASE_SET_SDRAM_PARAM(emc_mrs_wait_cnt);
CASE_SET_SDRAM_PARAM(emc_mrs_wait_cnt2);
CASE_SET_SDRAM_PARAM(emc_cmd_q);
CASE_SET_SDRAM_PARAM(emc_mc2emc_q);
CASE_SET_SDRAM_PARAM(emc_dyn_self_ref_control);
CASE_SET_SDRAM_PARAM(ahb_arbitration_xbar_ctrl_meminit_done);
CASE_SET_SDRAM_PARAM(emc_dev_select);
CASE_SET_SDRAM_PARAM(emc_sel_dpd_ctrl);
CASE_SET_SDRAM_PARAM(emc_dll_xform_dqs0);
CASE_SET_SDRAM_PARAM(emc_dll_xform_dqs1);
CASE_SET_SDRAM_PARAM(emc_dll_xform_dqs2);
CASE_SET_SDRAM_PARAM(emc_dll_xform_dqs3);
CASE_SET_SDRAM_PARAM(emc_dll_xform_dqs4);
CASE_SET_SDRAM_PARAM(emc_dll_xform_dqs5);
CASE_SET_SDRAM_PARAM(emc_dll_xform_dqs6);
CASE_SET_SDRAM_PARAM(emc_dll_xform_dqs7);
CASE_SET_SDRAM_PARAM(emc_dll_xform_quse0);
CASE_SET_SDRAM_PARAM(emc_dll_xform_quse1);
CASE_SET_SDRAM_PARAM(emc_dll_xform_quse2);
CASE_SET_SDRAM_PARAM(emc_dll_xform_quse3);
CASE_SET_SDRAM_PARAM(emc_dll_xform_quse4);
CASE_SET_SDRAM_PARAM(emc_dll_xform_quse5);
CASE_SET_SDRAM_PARAM(emc_dll_xform_quse6);
CASE_SET_SDRAM_PARAM(emc_dll_xform_quse7);
CASE_SET_SDRAM_PARAM(emc_dll_xform_addr0);
CASE_SET_SDRAM_PARAM(emc_dll_xform_addr1);
CASE_SET_SDRAM_PARAM(emc_dll_xform_addr2);
CASE_SET_SDRAM_PARAM(emc_dli_trim_tx_dqs0);
CASE_SET_SDRAM_PARAM(emc_dli_trim_tx_dqs1);
CASE_SET_SDRAM_PARAM(emc_dli_trim_tx_dqs2);
CASE_SET_SDRAM_PARAM(emc_dli_trim_tx_dqs3);
CASE_SET_SDRAM_PARAM(emc_dli_trim_tx_dqs4);
CASE_SET_SDRAM_PARAM(emc_dli_trim_tx_dqs5);
CASE_SET_SDRAM_PARAM(emc_dli_trim_tx_dqs6);
CASE_SET_SDRAM_PARAM(emc_dli_trim_tx_dqs7);
CASE_SET_SDRAM_PARAM(emc_dll_xform_dq0);
CASE_SET_SDRAM_PARAM(emc_dll_xform_dq1);
CASE_SET_SDRAM_PARAM(emc_dll_xform_dq2);
CASE_SET_SDRAM_PARAM(emc_dll_xform_dq3);
CASE_SET_SDRAM_PARAM(emc_zcal_interval);
CASE_SET_SDRAM_PARAM(emc_zcal_init_dev0);
CASE_SET_SDRAM_PARAM(emc_zcal_init_dev1);
CASE_SET_SDRAM_PARAM(emc_zcal_init_wait);
CASE_SET_SDRAM_PARAM(emc_zcal_warm_cold_boot_enables);
CASE_SET_SDRAM_PARAM(emc_mrw_lpddr2zcal_warm_boot);
CASE_SET_SDRAM_PARAM(emc_zqcal_ddr3_warm_boot);
CASE_SET_SDRAM_PARAM(emc_zcal_warm_boot_wait);
CASE_SET_SDRAM_PARAM(emc_mrs_warm_boot_enable);
CASE_SET_SDRAM_PARAM(emc_mrs_extra);
CASE_SET_SDRAM_PARAM(emc_warm_boot_mrs_extra);
CASE_SET_SDRAM_PARAM(emc_clken_override);
CASE_SET_SDRAM_PARAM(emc_extra_refresh_num);
CASE_SET_SDRAM_PARAM(emc_clken_override_allwarm_boot);
CASE_SET_SDRAM_PARAM(mc_clken_override_allwarm_boot);
CASE_SET_SDRAM_PARAM(emc_cfg_dig_dll_period_warm_boot);
CASE_SET_SDRAM_PARAM(pmc_vddp_sel);
CASE_SET_SDRAM_PARAM(pmc_ddr_cfg);
CASE_SET_SDRAM_PARAM(pmc_io_dpd_req);
CASE_SET_SDRAM_PARAM(pmc_io_dpd2_req);
CASE_SET_SDRAM_PARAM(pmc_reg_short);
CASE_SET_SDRAM_PARAM(pmc_eno_vtt_gen);
CASE_SET_SDRAM_PARAM(pmc_no_io_power);
CASE_SET_SDRAM_PARAM(emc_xm2cmd_pad_ctrl);
CASE_SET_SDRAM_PARAM(emc_xm2cmd_pad_ctrl2);
CASE_SET_SDRAM_PARAM(emc_xm2cmd_pad_ctrl3);
CASE_SET_SDRAM_PARAM(emc_xm2cmd_pad_ctrl4);
CASE_SET_SDRAM_PARAM(emc_xm2dqs_pad_ctrl);
CASE_SET_SDRAM_PARAM(emc_xm2dqs_pad_ctrl2);
CASE_SET_SDRAM_PARAM(emc_xm2dqs_pad_ctrl3);
CASE_SET_SDRAM_PARAM(emc_xm2dqs_pad_ctrl4);
CASE_SET_SDRAM_PARAM(emc_xm2dq_pad_ctrl);
CASE_SET_SDRAM_PARAM(emc_xm2dq_pad_ctrl2);
CASE_SET_SDRAM_PARAM(emc_xm2clk_pad_ctrl);
CASE_SET_SDRAM_PARAM(emc_xm2clk_pad_ctrl2);
CASE_SET_SDRAM_PARAM(emc_xm2comp_pad_ctrl);
CASE_SET_SDRAM_PARAM(emc_xm2vttgen_pad_ctrl);
CASE_SET_SDRAM_PARAM(emc_xm2vttgen_pad_ctrl2);
CASE_SET_SDRAM_PARAM(emc_acpd_control);
CASE_SET_SDRAM_PARAM(emc_swizzle_rank0_byte_cfg);
CASE_SET_SDRAM_PARAM(emc_swizzle_rank0_byte0);
CASE_SET_SDRAM_PARAM(emc_swizzle_rank0_byte1);
CASE_SET_SDRAM_PARAM(emc_swizzle_rank0_byte2);
CASE_SET_SDRAM_PARAM(emc_swizzle_rank0_byte3);
CASE_SET_SDRAM_PARAM(emc_swizzle_rank1_byte_cfg);
CASE_SET_SDRAM_PARAM(emc_swizzle_rank1_byte0);
CASE_SET_SDRAM_PARAM(emc_swizzle_rank1_byte1);
CASE_SET_SDRAM_PARAM(emc_swizzle_rank1_byte2);
CASE_SET_SDRAM_PARAM(emc_swizzle_rank1_byte3);
CASE_SET_SDRAM_PARAM(emc_addr_swizzle_stack1a);
CASE_SET_SDRAM_PARAM(emc_addr_swizzle_stack1b);
CASE_SET_SDRAM_PARAM(emc_addr_swizzle_stack2a);
CASE_SET_SDRAM_PARAM(emc_addr_swizzle_stack2b);
CASE_SET_SDRAM_PARAM(emc_addr_swizzle_stack3);
CASE_SET_SDRAM_PARAM(emc_dsr_vttgen_drv);
CASE_SET_SDRAM_PARAM(emc_txdsrvttgen);
CASE_SET_SDRAM_PARAM(mc_emem_adr_cfg);
CASE_SET_SDRAM_PARAM(mc_emem_adr_cfg_dev0);
CASE_SET_SDRAM_PARAM(mc_emem_adr_cfg_dev1);
CASE_SET_SDRAM_PARAM(mc_emem_adr_cfg_channel_mask);
CASE_SET_SDRAM_PARAM(mc_emem_adr_cfg_channel_mask_propagation_count);
CASE_SET_SDRAM_PARAM(mc_emem_adr_cfg_bank_mask0);
CASE_SET_SDRAM_PARAM(mc_emem_adr_cfg_bank_mask1);
CASE_SET_SDRAM_PARAM(mc_emem_adr_cfg_bank_mask2);
CASE_SET_SDRAM_PARAM(mc_emem_arb_cfg);
CASE_SET_SDRAM_PARAM(mc_emem_arb_outstanding_req);
CASE_SET_SDRAM_PARAM(mc_emem_arb_timing_rcd);
CASE_SET_SDRAM_PARAM(mc_emem_arb_timing_rp);
CASE_SET_SDRAM_PARAM(mc_emem_arb_timing_rc);
CASE_SET_SDRAM_PARAM(mc_emem_arb_timing_ras);
CASE_SET_SDRAM_PARAM(mc_emem_arb_timing_faw);
CASE_SET_SDRAM_PARAM(mc_emem_arb_timing_rrd);
CASE_SET_SDRAM_PARAM(mc_emem_arb_timing_rap2pre);
CASE_SET_SDRAM_PARAM(mc_emem_arb_timing_wap2pre);
CASE_SET_SDRAM_PARAM(mc_emem_arb_timing_r2r);
CASE_SET_SDRAM_PARAM(mc_emem_arb_timing_w2w);
CASE_SET_SDRAM_PARAM(mc_emem_arb_timing_r2w);
CASE_SET_SDRAM_PARAM(mc_emem_arb_timing_w2r);
CASE_SET_SDRAM_PARAM(mc_emem_arb_da_turns);
CASE_SET_SDRAM_PARAM(mc_emem_arb_da_covers);
CASE_SET_SDRAM_PARAM(mc_emem_arb_misc0);
CASE_SET_SDRAM_PARAM(mc_emem_arb_misc1);
CASE_SET_SDRAM_PARAM(mc_emem_arb_ring1_throttle);
CASE_SET_SDRAM_PARAM(mc_emem_arb_override);
CASE_SET_SDRAM_PARAM(mc_emem_arb_rsv);
CASE_SET_SDRAM_PARAM(mc_clken_override);
CASE_SET_SDRAM_PARAM(mc_emc_reg_mode);
CASE_SET_SDRAM_PARAM(mc_video_protect_bom);
CASE_SET_SDRAM_PARAM(mc_video_protect_size_mb);
CASE_SET_SDRAM_PARAM(mc_video_protect_vpr_override);
CASE_SET_SDRAM_PARAM(mc_sec_carveout_bom);
CASE_SET_SDRAM_PARAM(mc_sec_carveout_size_mb);
CASE_SET_SDRAM_PARAM(mc_video_protect_write_access);
CASE_SET_SDRAM_PARAM(mc_sec_carveout_protect_write_access);
CASE_SET_SDRAM_PARAM(emc_ca_training_enable);
CASE_SET_SDRAM_PARAM(emc_ca_training_timing_cntl1);
CASE_SET_SDRAM_PARAM(emc_ca_training_timing_cntl2);
CASE_SET_SDRAM_PARAM(swizzle_rank_byte_encode);
CASE_SET_SDRAM_PARAM(boot_rom_patch_control);
CASE_SET_SDRAM_PARAM(boot_rom_patch_data);
CASE_SET_SDRAM_PARAM(ch1_emc_dll_xform_dqs0);
CASE_SET_SDRAM_PARAM(ch1_emc_dll_xform_dqs1);
CASE_SET_SDRAM_PARAM(ch1_emc_dll_xform_dqs2);
CASE_SET_SDRAM_PARAM(ch1_emc_dll_xform_dqs3);
CASE_SET_SDRAM_PARAM(ch1_emc_dll_xform_dqs4);
CASE_SET_SDRAM_PARAM(ch1_emc_dll_xform_dqs5);
CASE_SET_SDRAM_PARAM(ch1_emc_dll_xform_dqs6);
CASE_SET_SDRAM_PARAM(ch1_emc_dll_xform_dqs7);
CASE_SET_SDRAM_PARAM(ch1_emc_dll_xform_quse0);
CASE_SET_SDRAM_PARAM(ch1_emc_dll_xform_quse1);
CASE_SET_SDRAM_PARAM(ch1_emc_dll_xform_quse2);
CASE_SET_SDRAM_PARAM(ch1_emc_dll_xform_quse3);
CASE_SET_SDRAM_PARAM(ch1_emc_dll_xform_quse4);
CASE_SET_SDRAM_PARAM(ch1_emc_dll_xform_quse5);
CASE_SET_SDRAM_PARAM(ch1_emc_dll_xform_quse6);
CASE_SET_SDRAM_PARAM(ch1_emc_dll_xform_quse7);
CASE_SET_SDRAM_PARAM(ch1_emc_dli_trim_tx_dqs0);
CASE_SET_SDRAM_PARAM(ch1_emc_dli_trim_tx_dqs1);
CASE_SET_SDRAM_PARAM(ch1_emc_dli_trim_tx_dqs2);
CASE_SET_SDRAM_PARAM(ch1_emc_dli_trim_tx_dqs3);
CASE_SET_SDRAM_PARAM(ch1_emc_dli_trim_tx_dqs4);
CASE_SET_SDRAM_PARAM(ch1_emc_dli_trim_tx_dqs5);
CASE_SET_SDRAM_PARAM(ch1_emc_dli_trim_tx_dqs6);
CASE_SET_SDRAM_PARAM(ch1_emc_dli_trim_tx_dqs7);
CASE_SET_SDRAM_PARAM(ch1_emc_dll_xform_dq0);
CASE_SET_SDRAM_PARAM(ch1_emc_dll_xform_dq1);
CASE_SET_SDRAM_PARAM(ch1_emc_dll_xform_dq2);
CASE_SET_SDRAM_PARAM(ch1_emc_dll_xform_dq3);
CASE_SET_SDRAM_PARAM(ch1_emc_swizzle_rank0_byte_cfg);
CASE_SET_SDRAM_PARAM(ch1_emc_swizzle_rank0_byte0);
CASE_SET_SDRAM_PARAM(ch1_emc_swizzle_rank0_byte1);
CASE_SET_SDRAM_PARAM(ch1_emc_swizzle_rank0_byte2);
CASE_SET_SDRAM_PARAM(ch1_emc_swizzle_rank0_byte3);
CASE_SET_SDRAM_PARAM(ch1_emc_swizzle_rank1_byte_cfg);
CASE_SET_SDRAM_PARAM(ch1_emc_swizzle_rank1_byte0);
CASE_SET_SDRAM_PARAM(ch1_emc_swizzle_rank1_byte1);
CASE_SET_SDRAM_PARAM(ch1_emc_swizzle_rank1_byte2);
CASE_SET_SDRAM_PARAM(ch1_emc_swizzle_rank1_byte3);
CASE_SET_SDRAM_PARAM(ch1_emc_addr_swizzle_stack1a);
CASE_SET_SDRAM_PARAM(ch1_emc_addr_swizzle_stack1b);
CASE_SET_SDRAM_PARAM(ch1_emc_addr_swizzle_stack2a);
CASE_SET_SDRAM_PARAM(ch1_emc_addr_swizzle_stack2b);
CASE_SET_SDRAM_PARAM(ch1_emc_addr_swizzle_stack3);
CASE_SET_SDRAM_PARAM(ch1_emc_auto_cal_config);
CASE_SET_SDRAM_PARAM(ch1_emc_auto_cal_config2);
CASE_SET_SDRAM_PARAM(ch1_emc_auto_cal_config3);
CASE_SET_SDRAM_PARAM(ch1_emc_cdb_cntl1);
CASE_SET_SDRAM_PARAM(ch1_emc_dll_xform_addr0);
CASE_SET_SDRAM_PARAM(ch1_emc_dll_xform_addr1);
CASE_SET_SDRAM_PARAM(ch1_emc_dll_xform_addr2);
CASE_SET_SDRAM_PARAM(ch1_emc_fbio_spare);
CASE_SET_SDRAM_PARAM(ch1_emc_xm2_clk_pad_ctrl);
CASE_SET_SDRAM_PARAM(ch1_emc_xm2_clk_pad_ctrl2);
CASE_SET_SDRAM_PARAM(ch1_emc_xm2_cmd_pad_ctrl2);
CASE_SET_SDRAM_PARAM(ch1_emc_xm2_cmd_pad_ctrl3);
CASE_SET_SDRAM_PARAM(ch1_emc_xm2_cmd_pad_ctrl4);
CASE_SET_SDRAM_PARAM(ch1_emc_xm2_dq_pad_ctrl);
CASE_SET_SDRAM_PARAM(ch1_emc_xm2_dq_pad_ctrl2);
CASE_SET_SDRAM_PARAM(ch1_emc_xm2_dqs_pad_ctrl);
CASE_SET_SDRAM_PARAM(ch1_emc_xm2_dqs_pad_ctrl3);
CASE_SET_SDRAM_PARAM(ch1_emc_xm2_dqs_pad_ctrl4);
DEFAULT();
}
return 0;
}
void NvRmPrivCoreVoltageInit(NvRmDeviceHandle hRmDevice)
{
NvU32 CoreRailAddress, RtcRailAddress, CpuRailAddress;
const NvOdmPeripheralConnectivity* pPmuRail;
NvRmMilliVolts CurrentCoreMv = 0;
NvRmMilliVolts CurrentRtcMv = 0;
NvRmMilliVolts NominalCoreMv = NvRmPrivGetNominalMV(hRmDevice);
NV_ASSERT(hRmDevice);
if (NvRmPrivGetExecPlatform(hRmDevice) != ExecPlatform_Soc)
{
return;
}
pPmuRail = NvOdmPeripheralGetGuid(NV_VDD_CORE_ODM_ID);
NV_ASSERT(pPmuRail);
NV_ASSERT(pPmuRail->NumAddress);
CoreRailAddress = pPmuRail->AddressList[0].Address;
pPmuRail = NvOdmPeripheralGetGuid(NV_VDD_RTC_ODM_ID);
NV_ASSERT(pPmuRail);
NV_ASSERT(pPmuRail->NumAddress);
RtcRailAddress = pPmuRail->AddressList[0].Address;
// This function is called during PMU initialization when current (= boot)
// core voltage is expected to be within one safe step from nominal, and
// RTC voltage must be within one safe step from the core. Set nominal
// voltage (bump PMU ref count), if the above conditions are true.
NvRmPmuGetVoltage(hRmDevice, CoreRailAddress, &CurrentCoreMv);
NvRmPmuGetVoltage(hRmDevice, RtcRailAddress, &CurrentRtcMv);
if((CurrentCoreMv > (NominalCoreMv + NVRM_SAFE_VOLTAGE_STEP_MV)) ||
((CurrentCoreMv + NVRM_SAFE_VOLTAGE_STEP_MV) < NominalCoreMv))
{
NV_ASSERT(!"Unexpected initial core voltage");
return;
}
if((CurrentRtcMv > (CurrentCoreMv + NVRM_SAFE_VOLTAGE_STEP_MV)) ||
((CurrentRtcMv + NVRM_SAFE_VOLTAGE_STEP_MV) < CurrentCoreMv))
{
NV_ASSERT(!"Unexpected initial RTC voltage");
return;
}
// If core voltage is going up, update it before CPU
if (CurrentCoreMv <= NominalCoreMv)
{
NvRmPmuSetVoltage(hRmDevice, RtcRailAddress, NominalCoreMv, NULL);
NvRmPmuSetVoltage(hRmDevice, CoreRailAddress, NominalCoreMv, NULL);
}
// If the platform has dedicated CPU voltage rail, make sure it is set to
// nominal level as well (bump PMU ref count along the way).
if (NvRmPrivIsCpuRailDedicated(hRmDevice))
{
NvRmPmuVddRailCapabilities cap;
NvRmMilliVolts NominalCpuMv = NvRmPrivModuleVscaleGetMV(
hRmDevice, NvRmModuleID_Cpu,
NvRmPrivGetSocClockLimits(NvRmModuleID_Cpu)->MaxKHz);
pPmuRail = NvOdmPeripheralGetGuid(NV_VDD_CPU_ODM_ID);
NV_ASSERT(pPmuRail);
NV_ASSERT(pPmuRail->NumAddress);
CpuRailAddress = pPmuRail->AddressList[0].Address;
// Clip nominal CPU voltage to minimal PMU capabilities, and set it.
// (note: PMU with CPU voltage range above nominal is temporary
// accepted exception; for other limit violations: PMU maximum level
// for CPU is not high enough, or PMU core range does not include
// nominal core voltage, assert is fired inside NvRmPmuSetVoltage())
NvRmPmuGetCapabilities(hRmDevice, CpuRailAddress, &cap);
NominalCpuMv = NV_MAX(NominalCpuMv, cap.MinMilliVolts);
NvRmPmuSetVoltage(hRmDevice, CpuRailAddress, NominalCpuMv, NULL);
if (CurrentCoreMv > NominalCoreMv)
NvOsWaitUS(NVRM_CPU_TO_CORE_DOWN_US); // delay if core to go down
}
// If core voltage is going down, update it after CPU voltage
if (CurrentCoreMv > NominalCoreMv)
{
NvRmPmuSetVoltage(hRmDevice, RtcRailAddress, NominalCoreMv, NULL);
NvRmPmuSetVoltage(hRmDevice, CoreRailAddress, NominalCoreMv, NULL);
}
// Always On System I/O, DDR IO and RX DDR (if exist) - set nominal,
// bump ref count
NvRmPrivPmuRailControl(hRmDevice, NV_VDD_SYS_ODM_ID, NV_TRUE);
NvRmPrivPmuRailControl(hRmDevice, NV_VDD_DDR_ODM_ID, NV_TRUE);
if (NvOdmPeripheralGetGuid(NV_VDD_DDR_RX_ODM_ID))
NvRmPrivPmuRailControl(hRmDevice, NV_VDD_DDR_RX_ODM_ID, NV_TRUE);
}
int
t30_set_sdram_param(build_image_context *context,
uint32_t index,
parse_token token,
uint32_t value)
{
nvboot_sdram_params *params;
nvboot_config_table *bct = NULL;
bct = (nvboot_config_table *)(context->bct);
assert(context != NULL);
assert(bct != NULL);
params = &(bct->sdram_params[index]);
/* Update the number of SDRAM parameter sets. */
bct->num_sdram_sets = NV_MAX(bct->num_sdram_sets, index + 1);
switch (token) {
CASE_SET_SDRAM_PARAM(memory_type);
CASE_SET_SDRAM_PARAM(pllm_charge_pump_setup_ctrl);
CASE_SET_SDRAM_PARAM(pllm_loop_filter_setup_ctrl);
CASE_SET_SDRAM_PARAM(pllm_input_divider);
CASE_SET_SDRAM_PARAM(pllm_feedback_divider);
CASE_SET_SDRAM_PARAM(pllm_post_divider);
CASE_SET_SDRAM_PARAM(pllm_stable_time);
CASE_SET_SDRAM_PARAM(emc_clock_divider);
CASE_SET_SDRAM_PARAM(emc_auto_cal_interval);
CASE_SET_SDRAM_PARAM(emc_auto_cal_config);
CASE_SET_SDRAM_PARAM(emc_auto_cal_wait);
CASE_SET_SDRAM_PARAM(emc_pin_program_wait);
CASE_SET_SDRAM_PARAM(emc_rc);
CASE_SET_SDRAM_PARAM(emc_rfc);
CASE_SET_SDRAM_PARAM(emc_ras);
CASE_SET_SDRAM_PARAM(emc_rp);
CASE_SET_SDRAM_PARAM(emc_r2w);
CASE_SET_SDRAM_PARAM(emc_w2r);
CASE_SET_SDRAM_PARAM(emc_r2p);
CASE_SET_SDRAM_PARAM(emc_w2p);
CASE_SET_SDRAM_PARAM(emc_rd_rcd);
CASE_SET_SDRAM_PARAM(emc_wr_rcd);
CASE_SET_SDRAM_PARAM(emc_rrd);
CASE_SET_SDRAM_PARAM(emc_rext);
CASE_SET_SDRAM_PARAM(emc_wdv);
CASE_SET_SDRAM_PARAM(emc_quse);
CASE_SET_SDRAM_PARAM(emc_qrst);
CASE_SET_SDRAM_PARAM(emc_qsafe);
CASE_SET_SDRAM_PARAM(emc_rdv);
CASE_SET_SDRAM_PARAM(emc_refresh);
CASE_SET_SDRAM_PARAM(emc_burst_refresh_num);
CASE_SET_SDRAM_PARAM(emc_pdex2wr);
CASE_SET_SDRAM_PARAM(emc_pdex2rd);
CASE_SET_SDRAM_PARAM(emc_pchg2pden);
CASE_SET_SDRAM_PARAM(emc_act2pden);
CASE_SET_SDRAM_PARAM(emc_ar2pden);
CASE_SET_SDRAM_PARAM(emc_rw2pden);
CASE_SET_SDRAM_PARAM(emc_txsr);
CASE_SET_SDRAM_PARAM(emc_tcke);
CASE_SET_SDRAM_PARAM(emc_tfaw);
CASE_SET_SDRAM_PARAM(emc_trpab);
CASE_SET_SDRAM_PARAM(emc_tclkstable);
CASE_SET_SDRAM_PARAM(emc_tclkstop);
CASE_SET_SDRAM_PARAM(emc_trefbw);
CASE_SET_SDRAM_PARAM(emc_quse_extra);
CASE_SET_SDRAM_PARAM(emc_fbio_cfg5);
CASE_SET_SDRAM_PARAM(emc_fbio_cfg6);
CASE_SET_SDRAM_PARAM(emc_fbio_spare);
CASE_SET_SDRAM_PARAM(emc_mrs);
CASE_SET_SDRAM_PARAM(emc_emrs);
CASE_SET_SDRAM_PARAM(emc_mrw1);
CASE_SET_SDRAM_PARAM(emc_mrw2);
CASE_SET_SDRAM_PARAM(emc_mrw3);
CASE_SET_SDRAM_PARAM(emc_mrw_reset_command);
CASE_SET_SDRAM_PARAM(emc_mrw_reset_ninit_wait);
CASE_SET_SDRAM_PARAM(emc_adr_cfg);
CASE_SET_SDRAM_PARAM(mc_emem_cfg);
CASE_SET_SDRAM_PARAM(emc_cfg);
CASE_SET_SDRAM_PARAM(emc_cfg2);
CASE_SET_SDRAM_PARAM(emc_dbg);
CASE_SET_SDRAM_PARAM(emc_cfg_dig_dll);
CASE_SET_SDRAM_PARAM(emc_cfg_dig_dll_period);
CASE_SET_SDRAM_PARAM(warm_boot_wait);
CASE_SET_SDRAM_PARAM(emc_ctt_term_ctrl);
CASE_SET_SDRAM_PARAM(emc_odt_write);
CASE_SET_SDRAM_PARAM(emc_odt_read);
CASE_SET_SDRAM_PARAM(emc_zcal_wait_cnt);
CASE_SET_SDRAM_PARAM(emc_zcal_mrw_cmd);
CASE_SET_SDRAM_PARAM(emc_mrs_reset_dll);
CASE_SET_SDRAM_PARAM(emc_mrs_reset_dll_wait);
CASE_SET_SDRAM_PARAM(emc_emrs_emr2);
CASE_SET_SDRAM_PARAM(emc_emrs_emr3);
CASE_SET_SDRAM_PARAM(emc_emrs_ddr2_dll_enable);
CASE_SET_SDRAM_PARAM(emc_mrs_ddr2_dll_reset);
CASE_SET_SDRAM_PARAM(emc_emrs_ddr2_ocd_calib);
CASE_SET_SDRAM_PARAM(emc_ddr2_wait);
CASE_SET_SDRAM_PARAM(pmc_ddr_pwr);
CASE_SET_SDRAM_PARAM(emc_clock_source);
CASE_SET_SDRAM_PARAM(emc_clock_use_pll_mud);
CASE_SET_SDRAM_PARAM(emc_pin_extra_wait);
CASE_SET_SDRAM_PARAM(emc_timing_control_wait);
CASE_SET_SDRAM_PARAM(emc_wext);
CASE_SET_SDRAM_PARAM(emc_ctt);
CASE_SET_SDRAM_PARAM(emc_ctt_duration);
CASE_SET_SDRAM_PARAM(emc_prerefresh_req_cnt);
CASE_SET_SDRAM_PARAM(emc_txsr_dll);
CASE_SET_SDRAM_PARAM(emc_cfg_rsv);
CASE_SET_SDRAM_PARAM(emc_mrw_extra);
CASE_SET_SDRAM_PARAM(emc_warm_boot_mrw1);
CASE_SET_SDRAM_PARAM(emc_warm_boot_mrw2);
CASE_SET_SDRAM_PARAM(emc_warm_boot_mrw3);
CASE_SET_SDRAM_PARAM(emc_warm_boot_mrw_extra);
CASE_SET_SDRAM_PARAM(emc_warm_boot_extramode_reg_write_enable);
CASE_SET_SDRAM_PARAM(emc_extramode_reg_write_enable);
CASE_SET_SDRAM_PARAM(emc_mrs_wait_cnt);
CASE_SET_SDRAM_PARAM(emc_cmd_q);
CASE_SET_SDRAM_PARAM(emc_mc2emc_q);
CASE_SET_SDRAM_PARAM(emc_dyn_self_ref_control);
CASE_SET_SDRAM_PARAM(ahb_arbitration_xbar_ctrl_meminit_done);
CASE_SET_SDRAM_PARAM(emc_dev_select);
CASE_SET_SDRAM_PARAM(emc_sel_dpd_ctrl);
CASE_SET_SDRAM_PARAM(emc_dll_xform_dqs0);
CASE_SET_SDRAM_PARAM(emc_dll_xform_dqs1);
CASE_SET_SDRAM_PARAM(emc_dll_xform_dqs2);
CASE_SET_SDRAM_PARAM(emc_dll_xform_dqs3);
CASE_SET_SDRAM_PARAM(emc_dll_xform_dqs4);
CASE_SET_SDRAM_PARAM(emc_dll_xform_dqs5);
CASE_SET_SDRAM_PARAM(emc_dll_xform_dqs6);
CASE_SET_SDRAM_PARAM(emc_dll_xform_dqs7);
CASE_SET_SDRAM_PARAM(emc_dll_xform_quse0);
CASE_SET_SDRAM_PARAM(emc_dll_xform_quse1);
CASE_SET_SDRAM_PARAM(emc_dll_xform_quse2);
CASE_SET_SDRAM_PARAM(emc_dll_xform_quse3);
CASE_SET_SDRAM_PARAM(emc_dll_xform_quse4);
CASE_SET_SDRAM_PARAM(emc_dll_xform_quse5);
CASE_SET_SDRAM_PARAM(emc_dll_xform_quse6);
CASE_SET_SDRAM_PARAM(emc_dll_xform_quse7);
CASE_SET_SDRAM_PARAM(emc_dli_trim_tx_dqs0);
CASE_SET_SDRAM_PARAM(emc_dli_trim_tx_dqs1);
CASE_SET_SDRAM_PARAM(emc_dli_trim_tx_dqs2);
CASE_SET_SDRAM_PARAM(emc_dli_trim_tx_dqs3);
CASE_SET_SDRAM_PARAM(emc_dli_trim_tx_dqs4);
CASE_SET_SDRAM_PARAM(emc_dli_trim_tx_dqs5);
CASE_SET_SDRAM_PARAM(emc_dli_trim_tx_dqs6);
CASE_SET_SDRAM_PARAM(emc_dli_trim_tx_dqs7);
CASE_SET_SDRAM_PARAM(emc_dll_xform_dq0);
CASE_SET_SDRAM_PARAM(emc_dll_xform_dq1);
CASE_SET_SDRAM_PARAM(emc_dll_xform_dq2);
CASE_SET_SDRAM_PARAM(emc_dll_xform_dq3);
CASE_SET_SDRAM_PARAM(emc_zcal_interval);
CASE_SET_SDRAM_PARAM(emc_zcal_init_dev0);
CASE_SET_SDRAM_PARAM(emc_zcal_init_dev1);
CASE_SET_SDRAM_PARAM(emc_zcal_init_wait);
CASE_SET_SDRAM_PARAM(emc_zcal_cold_boot_enable);
CASE_SET_SDRAM_PARAM(emc_zcal_warm_boot_enable);
CASE_SET_SDRAM_PARAM(emc_mrw_lpddr2zcal_warm_boot);
CASE_SET_SDRAM_PARAM(emc_zqcal_ddr3_warm_boot);
CASE_SET_SDRAM_PARAM(emc_zcal_warm_boot_wait);
CASE_SET_SDRAM_PARAM(emc_mrs_warm_boot_enable);
CASE_SET_SDRAM_PARAM(emc_mrs_extra);
CASE_SET_SDRAM_PARAM(emc_warm_boot_mrs);
CASE_SET_SDRAM_PARAM(emc_warm_boot_emrs);
CASE_SET_SDRAM_PARAM(emc_warm_boot_emr2);
CASE_SET_SDRAM_PARAM(emc_warm_boot_emr3);
CASE_SET_SDRAM_PARAM(emc_warm_boot_mrs_extra);
CASE_SET_SDRAM_PARAM(emc_clken_override);
CASE_SET_SDRAM_PARAM(emc_extra_refresh_num);
CASE_SET_SDRAM_PARAM(emc_clken_override_allwarm_boot);
CASE_SET_SDRAM_PARAM(mc_clken_override_allwarm_boot);
CASE_SET_SDRAM_PARAM(emc_cfg_dig_dll_period_warm_boot);
CASE_SET_SDRAM_PARAM(pmc_vddp_sel);
CASE_SET_SDRAM_PARAM(pmc_ddr_cfg);
CASE_SET_SDRAM_PARAM(pmc_io_dpd_req);
CASE_SET_SDRAM_PARAM(pmc_eno_vtt_gen);
CASE_SET_SDRAM_PARAM(pmc_no_io_power);
CASE_SET_SDRAM_PARAM(emc_xm2cmd_pad_ctrl);
CASE_SET_SDRAM_PARAM(emc_xm2cmd_pad_ctrl2);
CASE_SET_SDRAM_PARAM(emc_xm2dqs_pad_ctrl);
CASE_SET_SDRAM_PARAM(emc_xm2dqs_pad_ctrl2);
CASE_SET_SDRAM_PARAM(emc_xm2dqs_pad_ctrl3);
CASE_SET_SDRAM_PARAM(emc_xm2dq_pad_ctrl);
CASE_SET_SDRAM_PARAM(emc_xm2dq_pad_ctrl2);
CASE_SET_SDRAM_PARAM(emc_xm2clk_pad_ctrl);
CASE_SET_SDRAM_PARAM(emc_xm2comp_pad_ctrl);
CASE_SET_SDRAM_PARAM(emc_xm2vttgen_pad_ctrl);
CASE_SET_SDRAM_PARAM(emc_xm2vttgen_pad_ctrl2);
CASE_SET_SDRAM_PARAM(emc_xm2quse_pad_ctrl);
CASE_SET_SDRAM_PARAM(mc_emem_adr_cfg);
CASE_SET_SDRAM_PARAM(mc_emem_adr_cfg_dev0);
CASE_SET_SDRAM_PARAM(mc_emem_adr_cfg_dev1);
CASE_SET_SDRAM_PARAM(mc_emem_arb_cfg);
CASE_SET_SDRAM_PARAM(mc_emem_arb_outstanding_req);
CASE_SET_SDRAM_PARAM(mc_emem_arb_timing_rcd);
CASE_SET_SDRAM_PARAM(mc_emem_arb_timing_rp);
CASE_SET_SDRAM_PARAM(mc_emem_arb_timing_rc);
CASE_SET_SDRAM_PARAM(mc_emem_arb_timing_ras);
CASE_SET_SDRAM_PARAM(mc_emem_arb_timing_faw);
CASE_SET_SDRAM_PARAM(mc_emem_arb_timing_rrd);
CASE_SET_SDRAM_PARAM(mc_emem_arb_timing_rap2pre);
CASE_SET_SDRAM_PARAM(mc_emem_arb_timing_wap2pre);
CASE_SET_SDRAM_PARAM(mc_emem_arb_timing_r2r);
CASE_SET_SDRAM_PARAM(mc_emem_arb_timing_w2w);
CASE_SET_SDRAM_PARAM(mc_emem_arb_timing_r2w);
CASE_SET_SDRAM_PARAM(mc_emem_arb_timing_w2r);
CASE_SET_SDRAM_PARAM(mc_emem_arb_da_turns);
CASE_SET_SDRAM_PARAM(mc_emem_arb_da_covers);
CASE_SET_SDRAM_PARAM(mc_emem_arb_misc0);
CASE_SET_SDRAM_PARAM(mc_emem_arb_misc1);
CASE_SET_SDRAM_PARAM(mc_emem_arb_ring1_throttle);
CASE_SET_SDRAM_PARAM(mc_emem_arb_override);
CASE_SET_SDRAM_PARAM(mc_emem_arb_rsv);
CASE_SET_SDRAM_PARAM(mc_clken_override);
DEFAULT();
}
return 0;
}
void nv_shapecontext_feature(nv_shapecontext_t *sctx,
const nv_matrix_t *img,
float r
)
{
int m, row, col, pc, i, l;
nv_matrix_t *edge = nv_matrix3d_alloc(1, img->rows, img->cols);
nv_matrix_t *points = nv_matrix_alloc(2, img->m);
int *rand_idx = (int *)nv_malloc(sizeof(int) * img->m);
float u_x, u_y, p_x, p_y, r_e;
int pn;
// 細線化
nv_matrix_zero(points);
nv_shapecontext_edge_image(edge, img);
pc = 0;
u_x = 0.0f;
u_y = 0.0f;
for (row = 0; row < edge->rows; ++row) {
for (col = 0; col < edge->cols; ++col) {
if (NV_MAT3D_V(edge, row, col, 0) > 50.0f) {
NV_MAT_V(points, pc, 0) = (float)row;
NV_MAT_V(points, pc, 1) = (float)col;
++pc;
u_y += (float)row;
u_x += (float)col;
}
}
}
u_x /= pc;
u_y /= pc;
// 指定数の特徴にする（ランダム）
pn = NV_MIN(pc, sctx->sctx->list);
nv_shuffle_index(rand_idx, 0, pc);
#if 1
{
float max_x, max_y;
if (pc < sctx->sctx->list) {
// 足りないときはランダムに増やす
for (i = pc; i < sctx->sctx->list; ++i) {
rand_idx[i] = (int)(nv_rand() * pn);
}
}
pc = pn = sctx->sctx->list;
// 半径を求める
max_x = 0.0f;
max_y = 0.0f;
for (m = 0; m < pn; ++m) {
float yd = fabsf(NV_MAT_V(points, rand_idx[m], 0) - u_y);
float xd = fabsf(NV_MAT_V(points, rand_idx[m], 1) - u_x);
max_x = NV_MAX(max_x, xd);
max_y = NV_MAX(max_y, yd);
}
r = (float)img->rows/2.0f;//NV_MAX(max_x, max_y) * 1.0f;
}
#endif
// log(r) = 5の基底定数を求める
r_e = powf(r, 1.0f / NV_SC_LOG_R_BIN);
// histgramを計算する
sctx->n = pn;
nv_matrix_zero(sctx->sctx);
nv_matrix_zero(sctx->tan_angle);
for (l = 0; l < pn; ++l) {
// tangent angle
#if 0
float max_bin = 0.0f, min_bin = FLT_MAX;
float tan_angle = tangent_angle(
r,
NV_MAT_V(points, rand_idx[l], 0),
NV_MAT_V(points, rand_idx[l], 1),
points, pc);
#else
float tan_angle = 0.0f;
#endif
p_y = NV_MAT_V(points, rand_idx[l], 0);
p_x = NV_MAT_V(points, rand_idx[l], 1);
NV_MAT_V(sctx->tan_angle, l, 0) = tan_angle;
NV_MAT_V(sctx->coodinate, l, 0) = p_y;
NV_MAT_V(sctx->coodinate, l, 1) = p_x;
NV_MAT_V(sctx->radius, l, 0) = r;
// shape context
for (i = 0; i < pn; ++i) {
// # i ≠ l判定はとりあえずしない
float xd = NV_MAT_V(points, rand_idx[i], 1) - p_x;
float yd = NV_MAT_V(points, rand_idx[i], 0) - p_y;
//int row = i / img->rows;
//int col = i % img->rows;
//float xd = col - p_x;
//float yd = row - p_y;
float theta;
float log_r = logf(sqrtf(xd * xd + yd * yd)) / logf(r_e);
float atan_r = atan2f(xd, yd);
//if (NV_MAT3D_V(img, row, col, 0) == 0.0f) {
// continue;
//}
if (i == l) {
continue;
}
if (atan_r < 0.0f) {
atan_r = 2.0f * NV_PI + atan_r;
}
if (tan_angle > 0.0f) {
if (atan_r + tan_angle > 2.0f * NV_PI) {
atan_r = atan_r + tan_angle - 2.0f * NV_PI;
} else {
atan_r += tan_angle;
}
} else {
if (atan_r + tan_angle < 0.0f) {
atan_r = 2.0f * NV_PI + (atan_r + tan_angle);
} else {
atan_r += tan_angle;
}
}
theta = atan_r / (2.0f * NV_PI / NV_SC_THETA_BIN);
if (theta < NV_SC_THETA_BIN && log_r < NV_SC_LOG_R_BIN) {
NV_MAT3D_LIST_V(sctx->sctx, l, (int)log_r, (int)theta, 0) += 1.0f;
}
}
#if 0
for (row = 0; row < NV_SC_LOG_R_BIN; ++row) {
for (col = 0; col < NV_SC_THETA_BIN; ++col) {
max_bin = NV_MAX(max_bin, NV_MAT3D_LIST_V(sctx->sctx, l, row, col, 0));
min_bin = NV_MIN(min_bin, NV_MAT3D_LIST_V(sctx->sctx, l, row, col, 0));
}
}
if (max_bin > 0.0f) {
for (row = 0; row < NV_SC_LOG_R_BIN; ++row) {
for (col = 0; col < NV_SC_THETA_BIN; ++col) {
NV_MAT3D_LIST_V(sctx->sctx, l, row, col, 0)
= (NV_MAT3D_LIST_V(sctx->sctx, l, row, col, 0) - min_bin) / (max_bin - min_bin);
}
}
}
#endif
}
nv_matrix_free(&edge);
nv_matrix_free(&points);
nv_free(rand_idx);
}
float nv_mlp3_train_lex(nv_mlp3_t *mlp,
const nv_matrix_t *data,
const nv_matrix_t *label,
const nv_matrix_t *t,
float ir, float hr1, float hr2,
int start_epoch, int end_epoch, int max_epoch)
{
long tm;
int m, n, im, ok;
int epoch = 1;
float prediction;
float y, data_e, bp_sum;
float org_ir = ir;
float org_hr1 = hr1;
float org_hr2 = hr2;
int *rand_idx = (int *)nv_malloc(sizeof(int) * data->m);
int label_ok;
int do_train;
nv_matrix_t *input_y = nv_matrix_alloc(mlp->input_w->m, 1);
nv_matrix_t *hidden1_y = nv_matrix_alloc(mlp->hidden1_w->m, 1);
nv_matrix_t *hidden2_y = nv_matrix_alloc(mlp->hidden2_w->m, 1);
nv_matrix_t *output_y = nv_matrix_alloc(mlp->output, 1);
nv_matrix_t *output_bp = nv_matrix_alloc(mlp->output, 1);
nv_matrix_t *hidden1_bp = nv_matrix_alloc(mlp->hidden1, 1);
nv_matrix_t *hidden2_bp = nv_matrix_alloc(mlp->hidden2, 1);
nv_matrix_t *rand_s = nv_matrix_alloc(NV_MAX(mlp->hidden1, mlp->hidden2), 2);
epoch = start_epoch + 1;
do {
if (epoch != 0 && max_epoch != 0) {
float factor = expf(-((float)epoch * epoch) / (0.2f * max_epoch * max_epoch));
ir = org_ir * factor;
hr1 = org_hr1 * factor;
hr2 = org_hr2 * factor;
}
ok = 0;
data_e = 0.0f;
tm = nv_clock();
nv_shuffle_index(rand_idx, 0, data->m);
for (im = 0; im < data->m; ++im) {
float e;
float mp = -FLT_MAX;
int l = -1;
int dm = rand_idx[im];
/* 順伝播 */
/* 入力層 */
for (m = 0; m < mlp->hidden1; ++m) {
NV_MAT_V(rand_s, 0, m) = (nv_rand() * NV_MLP_RAND_S1) - (NV_MLP_RAND_S1 * 0.5f);
}
for (m = 0; m < mlp->hidden2; ++m) {
NV_MAT_V(rand_s, 1, m) = (nv_rand() * NV_MLP_RAND_S2) - (NV_MLP_RAND_S2 * 0.5f);
}
#ifdef _OPENMP
#pragma omp parallel for private(y) //if (mlp->input * mlp->hidden > 10240)
#endif
for (m = 0; m < mlp->input_w->m; ++m) {
y = NV_MAT_V(mlp->input_bias, m, 0);
y += nv_vector_dot(data, dm, mlp->input_w, m);
y = nv_mlp_sigmoid(y + NV_MAT_V(rand_s, 0, m));
NV_MAT_V(input_y, 0, m) = y;
}
/* 隠れ層1 */
#ifdef _OPENMP
#pragma omp parallel for private(y) if (mlp->output > 256)
#endif
for (m = 0; m < mlp->hidden1_w->m; ++m) {
y = NV_MAT_V(mlp->hidden1_bias, m, 0);
y += nv_vector_dot(input_y, 0, mlp->hidden1_w, m);
y = nv_mlp_sigmoid(y + NV_MAT_V(rand_s, 1, m));
NV_MAT_V(hidden1_y, 0, m) = y;
}
/* 隠れ層2 */
#ifdef _OPENMP
#pragma omp parallel for private(y) if (mlp->output > 256)
#endif
for (m = 0; m < mlp->hidden2_w->m; ++m) {
y = NV_MAT_V(mlp->hidden2_bias, m, 0);
y += nv_vector_dot(hidden1_y, 0, mlp->hidden2_w, m);
NV_MAT_V(hidden2_y, 0, m) = y;
}
/* 出力層 */
for (m = 0; m < mlp->hidden2_w->m; ++m) {
NV_MAT_V(output_y, 0, m) = nv_mlp_sigmoid(NV_MAT_V(hidden2_y, 0, m));
}
/* 誤差 */
do_train = 0;
e = 0.0f;
for (n = 0; n < output_y->n; ++n) {
float y = NV_MAT_V(output_y, 0, n);
float yt = NV_MAT_V(t, dm, n);
if (y == 0.0f) {
e += (yt * 0.0f + (1.0f - yt) * logf(1.0f - y)) * -1.0f;
} else if (y == 1.0f) {
e += (yt * logf(y) + (1.0f - yt) * 0.0f) * - 1.0f;
} else {
e += (yt * logf(y) + (1.0f - yt) * logf(1.0f - y)) * -1.0f;
}
}
data_e += e;
mp = -FLT_MAX;
l = -1; // nega
label_ok = NV_MAT_VI(label, dm, 0);
if (output_y->n == 1) {
if (NV_MAT_V(output_y, 0, 0) > 0.5f) {
l = 0;
} else {
l = 1;
}
if (label_ok == 0) {
if (NV_MAT_V(output_y, 0, 0) < 0.995f) {
do_train = 1;
}
} else {
if (NV_MAT_V(output_y, 0, 0) > 0.005f) {
do_train = 1;
}
}
} else {
for (n = 0; n < output_y->n; ++n) {
if (//NV_MAT_V(output_y, 0, n) > 0.5f
//&&
mp < NV_MAT_V(output_y, 0, n))
{
mp = NV_MAT_V(output_y, 0, n);
l = n;
}
if (n == label_ok) {
if (NV_MAT_V(output_y, 0, n) < 0.995f) {
do_train = 1;
}
} else {
if (NV_MAT_V(output_y, 0, n) > 0.005f) {
do_train = 1;
}
}
}
}
if (l == label_ok) {
++ok;
}
if (do_train) {
/* 逆伝播 */
bp_sum = 0.0f;
for (n = 0; n < output_bp->n; ++n) {
float y = NV_MAT_V(hidden2_y, 0, n);
float yt = NV_MAT_V(t, dm, n);
float expy = expf(y);
float bp =
-((2.0f * yt - 1.0f) * expy + yt)
/ (expf(2.0f * y) + 2.0f * expy + 1.0f);
bp_sum += bp;
NV_MAT_V(output_bp, 0, n) = bp;
}
if (bp_sum != 0.0f) {
for (m = 0; m < mlp->hidden2_w->n; ++m) {
y = 0.0f;
for (n = 0; n < mlp->output; ++n) {
y += NV_MAT_V(output_bp, 0, n) * NV_MAT_V(mlp->hidden2_w, n, m);
}
NV_MAT_V(hidden2_bp, 0, m) = y * (1.0f - NV_MAT_V(hidden1_y, 0, m)) * NV_MAT_V(hidden1_y, 0, m);
}
for (m = 0; m < mlp->hidden1_w->n; ++m) {
y = 0.0f;
for (n = 0; n < mlp->hidden2; ++n) {
y += NV_MAT_V(hidden2_bp, 0, n) * NV_MAT_V(mlp->hidden1_w, n, m);
}
NV_MAT_V(hidden1_bp, 0, m) = y * (1.0f - NV_MAT_V(input_y, 0, m)) * NV_MAT_V(input_y, 0, m);
}
/* I -= εΔI */
#ifdef _OPENMP
#pragma omp parallel for private(m)
#endif
for (n = 0; n < mlp->input_w->m; ++n) {
for (m = 0; m < mlp->input_w->n; ++m) {
NV_MAT_V(mlp->input_w, n, m) =
NV_MAT_V(mlp->input_w, n, m)
- ir * NV_MAT_V(data, dm, m) * NV_MAT_V(hidden1_bp, 0, n);
}
NV_MAT_V(mlp->input_bias, n, 0) =
NV_MAT_V(mlp->input_bias, n, 0)
- ir * 1.0f * NV_MAT_V(hidden1_bp, 0, n);
}
/* H1 -= εΔH1 */
#ifdef _OPENMP
#pragma omp parallel for private(m)
#endif
for (n = 0; n < mlp->hidden1_w->m; ++n) {
for (m = 0; m < mlp->hidden1_w->n; ++m) {
NV_MAT_V(mlp->hidden1_w, n, m) =
NV_MAT_V(mlp->hidden1_w, n, m)
- hr1 * NV_MAT_V(input_y, 0, m) * NV_MAT_V(hidden2_bp, 0, n);
}
NV_MAT_V(mlp->hidden1_bias, n, 0) =
NV_MAT_V(mlp->hidden1_bias, n, 0)
- hr1 * 1.0f * NV_MAT_V(hidden2_bp, 0, n);
}
/* H -= εΔH */
#ifdef _OPENMP
#pragma omp parallel for private(m)
#endif
for (n = 0; n < mlp->hidden2_w->m; ++n) {
for (m = 0; m < mlp->hidden2_w->n; ++m) {
NV_MAT_V(mlp->hidden2_w, n, m) =
NV_MAT_V(mlp->hidden2_w, n, m)
- hr2 * NV_MAT_V(hidden1_y, 0, m) * NV_MAT_V(output_bp, 0, n);
}
NV_MAT_V(mlp->hidden2_bias, n, 0) =
NV_MAT_V(mlp->hidden2_bias, n, 0)
- hr2 * 1.0f * NV_MAT_V(output_bp, 0, n);
}
}
}
}
prediction = (float)ok / data->m;
printf("%d: E:%E, ME:%E, %f (%d/%d), %ldms\n",
epoch, data_e, data_e / data->m / mlp->output,
prediction, data->m - ok,
data->m,
nv_clock() - tm);
} while (epoch++ < end_epoch);
nv_matrix_free(&input_y);
nv_matrix_free(&hidden1_y);
nv_matrix_free(&hidden2_y);
nv_matrix_free(&output_y);
nv_matrix_free(&hidden1_bp);
nv_matrix_free(&hidden2_bp);
nv_matrix_free(&output_bp);
nv_matrix_free(&rand_s);
nv_free(rand_idx);
return prediction;
}
void
nv_lr_train(nv_lr_t *lr,
const nv_matrix_t *data, const nv_matrix_t *label,
nv_lr_param_t param)
{
int m, n, i, j, k, l;
long tm, tm_all = nv_clock();
float oe = FLT_MAX, er = 1.0f, we;
float sum_e = 0.0f;
int epoch = 0;
int pn = (data->m > 256) ? 128:1;
int step = data->m / (pn);
int threads = nv_omp_procs();
nv_matrix_t *y = nv_matrix_alloc(lr->k, threads);
nv_matrix_t *t = nv_matrix_alloc(lr->k, threads);
nv_matrix_t *dw = nv_matrix_list_alloc(lr->n, lr->k, threads);
nv_matrix_t *count = nv_matrix_alloc(lr->k, 1);
nv_matrix_t *label_weight = nv_matrix_alloc(lr->k, 1);
float count_max_log;
nv_matrix_zero(count);
nv_matrix_fill(label_weight, 1.0f);
if (param.auto_balance) {
/* クラスごとに数が違う場合に更新重みをスケーリングする */
for (m = 0; m < data->m; ++m) {
NV_MAT_V(count, 0, (int)NV_MAT_V(label, m, 0)) += 1.0f;
}
count_max_log = logf(3.0f + NV_MAT_V(count, 0, nv_vector_max_n(count, 0)));
for (n = 0; n < count->n; ++n) {
if (NV_MAT_V(count, 0, n) > 0.0f) {
float count_log = logf(3.0f + NV_MAT_V(count, 0, n));
NV_MAT_V(label_weight, 0, n) =
powf(count_max_log, NV_LR_CLASS_COUNT_PENALTY_EXP)
/ powf(count_log, NV_LR_CLASS_COUNT_PENALTY_EXP);
} else {
NV_MAT_V(label_weight, 0, n) = 1.0f;
}
}
}
do {
we = 1.0f / er;
tm = nv_clock();
sum_e = 0.0f;
for (m = 0; m < step; ++m) {
nv_matrix_zero(dw);
#ifdef _OPENMP
#pragma omp parallel for schedule(dynamic, 4) reduction(+:sum_e) num_threads(threads)
#endif
for (i = 0; i < pn; ++i) {
int rand_m = NV_ROUND_INT((data->m - 1) * nv_rand());
int thread_num = nv_omp_thread_id();
int label_i = (int)NV_MAT_V(label, rand_m, 0);
float weight = NV_MAT_V(label_weight, 0, label_i);
float yp;
nv_vector_zero(t, thread_num);
NV_MAT_V(t, thread_num, label_i) = 1.0f;
nv_lr_predict_vector(lr, y, thread_num, data, rand_m);
yp = NV_MAT_V(y, thread_num, (int)NV_MAT_V(label, rand_m, 0));
if (yp < 1.0 - NV_LR_MARGIN) {
nv_lr_dw(lr, weight, dw, thread_num, data, rand_m, t, thread_num, y, thread_num);
sum_e += nv_lr_error(t, thread_num, y, thread_num);
}
}
for (l = 1; l < threads; ++l) {
for (j = 0; j < dw->m; ++j) {
for (i = 0; i < dw->n; ++i) {
NV_MAT_LIST_V(dw, 0, j, i) += NV_MAT_LIST_V(dw, l, j, i);
}
}
}
#ifdef _OPENMP
#pragma omp parallel for private(n) num_threads(threads) if (lr->k > 32)
#endif
for (k = 0; k < lr->k; ++k) {
switch (param.reg_type) {
case NV_LR_REG_NONE:
for (n = 0; n < lr->n; ++n) {
NV_MAT_V(lr->w, k, n) -=
we * param.grad_w * NV_MAT_LIST_V(dw, 0, k, n);
}
break;
case NV_LR_REG_L1:
// FOBOS L1
for (n = 0; n < lr->n; ++n) {
NV_MAT_V(lr->w, k, n) -=
we * param.grad_w * NV_MAT_LIST_V(dw, 0, k, n);
}
for (n = 0; n < lr->n; ++n) {
float w_i = NV_MAT_V(lr->w, k, n);
float lambda = we * param.reg_w * (1.0f / (1.0f + epoch));
NV_MAT_V(lr->w, k, n) = nv_sign(w_i) * NV_MAX(0.0f, (fabsf(w_i) - lambda));
}
break;
case NV_LR_REG_L2:
for (n = 0; n < lr->n; ++n) {
NV_MAT_V(lr->w, k, n) -=
we * (param.grad_w * (NV_MAT_LIST_V(dw, 0, k, n)
+ param.reg_w * NV_MAT_V(lr->w, k, n)));
}
break;
}
}
}
if (nv_lr_progress_flag) {
printf("nv_lr:%d: E: %E, %ldms\n",
epoch, sum_e / (pn * step), nv_clock() - tm);
}
if (nv_lr_progress_flag > 1) {
int *ok = nv_alloc_type(int, lr->k);
int *ng = nv_alloc_type(int, lr->k);
memset(ok, 0, sizeof(int) * lr->k);
memset(ng, 0, sizeof(int) * lr->k);
for (i = 0; i < data->m; ++i) {
int predict = nv_lr_predict_label(lr, data, i);
int teach = (int)NV_MAT_V(label, i, 0);
if (predict == teach) {
++ok[teach];
} else {
++ng[teach];
}
}
for (i = 0; i < lr->k; ++i) {
printf("%d: ok: %d, ng: %d, %f\n", i, ok[i], ng[i], (float)ok[i] / (float)(ok[i] + ng[i]));
}
nv_free(ok);
nv_free(ng);
}
if (nv_lr_progress_flag) {
fflush(stdout);
}
if (sum_e > oe) {
er += 1.0f;
}
if (er >= 20.0f) {
break;
}
if (sum_e < FLT_EPSILON) {
break;
}
oe = sum_e;
} while (param.max_epoch > ++epoch);
