static void _vip_hw_set_clock(int module, struct nxp_backward_camera_platform_data *param, bool on)
{
if (on) {
volatile u32 *clkgen_base = (volatile u32 *)IO_ADDRESS(NX_CLKGEN_GetPhysicalAddress(NX_VIP_GetClockNumber(module)));
NX_CLKGEN_SetBaseAddress(NX_VIP_GetClockNumber(module), (U32)clkgen_base);
NX_CLKGEN_SetClockDivisorEnable(NX_VIP_GetClockNumber(module), CTRUE);
NX_CLKGEN_SetClockBClkMode(NX_VIP_GetClockNumber(module), NX_BCLKMODE_DYNAMIC);
/* printk("RSTCON Base: 0x%x\n", NX_RSTCON_GetBaseAddress()); */
/* printk("RSTCON VIP %d Reset Number %d, REG Number %d\n", module, NX_VIP_GetResetNumber(module), NX_VIP_GetResetNumber(module)>>5); */
/* printk("CLKGEN Base: 0x%x\n", clkgen_base); */
NX_RSTCON_SetnRST(NX_VIP_GetResetNumber(module), RSTCON_nDISABLE);
NX_RSTCON_SetnRST(NX_VIP_GetResetNumber(module), RSTCON_nENABLE);
if (param->is_mipi) {
printk("%s: apply mipi csi clock!!!\n", __func__);
NX_CLKGEN_SetClockSource(NX_VIP_GetClockNumber(module), 0, 2); /* external PCLK */
NX_CLKGEN_SetClockDivisor(NX_VIP_GetClockNumber(module), 0, 2);
NX_CLKGEN_SetClockDivisorEnable(NX_VIP_GetClockNumber(module), CTRUE);
} else {
NX_CLKGEN_SetClockSource(NX_VIP_GetClockNumber(module), 0, 4 + param->port); /* external PCLK */
NX_CLKGEN_SetClockDivisor(NX_VIP_GetClockNumber(module), 0, 1);
NX_CLKGEN_SetClockDivisorEnable(NX_VIP_GetClockNumber(module), CTRUE);
}
printk("VIP CLK GEN VAL: 0x%x\n", *clkgen_base);
NX_VIP_SetBaseAddress(module, IO_ADDRESS(NX_VIP_GetPhysicalAddress(module)));
}
}
int bd_eth_init(void)
{
#if defined(CONFIG_DESIGNWARE_ETH)
u32 addr;
// Clock control
NX_CLKGEN_Initialize();
addr = NX_CLKGEN_GetPhysicalAddress(CLOCKINDEX_OF_DWC_GMAC_MODULE);
NX_CLKGEN_SetBaseAddress( CLOCKINDEX_OF_DWC_GMAC_MODULE, (u32)IO_ADDRESS(addr) );
NX_CLKGEN_SetClockSource( CLOCKINDEX_OF_DWC_GMAC_MODULE, 0, 4); // Sync mode for 100 & 10Base-T : External RX_clk
NX_CLKGEN_SetClockDivisor( CLOCKINDEX_OF_DWC_GMAC_MODULE, 0, 1); // Sync mode for 100 & 10Base-T
NX_CLKGEN_SetClockOutInv( CLOCKINDEX_OF_DWC_GMAC_MODULE, 0, CFALSE); // TX Clk invert off : 100 & 10Base-T
// NX_CLKGEN_SetClockOutInv( CLOCKINDEX_OF_DWC_GMAC_MODULE, 0, CTRUE); // TX clk invert on : 100 & 10Base-T
NX_CLKGEN_SetClockDivisorEnable( CLOCKINDEX_OF_DWC_GMAC_MODULE, CTRUE);
// Reset control
NX_RSTCON_Initialize();
addr = NX_RSTCON_GetPhysicalAddress();
NX_RSTCON_SetBaseAddress( (u32)IO_ADDRESS(addr) );
NX_RSTCON_SetnRST(RESETINDEX_OF_DWC_GMAC_MODULE_aresetn_i, RSTCON_ENABLE);
udelay(100);
NX_RSTCON_SetnRST(RESETINDEX_OF_DWC_GMAC_MODULE_aresetn_i, RSTCON_DISABLE);
udelay(100);
NX_RSTCON_SetnRST(RESETINDEX_OF_DWC_GMAC_MODULE_aresetn_i, RSTCON_ENABLE);
udelay(100);
// Set interrupt config.
//nxp_gpio_set_pull_sel(CFG_ETHER_GMAC_PHY_IRQ_NUM, CTRUE);
//nxp_gpio_set_pull_enb(CFG_ETHER_GMAC_PHY_IRQ_NUM, CTRUE);
gpio_direction_input(CFG_ETHER_GMAC_PHY_IRQ_NUM);
// Set GPIO nReset
//nxp_gpio_set_pull_enb(CFG_ETHER_GMAC_PHY_RST_NUM, CFALSE);
gpio_direction_output(CFG_ETHER_GMAC_PHY_RST_NUM, 1 );
udelay( 100 );
gpio_set_value(CFG_ETHER_GMAC_PHY_RST_NUM, 0 );
udelay( 100 );
gpio_set_value(CFG_ETHER_GMAC_PHY_RST_NUM, 1 );
#endif // #if defined(CONFIG_DESIGNWARE_ETH)
return 0;
}
