/* Returns true if the 64-bit register reg64 set by an instruction of the form
*
* add %reg64 %RBASE
*
* The instruction checked is the "distance" instruction from the current
* instruction being looked at by the specified iterator.
*/
static Bool NaClIsAddRbaseToReg64(NaClValidatorState* vstate,
size_t distance,
NaClOpKind reg64) {
NaClInstState* state;
const NaClInst* inst;
int op_1, op_2;
NaClExpVector* nodes;
NaClExp* node;
NaClOpKind reg;
NaClInstIter* iter = vstate->cur_iter;
/* Get the corresponding instruction. */
if (!NaClInstIterHasLookbackStateInline(iter, distance)) return FALSE;
state = NaClInstIterGetLookbackStateInline(iter, distance);
inst = NaClInstStateInst(state);
if (InstAdd != inst->name) return FALSE;
DEBUG(NaClLog(LOG_INFO, "inst(%d): add rbase: ", (int) distance);
NaClInstStateInstPrint(NaClLogGetGio(), state));
/* Extract the values of the two operands for the and. */
if (!NaClExtractBinaryOperandIndices(state, &op_1, &op_2)) return FALSE;
/* Extract the destination register of the and. */
nodes = NaClInstStateExpVector(state);
node = &nodes->node[op_1];
if (ExprRegister != node->kind) return FALSE;
/* Check that destination register matches wanted register. */
reg = NaClGetExpRegisterInline(node);
if (reg != reg64) return FALSE;
/* Check that source register is the base register. */
return NaClGetExpVectorRegister(nodes, op_2) == vstate->base_register;
}
/* Print out the given (memory offset) expression node to the given file.
* Returns the index of the node following the given (indexed) memory offset.
*/
static int NaClPrintDisassembledMemOffset(struct Gio* file,
NaClInstState *state,
int index) {
NaClExpVector* vector = NaClInstStateExpVector(state);
int r1_index = index + 1;
int r2_index = r1_index + NaClExpWidth(vector, r1_index);
int scale_index = r2_index + NaClExpWidth(vector, r2_index);
int disp_index = scale_index + NaClExpWidth(vector, scale_index);
NaClOpKind r1 = NaClGetExpVectorRegister(vector, r1_index);
NaClOpKind r2 = NaClGetExpVectorRegister(vector, r2_index);
uint64_t scale = NaClGetExprUnsignedValue(&vector->node[scale_index]);
int64_t disp = NaClGetExprSignedValue(&vector->node[disp_index]);
assert(ExprMemOffset == vector->node[index].kind);
gprintf(file,"[");
if (r1 != RegUnknown) {
NaClPrintDisassembledRegKind(file, r1);
}
if (r2 != RegUnknown) {
if (r1 != RegUnknown) {
gprintf(file, "+");
}
NaClPrintDisassembledRegKind(file, r2);
gprintf(file, "*%d", (uint32_t) scale);
}
if (disp != 0) {
if ((r1 != RegUnknown || r2 != RegUnknown) &&
!NaClIsExpNegativeConstant(vector, disp_index)) {
gprintf(file, "+");
}
/* Recurse to handle print using format flags. */
NaClPrintDisassembledExp(file, state, disp_index);
} else if (r1 == RegUnknown && r2 == RegUnknown) {
/* be sure to generate case: [0x0]. */
NaClPrintDisassembledExp(file, state, disp_index);
}
gprintf(file, "]");
return disp_index + NaClExpWidth(vector, disp_index);
}
