static uint32_t omap3_l4ta_read(void *opaque, target_phys_addr_t addr) { struct omap_target_agent_s *s = (struct omap_target_agent_s *)opaque; switch (addr) { case 0x00: /* COMPONENT_L */ return s->component; case 0x04: /* COMPONENT_H */ return 0; case 0x18: /* CORE_L */ return s->component; case 0x1c: /* CORE_H */ return (s->component >> 16); case 0x20: /* AGENT_CONTROL_L */ return s->control; case 0x24: /* AGENT_CONTROL_H */ return s->control_h; case 0x28: /* AGENT_STATUS_L */ return s->status; case 0x2c: /* AGENT_STATUS_H */ return 0; default: break; } OMAP_BAD_REG(s->base + addr); return 0; }
static uint32_t omap_uart_read(void *opaque, target_phys_addr_t addr) { struct omap_uart_s *s = (struct omap_uart_s *) opaque; addr &= 0xff; switch (addr) { case 0x20: /* MDR1 */ return s->mdr[0]; case 0x24: /* MDR2 */ return s->mdr[1]; case 0x40: /* SCR */ return s->scr; case 0x44: /* SSR */ return 0x0; case 0x48: /* EBLR (OMAP2) */ return s->eblr; case 0x4C: /* OSC_12M_SEL (OMAP1) */ return s->clksel; case 0x50: /* MVR */ return 0x30; case 0x54: /* SYSC (OMAP2) */ return s->syscontrol; case 0x58: /* SYSS (OMAP2) */ return 1; case 0x5c: /* WER (OMAP2) */ return s->wkup; case 0x60: /* CFPS (OMAP2) */ return s->cfps; } OMAP_BAD_REG(addr); return 0; }
static void omap3_l4ta_write(void *opaque, target_phys_addr_t addr, uint32_t value) { struct omap_target_agent_s *s = (struct omap_target_agent_s *)opaque; switch (addr) { case 0x00: /* COMPONENT_L */ case 0x04: /* COMPONENT_H */ case 0x18: /* CORE_L */ case 0x1c: /* CORE_H */ OMAP_RO_REG(s->base + addr); break; case 0x20: /* AGENT_CONTROL_L */ s->control = value & 0x00000701; break; case 0x24: /* AGENT_CONTROL_H */ s->control_h = value & 0x100; /* TODO: shouldn't this be read-only? */ break; case 0x28: /* AGENT_STATUS_L */ if (value & 0x100) s->status &= ~0x100; /* REQ_TIMEOUT */ break; case 0x2c: /* AGENT_STATUS_H */ /* no writable bits although the register is listed as RW */ break; default: OMAP_BAD_REG(s->base + addr); break; } }
static void omap_l4ta_write(void *opaque, hwaddr addr, uint64_t value, unsigned size) { struct omap_target_agent_s *s = (struct omap_target_agent_s *) opaque; if (size != 4) { return omap_badwidth_write32(opaque, addr, value); } switch (addr) { case 0x00: /* COMPONENT */ case 0x28: /* AGENT_STATUS */ OMAP_RO_REG(addr); break; case 0x20: /* AGENT_CONTROL */ s->control = value & 0x01000700; if (value & 1) /* OCP_RESET */ s->status &= ~1; /* REQ_TIMEOUT */ break; default: OMAP_BAD_REG(addr); } }
static void omap_tap_write(void *opaque, hwaddr addr, uint64_t value, unsigned size) { if (size != 4) { return omap_badwidth_write32(opaque, addr, value); } OMAP_BAD_REG(addr); }
static void omap3_synctimer_write(void *opaque, hwaddr addr, uint32_t value) { struct omap_synctimer_s *s = (struct omap_synctimer_s *)opaque; if (addr == 0x04) { s->sysconfig = value & 0x0c; } else { OMAP_BAD_REG(addr); } }
static uint32_t omap_synctimer_readw(void *opaque, target_phys_addr_t addr) { struct omap_synctimer_s *s = (struct omap_synctimer_s *) opaque; switch (addr) { case 0x00: /* 32KSYNCNT_REV */ return 0x21; case 0x10: /* CR */ return omap_synctimer_read(s) - s->val; } OMAP_BAD_REG(addr); return 0; }
static void omap_uart_write(void *opaque, hwaddr addr, uint64_t value, unsigned size) { struct omap_uart_s *s = (struct omap_uart_s *) opaque; if (size == 4) { omap_badwidth_write8(opaque, addr, value); return; } switch (addr) { case 0x20: /* MDR1 */ s->mdr[0] = value & 0x7f; break; case 0x24: /* MDR2 */ s->mdr[1] = value & 0xff; break; case 0x40: /* SCR */ s->scr = value & 0xff; break; case 0x48: /* EBLR (OMAP2) */ s->eblr = value & 0xff; break; case 0x4C: /* OSC_12M_SEL (OMAP1) */ s->clksel = value & 1; break; case 0x44: /* SSR */ case 0x50: /* MVR */ case 0x58: /* SYSS (OMAP2) */ OMAP_RO_REG(addr); break; case 0x54: /* SYSC (OMAP2) */ s->syscontrol = value & 0x1d; if (value & 2) omap_uart_reset(s); break; case 0x5c: /* WER (OMAP2) */ s->wkup = value & 0x7f; break; case 0x60: /* CFPS (OMAP2) */ s->cfps = value & 0xff; break; default: OMAP_BAD_REG(addr); } }
static uint32_t omap2_l4ta_read(void *opaque, target_phys_addr_t addr) { struct omap_target_agent_s *s = (struct omap_target_agent_s *) opaque; switch (addr) { case 0x00: /* COMPONENT */ return s->component; case 0x20: /* AGENT_CONTROL */ return s->control; case 0x28: /* AGENT_STATUS */ return s->status; } OMAP_BAD_REG(addr); return 0; }
static void omap_uart_write(void *opaque, target_phys_addr_t addr, uint32_t value) { struct omap_uart_s *s = (struct omap_uart_s *) opaque; addr &= 0xff; switch (addr) { case 0x20: /* MDR1 */ s->mdr[0] = value & 0x7f; break; case 0x24: /* MDR2 */ s->mdr[1] = value & 0xff; break; case 0x40: /* SCR */ s->scr = value & 0xff; break; case 0x48: /* EBLR (OMAP2) */ s->eblr = value & 0xff; break; case 0x4C: /* OSC_12M_SEL (OMAP1) */ s->clksel = value & 1; break; case 0x44: /* SSR */ case 0x50: /* MVR */ case 0x58: /* SYSS (OMAP2) */ OMAP_RO_REG(addr); break; case 0x54: /* SYSC (OMAP2) */ s->syscontrol = value & 0x1d; if (value & 2) omap_uart_reset(s); break; case 0x5c: /* WER (OMAP2) */ s->wkup = value & 0x7f; break; case 0x60: /* CFPS (OMAP2) */ s->cfps = value & 0xff; break; default: OMAP_BAD_REG(addr); } }
static void omap2_l4ta_write(void *opaque, target_phys_addr_t addr, uint32_t value) { struct omap_target_agent_s *s = (struct omap_target_agent_s *) opaque; switch (addr) { case 0x00: /* COMPONENT */ case 0x28: /* AGENT_STATUS */ OMAP_RO_REG(addr); break; case 0x20: /* AGENT_CONTROL */ s->control = value & 0x01000700; if (value & 1) /* OCP_RESET */ s->status &= ~1; /* REQ_TIMEOUT */ break; default: OMAP_BAD_REG(addr); } }
static uint64_t omap_l4ta_read(void *opaque, hwaddr addr, unsigned size) { struct omap_target_agent_s *s = (struct omap_target_agent_s *) opaque; if (size != 2) { return omap_badwidth_read16(opaque, addr); } switch (addr) { case 0x00: /* COMPONENT */ return s->component; case 0x20: /* AGENT_CONTROL */ return s->control; case 0x28: /* AGENT_STATUS */ return s->status; } OMAP_BAD_REG(addr); return 0; }
static uint64_t omap_uart_read(void *opaque, hwaddr addr, unsigned size) { struct omap_uart_s *s = (struct omap_uart_s *) opaque; if (size == 4) { return omap_badwidth_read8(opaque, addr); } switch (addr) { case 0x20: /* MDR1 */ return s->mdr[0]; case 0x24: /* MDR2 */ return s->mdr[1]; case 0x40: /* SCR */ return s->scr; case 0x44: /* SSR */ return 0x0; case 0x48: /* EBLR (OMAP2) */ return s->eblr; case 0x4C: /* OSC_12M_SEL (OMAP1) */ return s->clksel; case 0x50: /* MVR */ return 0x30; case 0x54: /* SYSC (OMAP2) */ return s->syscontrol; case 0x58: /* SYSS (OMAP2) */ return 1; case 0x5c: /* WER (OMAP2) */ return s->wkup; case 0x60: /* CFPS (OMAP2) */ return s->cfps; } OMAP_BAD_REG(addr); return 0; }
static void omap_synctimer_write(void *opaque, hwaddr addr, uint32_t value) { OMAP_BAD_REG(addr); }
/* TEST-Chip-level TAP */ static uint64_t omap_tap_read(void *opaque, hwaddr addr, unsigned size) { struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque; if (size != 4) { return omap_badwidth_read32(opaque, addr); } switch (addr) { case 0x204: /* IDCODE_reg */ switch (s->mpu_model) { case omap2420: case omap2422: case omap2423: return 0x5b5d902f; /* ES 2.2 */ case omap2430: return 0x5b68a02f; /* ES 2.2 */ case omap3430: return 0x1b7ae02f; /* ES 2 */ default: hw_error("%s: Bad mpu model\n", __FUNCTION__); } case 0x208: /* PRODUCTION_ID_reg for OMAP2 */ case 0x210: /* PRODUCTION_ID_reg for OMAP3 */ switch (s->mpu_model) { case omap2420: return 0x000254f0; /* POP ESHS2.1.1 in N91/93/95, ES2 in N800 */ case omap2422: return 0x000400f0; case omap2423: return 0x000800f0; case omap2430: return 0x000000f0; case omap3430: return 0x000000f0; default: hw_error("%s: Bad mpu model\n", __FUNCTION__); } case 0x20c: switch (s->mpu_model) { case omap2420: case omap2422: case omap2423: return 0xcafeb5d9; /* ES 2.2 */ case omap2430: return 0xcafeb68a; /* ES 2.2 */ case omap3430: return 0xcafeb7ae; /* ES 2 */ default: hw_error("%s: Bad mpu model\n", __FUNCTION__); } case 0x218: /* DIE_ID_reg */ return ('Q' << 24) | ('E' << 16) | ('M' << 8) | ('U' << 0); case 0x21c: /* DIE_ID_reg */ return 0x54 << 24; case 0x220: /* DIE_ID_reg */ return ('Q' << 24) | ('E' << 16) | ('M' << 8) | ('U' << 0); case 0x224: /* DIE_ID_reg */ return ('Q' << 24) | ('E' << 16) | ('M' << 8) | ('U' << 0); } OMAP_BAD_REG(addr); return 0; }
static void omap_synctimer_write(void *opaque, target_phys_addr_t addr, uint32_t value) { OMAP_BAD_REG(addr); }
/* TEST-Chip-level TAP */ static uint64_t omap_tap_read(void *opaque, hwaddr addr, unsigned size) { struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque; if (size != 4) { return omap_badwidth_read32(opaque, addr); } switch (addr) { case 0x204: /* IDCODE_reg */ switch (s->mpu_model) { case omap2420: case omap2422: case omap2423: return 0x5b5d902f; /* ES 2.2 */ case omap2430: return 0x5b68a02f; /* ES 2.2 */ case omap3430: return 0x4b7ae02f; /* ES 3.1 */ case omap3630: return 0x1b89102f; /* ES 1.1 */ default: hw_error("%s: Bad mpu model\n", __func__); } /* For OMAP2 there is a two word PRODUCTION_ID register at * 0x208..0x210. * For OMAP3 there is a four word PRODUCTION_ID register at * 0x208..0x214. */ case 0x208: /* PRODUCTION_ID_reg bits 0-31 */ switch (s->mpu_model) { case omap2420: return 0x000254f0; /* POP ESHS2.1.1 in N91/93/95, ES2 in N800 */ case omap2422: return 0x000400f0; case omap2423: return 0x000800f0; case omap2430: return 0x000000f0; case omap3430: case omap3630: return 0x0; default: hw_error("%s: Bad mpu model\n", __func__); } break; case 0x20c: /* PRODUCTION_ID bits 32-63 */ switch (s->mpu_model) { case omap2420: case omap2422: case omap2423: return 0xcafeb5d9; /* ES 2.2 */ case omap2430: return 0xcafeb68a; /* ES 2.2 */ case omap3430: case omap3630: return 0x0; default: hw_error("%s: Bad mpu model\n", __func__); } break; case 0x210: /* PRODUCTION_ID reg bits 64-95 (OMAP3 only) */ switch (s->mpu_model) { case omap2420: case omap2422: case omap2423: case omap2430: /* OMAP3 only, break out to bad-register path */ break; case omap3430: case omap3630: return 0x000f00f0; default: hw_error("%s: Bad mpu model\n", __func__); } break; case 0x214: /* PRODUCTION_ID bits 96-127 (OMAP3 only) */ switch (s->mpu_model) { case omap2420: case omap2422: case omap2423: case omap2430: /* OMAP3 only, break out to bad-register path */ break; case omap3430: return 0xcafeb7ae; /* ES 2.x/3.0 */ case omap3630: return 0xcafeb891; /* ES 1.0/1.1 */ default: hw_error("%s: Bad mpu model\n", __func__); } break; case 0x218: /* DIE_ID_reg */ return ('Q' << 24) | ('E' << 16) | ('M' << 8) | ('U' << 0); case 0x21c: /* DIE_ID_reg */ return 0x54 << 24; case 0x220: /* DIE_ID_reg */ return ('Q' << 24) | ('E' << 16) | ('M' << 8) | ('U' << 0); case 0x224: /* DIE_ID_reg */ return ('Q' << 24) | ('E' << 16) | ('M' << 8) | ('U' << 0); } OMAP_BAD_REG(addr); return 0; }