#include "cm-regbits-34xx.h"
/*
* 34XX-specific powerdomains, dependencies
*/
#ifdef CONFIG_ARCH_OMAP3
/*
* Powerdomains
*/
static struct powerdomain iva2_pwrdm = {
.name = "iva2_pwrdm",
.prcm_offs = OMAP3430_IVA2_MOD,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
.pwrsts = PWRSTS_OFF_RET_ON,
.pwrsts_logic_ret = PWRSTS_OFF_RET,
.banks = 4,
.pwrsts_mem_ret = {
[0] = PWRSTS_OFF_RET,
[1] = PWRSTS_OFF_RET,
[2] = PWRSTS_OFF_RET,
[3] = PWRSTS_OFF_RET,
},
.pwrsts_mem_on = {
[0] = PWRSTS_ON,
[1] = PWRSTS_ON,
[2] = PWRSTS_OFF_ON,
[3] = PWRSTS_ON,
},
.cmd_reg_addr = 0x01,
.i2c_high_speed = false,
.i2c_scll_low = 0x60,
.i2c_scll_high = 0x26,
.i2c_hscll_low = 0x0B,
.i2c_hscll_high = 0x00,
.reconfigure_switcher = omap_fan5355_reconfigure_regs,
.vsel_to_uv = omap_fan535503_vsel_to_uv,
.uv_to_vsel = omap_fan535503_uv_to_vsel,
};
static __initdata struct omap_pmic_map fan_map[] = {
{
.name = "core",
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP443X),
.pmic_data = &omap4_fan_core,
},
{
.name = "iva",
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP443X),
.pmic_data = &omap4_fan_iva,
},
/* Terminator */
{ .name = NULL, .pmic_data = NULL},
};
static __initdata struct omap_pmic_description fan_desc = {
.pmic_lp_tshut = 500, /* T-OFF */
.pmic_lp_tstart = 500, /* T-ON */
};
#include "powerdomain.h"
#include "powerdomains2xxx_3xxx_data.h"
#include "prcm-common.h"
#include "prm2xxx_3xxx.h"
#include "prm-regbits-24xx.h"
/* 24XX powerdomains and dependencies */
/* Powerdomains */
static struct powerdomain dsp_pwrdm = {
.name = "dsp_pwrdm",
.prcm_offs = OMAP24XX_DSP_MOD,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX),
.pwrsts = PWRSTS_OFF_RET_ON,
.pwrsts_logic_ret = PWRDM_POWER_RET,
.banks = 1,
.pwrsts_mem_ret = {
[0] = PWRDM_POWER_RET,
},
.pwrsts_mem_on = {
[0] = PWRDM_POWER_ON,
},
};
static struct powerdomain mpu_24xx_pwrdm = {
.name = "mpu_pwrdm",
.prcm_offs = MPU_MOD,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX),
{ .desc = NULL} /* TERMINATOR */
};
static int __init twl_set_4460vcore(struct voltagedomain *voltdm)
{
return _twl_set_regs("OMAP4460 ", omap4460_twl6030_setup);
}
#define OMAP3_TWL4030_USED (CHIP_GE_OMAP3430ES2 | \
CHIP_GE_OMAP3630ES1_1 | \
CHIP_IS_OMAP3630ES1)
static __initdata struct omap_pmic_map omap_twl_map[] = {
{
.name = "mpu_iva",
.omap_chip = OMAP_CHIP_INIT(OMAP3_TWL4030_USED),
.pmic_data = &omap3_mpu_pmic,
.special_action = twl_set_sr,
},
{
.name = "core",
.omap_chip = OMAP_CHIP_INIT(OMAP3_TWL4030_USED),
.pmic_data = &omap3_core_pmic,
},
{
.name = "mpu",
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP443X),
.pmic_data = &omap443x_mpu_pmic,
},
{
.name = "core",
#include "powerdomain.h"
#include "prcm-common.h"
#include "prm.h"
/* OMAP2/3-common powerdomains */
/*
* The GFX powerdomain is not present on 3430ES2, but currently we do not
* have a macro to filter it out at compile-time.
*/
struct powerdomain gfx_omap2_pwrdm = {
.name = "gfx_pwrdm",
.prcm_offs = GFX_MOD,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX |
CHIP_IS_OMAP3430ES1),
.pwrsts = PWRSTS_OFF_RET_ON,
.pwrsts_logic_ret = PWRSTS_RET,
.banks = 1,
.pwrsts_mem_ret = {
[0] = PWRSTS_RET, /* MEMRETSTATE */
},
.pwrsts_mem_on = {
[0] = PWRSTS_ON, /* MEMONSTATE */
},
.voltdm = { .name = "core" },
};
struct powerdomain wkup_omap2_pwrdm = {
.name = "wkup_pwrdm",
.prcm_offs = WKUP_MOD,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
};
/* Master interfaces on the MPU device */
static struct omap_hwmod_ocp_if *omap3xxx_mpu_masters[] = {
&omap3xxx_mpu__l3,
};
/* MPU */
static struct omap_hwmod omap3xxx_mpu_hwmod = {
.name = "mpu",
.class = &mpu_hwmod_class,
.main_clk = "arm_fck",
.masters = omap3xxx_mpu_masters,
.masters_cnt = ARRAY_SIZE(omap3xxx_mpu_masters),
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
};
static __initdata struct omap_hwmod *omap3xxx_hwmods[] = {
&omap3xxx_l3_hwmod,
&omap3xxx_l4_core_hwmod,
&omap3xxx_l4_per_hwmod,
&omap3xxx_l4_wkup_hwmod,
&omap3xxx_mpu_hwmod,
NULL,
};
int __init omap3xxx_hwmod_init(void)
{
return omap_hwmod_init(omap3xxx_hwmods);
}
};
/* Master interfaces on the L3 SLOW interconnect */
static struct omap_hwmod_ocp_if *ti816x_l3_slow_masters[] = {
&ti816x_l3_slow__l4_slow,
};
/* L3 SLOW */
static struct omap_hwmod ti816x_l3_slow_hwmod = {
.name = "l3_slow",
.class = &l3_hwmod_class,
.masters = ti816x_l3_slow_masters,
.masters_cnt = ARRAY_SIZE(ti816x_l3_slow_masters),
.slaves = ti816x_l3_slow_slaves,
.slaves_cnt = ARRAY_SIZE(ti816x_l3_slow_slaves),
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_TI81XX),
.flags = HWMOD_NO_IDLEST,
};
static struct omap_hwmod ti816x_uart1_hwmod;
static struct omap_hwmod ti816x_uart2_hwmod;
static struct omap_hwmod ti816x_uart3_hwmod;
static struct omap_hwmod ti814x_uart4_hwmod;
static struct omap_hwmod ti814x_uart5_hwmod;
static struct omap_hwmod ti814x_uart6_hwmod;
static struct omap_hwmod ti816x_wd_timer2_hwmod;
static struct omap_hwmod ti814x_wd_timer1_hwmod;
static struct omap_hwmod ti81xx_i2c1_hwmod;
static struct omap_hwmod ti816x_i2c2_hwmod;
static struct omap_hwmod ti814x_i2c3_hwmod;
static struct omap_hwmod ti814x_i2c4_hwmod;