/*FUNCTION**********************************************************************
*
* Function Name : UART_DRV_Init
* Description : This function initializes a UART instance for operation.
* This function will initialize the run-time state structure to keep track of the on-going
* transfers, ungate the clock to the UART module, initialize the module
* to user defined settings and default settings, configure the IRQ state structure and enable
* the module-level interrupt to the core, and enable the UART module transmitter and receiver.
* The following is an example of how to set up the uart_state_t and the
* uart_user_config_t parameters and how to call the UART_DRV_Init function by passing
* in these parameters:
* uart_user_config_t uartConfig;
* uartConfig.baudRate = 9600;
* uartConfig.bitCountPerChar = kUart8BitsPerChar;
* uartConfig.parityMode = kUartParityDisabled;
* uartConfig.stopBitCount = kUartOneStopBit;
* uart_state_t uartState;
* UART_DRV_Init(instance, &uartState, &uartConfig);
*
*END**************************************************************************/
uart_status_t UART_DRV_Init(uint32_t instance, uart_state_t * uartStatePtr,
const uart_user_config_t * uartUserConfig)
{
assert(uartStatePtr && uartUserConfig);
assert(instance < HW_UART_INSTANCE_COUNT);
uint32_t baseAddr = g_uartBaseAddr[instance];
uint32_t uartSourceClock;
/* Exit if current instance is already initialized. */
if (g_uartStatePtr[instance])
{
return kStatus_UART_Initialized;
}
/* Clear the state structure for this instance. */
memset(uartStatePtr, 0, sizeof(uart_state_t));
/* Save runtime structure pointer.*/
g_uartStatePtr[instance] = uartStatePtr;
/* Un-gate UART module clock */
CLOCK_SYS_EnableUartClock(instance);
/* Initialize UART to a known state. */
UART_HAL_Init(baseAddr);
/* Create Semaphore for txIrq and rxIrq. */
OSA_SemaCreate(&uartStatePtr->txIrqSync, 0);
OSA_SemaCreate(&uartStatePtr->rxIrqSync, 0);
/* UART clock source is either system clock or bus clock depending on the instance */
uartSourceClock = CLOCK_SYS_GetUartFreq(instance);
/* Initialize UART baud rate, bit count, parity and stop bit. */
UART_HAL_SetBaudRate(baseAddr, uartSourceClock, uartUserConfig->baudRate);
UART_HAL_SetBitCountPerChar(baseAddr, uartUserConfig->bitCountPerChar);
UART_HAL_SetParityMode(baseAddr, uartUserConfig->parityMode);
#if FSL_FEATURE_UART_HAS_STOP_BIT_CONFIG_SUPPORT
UART_HAL_SetStopBitCount(baseAddr, uartUserConfig->stopBitCount);
#endif
#if FSL_FEATURE_UART_HAS_FIFO
uint8_t fifoSize;
/* Obtain raw TX FIFO size bit setting */
fifoSize = UART_HAL_GetTxFifoSize(baseAddr);
/* Now calculate the number of data words per given FIFO size */
uartStatePtr->txFifoEntryCount = (fifoSize == 0 ? 1 : 0x1 << (fifoSize + 1));
/* Configure the TX FIFO watermark to be 1/2 of the total entry or 0 if entry count = 1
* A watermark setting of 0 for TX FIFO entry count of 1 means that TDRE will only interrupt
* when the TX buffer (the one entry in the TX FIFO) is empty. Otherwise, if we set the
* watermark to 1, the TDRE will always be set regardless if the TX buffer was empty or not
* as the spec says TDRE will set when the FIFO is at or below the configured watermark. */
if (uartStatePtr->txFifoEntryCount > 1)
{
UART_HAL_SetTxFifoWatermark(baseAddr, (uartStatePtr->txFifoEntryCount >> 1U));
}
/*FUNCTION**********************************************************************
*
* Function Name : LPSCI_DRV_Init
* Description : This function initializes a LPSCI instance for operation.
* This function will initialize the run-time state structure to keep track of
* the on-going transfers, ungate the clock to the LPSCI module, initialize the
* module to user defined settings and default settings, configure the IRQ state
* structure and enable the module-level interrupt to the core, and enable the
* LPSCI module transmitter and receiver.
* The following is an example of how to set up the lpsci_state_t and the
* lpsci_user_config_t parameters and how to call the LPSCI_DRV_Init function
* by passing in these parameters:
* lpsci_user_config_t lpsciConfig;
* lpsciConfig.clockSource = kClockLpsciSrcPllFllSel;
* lpsciConfig.baudRate = 9600;
* lpsciConfig.bitCountPerChar = kLpsci8BitsPerChar;
* lpsciConfig.parityMode = kLpsciParityDisabled;
* lpsciConfig.stopBitCount = kLpsciOneStopBit;
* lpsci_state_t lpsciState;
* LPSCI_DRV_Init(instance, &lpsciState, &lpsciConfig);
*
*END**************************************************************************/
lpsci_status_t LPSCI_DRV_Init(uint32_t instance,
lpsci_state_t * lpsciStatePtr,
const lpsci_user_config_t * lpsciUserConfig)
{
assert(lpsciStatePtr && lpsciUserConfig);
assert(instance < HW_UART0_INSTANCE_COUNT);
uint32_t baseAddr = g_lpsciBaseAddr[instance];
uint32_t lpsciSourceClock;
/* Exit if current instance is already initialized. */
if (g_lpsciStatePtr[instance])
{
return kStatus_LPSCI_Initialized;
}
/* Clear the state structure for this instance. */
memset(lpsciStatePtr, 0, sizeof(lpsci_state_t));
/* Save runtime structure pointer.*/
g_lpsciStatePtr[instance] = lpsciStatePtr;
/* Un-gate LPSCI module clock */
CLOCK_SYS_EnableLpsciClock(instance);
/* Set LPSCI clock source */
CLOCK_SYS_SetLpsciSrc(instance, lpsciUserConfig->clockSource);
/* Initialize LPSCI to a known state. */
LPSCI_HAL_Init(baseAddr);
/* Create Semaphore for txIrq and rxIrq. */
OSA_SemaCreate(&lpsciStatePtr->txIrqSync, 0);
OSA_SemaCreate(&lpsciStatePtr->rxIrqSync, 0);
lpsciSourceClock = CLOCK_SYS_GetLpsciFreq(instance);
/* Initialize LPSCI baud rate, bit count, parity and stop bit. */
LPSCI_HAL_SetBaudRate(baseAddr, lpsciSourceClock, lpsciUserConfig->baudRate);
LPSCI_HAL_SetBitCountPerChar(baseAddr, lpsciUserConfig->bitCountPerChar);
LPSCI_HAL_SetParityMode(baseAddr, lpsciUserConfig->parityMode);
#if FSL_FEATURE_LPSCI_HAS_STOP_BIT_CONFIG_SUPPORT
LPSCI_HAL_SetStopBitCount(baseAddr, lpsciUserConfig->stopBitCount);
#endif
/* Enable LPSCI interrupt on NVIC level. */
INT_SYS_EnableIRQ(g_lpsciRxTxIrqId[instance]);
/* Finally, enable the LPSCI transmitter and receiver*/
LPSCI_HAL_EnableTransmitter(baseAddr);
LPSCI_HAL_EnableReceiver(baseAddr);
return kStatus_LPSCI_Success;
}
/*FUNCTION**********************************************************************
*
* Function Name : LPUART_DRV_Init
* Description : This function initializes a LPUART instance for operation.
* This function will initialize the run-time state structure to keep track of
* the on-going transfers, ungate the clock to the LPUART module, initialize the
* module to user defined settings and default settings, configure the IRQ state
* structure and enable the module-level interrupt to the core, and enable the
* LPUART module transmitter and receiver.
* The following is an example of how to set up the lpuart_state_t and the
* lpuart_user_config_t parameters and how to call the LPUART_DRV_Init function
* by passing in these parameters:
* lpuart_user_config_t lpuartConfig;
* lpuartConfig.clockSource = kClockLpuartSrcPllFllSel;
* lpuartConfig.baudRate = 9600;
* lpuartConfig.bitCountPerChar = klpuart8BitsPerChar;
* lpuartConfig.parityMode = klpuartParityDisabled;
* lpuartConfig.stopBitCount = klpuartOneStopBit;
* lpuart_state_t lpuartState;
* LPUART_DRV_Init(instance, &lpuartState, &lpuartConfig);
*
*END**************************************************************************/
lpuart_status_t LPUART_DRV_Init(uint32_t instance, lpuart_state_t * lpuartStatePtr,
const lpuart_user_config_t * lpuartUserConfig)
{
assert(lpuartStatePtr && lpuartUserConfig);
assert(instance < LPUART_INSTANCE_COUNT);
uint32_t lpuartSourceClock;
LPUART_Type * base = g_lpuartBase[instance];
/* Exit if current instance is already initialized. */
if (g_lpuartStatePtr[instance])
{
return kStatus_LPUART_Initialized;
}
/* Clear the state struct for this instance. */
memset(lpuartStatePtr, 0, sizeof(lpuart_state_t));
/* Save runtime structure pointer.*/
g_lpuartStatePtr[instance] = lpuartStatePtr;
/* Set LPUART clock source */
CLOCK_SYS_SetLpuartSrc(instance, lpuartUserConfig->clockSource);
/* ungate lpuart module clock */
CLOCK_SYS_EnableLpuartClock(instance);
/* initialize the LPUART instance */
LPUART_HAL_Init(base);
/* Init the interrupt sync object. */
OSA_SemaCreate(&lpuartStatePtr->txIrqSync, 0);
OSA_SemaCreate(&lpuartStatePtr->rxIrqSync, 0);
/* LPUART clock source is either system clock or bus clock depending on the instance */
lpuartSourceClock = CLOCK_SYS_GetLpuartFreq(instance);
/* initialize the parameters of the LPUART config structure with desired data */
LPUART_HAL_SetBaudRate(base, lpuartSourceClock, lpuartUserConfig->baudRate);
LPUART_HAL_SetBitCountPerChar(base, lpuartUserConfig->bitCountPerChar);
LPUART_HAL_SetParityMode(base, lpuartUserConfig->parityMode);
LPUART_HAL_SetStopBitCount(base, lpuartUserConfig->stopBitCount);
/* finally, enable the LPUART transmitter and receiver */
LPUART_HAL_SetTransmitterCmd(base, true);
LPUART_HAL_SetReceiverCmd(base, true);
/* Enable LPUART interrupt. */
INT_SYS_EnableIRQ(g_lpuartRxTxIrqId[instance]);
return kStatus_LPUART_Success;
}
static int nio_dummy_init(void *init_data, void **dev_context, int *error) {
NIO_DUMMY_DEV_CONTEXT_STRUCT *context;
context = (NIO_DUMMY_DEV_CONTEXT_STRUCT*)OSA_MemAlloc(sizeof(NIO_DUMMY_DEV_CONTEXT_STRUCT));
OSA_SemaCreate(&context->lock, 1);
*dev_context = (void*)context;
return 0;
}
/*FUNCTION**********************************************************************
*
* Function Name : SPI_DRV_MasterInit
* Description : Initialize a SPI instance for master mode operation.
* This function uses a CPU interrupt driven method for transferring data.
* This function initializes the run-time state structure to track the ongoing
* transfers, ungates the clock to the SPI module, resets and initializes the module
* to default settings, configures the IRQ state structure, enables
* the module-level interrupt to the core, and enables the SPI module.
*
*END**************************************************************************/
spi_status_t SPI_DRV_MasterInit(uint32_t instance, spi_master_state_t * spiState)
{
SPI_Type *base = g_spiBase[instance];
/* Clear the state for this instance.*/
memset(spiState, 0, sizeof(* spiState));
/* Enable clock for SPI*/
CLOCK_SYS_EnableSpiClock(instance);
/* configure the run-time state struct with the source clock value */
spiState->spiSourceClock = CLOCK_SYS_GetSpiFreq(instance);
/* Reset the SPI module to it's default state, which includes SPI disabled */
SPI_HAL_Init(base);
/* Init the interrupt sync object.*/
OSA_SemaCreate(&spiState->irqSync, 0);
/* Set SPI to master mode */
SPI_HAL_SetMasterSlave(base, kSpiMaster);
/* Set slave select to automatic output mode */
SPI_HAL_SetSlaveSelectOutputMode(base, kSpiSlaveSelect_AutomaticOutput);
/* Set the SPI pin mode to normal mode */
SPI_HAL_SetPinMode(base, kSpiPinMode_Normal);
#if FSL_FEATURE_SPI_FIFO_SIZE
if (g_spiFifoSize[instance] != 0)
{
/* If SPI module contains a FIFO, enable it and set watermarks to half full/empty */
SPI_HAL_SetFifoMode(base, true, kSpiTxFifoOneHalfEmpty, kSpiRxFifoOneHalfFull);
}
#endif
/* Save runtime structure pointers to irq handler can point to the correct state structure*/
g_spiStatePtr[instance] = spiState;
/* Enable SPI interrupt.*/
INT_SYS_EnableIRQ(g_spiIrqId[instance]);
/* SPI system Enable*/
SPI_HAL_Enable(base);
return kStatus_SPI_Success;
}
/* Semaphore create and destroy */
os_sem_handle OS_Sem_create(uint32_t initial_number)
{
semaphore_t *p_sem = (semaphore_t *) OSA_MemAllocZero(sizeof(semaphore_t));
if (!p_sem)
{
return (os_sem_handle) 0;
}
if (kStatus_OSA_Success != OSA_SemaCreate(p_sem, initial_number))
{
OSA_MemFree(p_sem);
return (os_sem_handle) 0;
}
return (os_sem_handle) p_sem;
}
/*FUNCTION**********************************************************************
*
* Function Name : OSA_MsgQCreate
* Description : This function is used to create a message queue.
* Return the handle to the message queue if create successfully, otherwise
* return 0.
*
*END**************************************************************************/
msg_queue_handler_t OSA_MsgQCreate(msg_queue_t *queue,
uint16_t message_number,
uint16_t message_size)
{
assert(queue);
queue->number = message_number;
queue->size = message_size;
queue->head = 0;
queue->tail = 0;
queue->isEmpty = true;
if(kStatus_OSA_Success == OSA_SemaCreate(&queue->queueSem, 0))
{
return queue;
}
else
{
return NULL;
}
}
/*FUNCTION**********************************************************************
*
* Function Name : SND_RxInit
* Description : Initialize the Rx soundcard.
* The soundcard includes a controller and a codec.
*END**************************************************************************/
snd_status_t SND_RxInit(
sound_card_t * card, void * ctrl_config, void * codec_config, ctrl_state_t *state)
{
audio_controller_t *ctrl = &card->controller;
audio_codec_t *codec = &card->codec;
/* Allocate space for buffer */
audio_buffer_t *buffer = &card->buffer;
/* Buffer size and block settings */
if ((buffer->blocks == 0) || (buffer->size == 0))
{
buffer->blocks = AUDIO_BUFFER_BLOCK;
buffer->size = AUDIO_BUFFER_BLOCK_SIZE;
}
#if SOUNDCARD_USE_STATIC_MEM
buffer->buff = &s_rx_buffer[ctrl->instance][0];
#else
buffer->buff = (uint8_t *)OSA_MemAllocZero(buffer->size * buffer->blocks);
if(!buffer->buff)
{
return kStatus_SND_BufferAllocateFail;
}
#endif
buffer->input_curbuff = buffer->buff;
buffer->output_curbuff = buffer->buff;
/* Initialize the status structure */
buffer->empty_block = buffer->blocks;
buffer->full_block = 0;
OSA_SemaCreate(&buffer->sem, 0);
/* Initialize audio controller and codec */
ctrl->ops->Ctrl_RxInit(ctrl->instance, ctrl_config,state);
codec->ops->Codec_Init((void *)codec->handler, codec_config);
#if USEDMA
EDMA_DRV_RequestChannel(kEDMAAnyChannel, ctrl->dma_source, &ctrl->dma_channel);
EDMA_DRV_InstallCallback(&ctrl->dma_channel, SND_RxDmaCallback, (void *)card);
#else
ctrl->ops->Ctrl_RxRegisterCallback(ctrl->instance, SND_RxCallback, card);
#endif
return kStatus_SND_Success;
}
/**
* initialize the power task and relevant power objects
* @return status flag
*/
power_status_t power_Init()
{
if ( kStatus_OSA_Success != OSA_SemaCreate( &power_sema, 0 ) )
{
return POWER_STATUS_ERROR;
}
if ( kStatus_OSA_Success != power_CreateBinSema( &power_wakeSrcSema ) )
{
return POWER_STATUS_ERROR;
}
if ( kStatus_OSA_Success != power_CreateBinSema( &power_STSema ) )
{
return POWER_STATUS_ERROR;
}
osa_status_t
status = OSA_TaskCreate (
power_Task,
(uint8_t *) "Active power management",
POWER_STACK_SIZE,
NULL,
HEXIWEAR_STARTUP_PRIO,
(task_param_t)0,
false,
&power_handler
);
if ( kStatus_OSA_Success != status )
{
return POWER_STATUS_ERROR;
}
else
{
return POWER_STATUS_SUCCESS;
}
}
/************************* Configure for MQX************************************/
#if (defined FSL_RTOS_MQX)&&(MQX_COMMON_CONFIG == MQX_LITE_CONFIG)
#if MQX_STDIO
#error "MQX Lite configuration is designed to work with tool provided STD Library.\
Remove reference to MQX STD library from your build tool project options:\
IAR:\
Linker->Library->aditional_libraries - remove lib_mqx_stdlib.a path \
C/C++ Compiler->Preprocessor->Additional include directories: - remove mqx_stdlib \
\
KEIL: \
Linker->Misc controls - remove lib_mqx_stdlib.lib path \
C/C++->Include Paths - remove mqx_stdlib \
\
KDS: \
C/C++ Build\Settings->Cross ARM C Linker\Miscellaneous - remove lib_mqx_stdlib.a path\
C/C++ Build\Settings->Cross ARM C Compiler\Includes - remove mqx_stdlib (on 4th line)\
\
Atollic: \
C/C++ Build\Settings->C Linker/Libraries->Librarie search path - remove lib_mqx_stdlib \
C/C++ Build\Settings->C Compiler/Directories->Include Paths - remove mqx_stdlib \
CMAKE : \
Remove following lines from CMakeList.txt: \
INCLUDE_DIRECTORIES(${ProjDirPath}/../../../../../rtos/mqx/lib/twrk22f120m.armgcc/debug/mqx_stdlib) \
INCLUDE_DIRECTORIES(${ProjDirPath}/../../../../../rtos/mqx/lib/twrk22f120m.armgcc/release/mqx_stdlib) \
\
TARGET_LINK_LIBRARIES(lpm_rtos_mqx ${ProjDirPath}/../../../../../rtos/mqx/lib/twrk22f120m.armgcc/debug/mqx_stdlib/lib_mqx_stdlib.a) \
TARGET_LINK_LIBRARIES(lpm_rtos_mqx ${ProjDirPath}/../../../../../rtos/mqx/lib/twrk22f120m.armgcc/release/mqx_stdlib/lib_mqx_stdlib.a) \
."
#endif /* MQX_STDIO */
#elif (defined FSL_RTOS_MQX)&&(MQX_COMMON_CONFIG != MQX_LITE_CONFIG)
#define MAIN_TASK 8
void main_task(uint32_t param);
const TASK_TEMPLATE_STRUCT MQX_template_list[] =
{
{ MAIN_TASK, main_task, 0xC00, 20, "main_task", MQX_AUTO_START_TASK},
{ 0L, 0L, 0L, 0L, 0L, 0L }
};
#endif /* (FSL_RTOS_MQX)&&(MQX_COMMON_CONFIG != MQX_LITE_CONFIG) */
///////////////////////////////////////////////////////////////////////////////
// Code
///////////////////////////////////////////////////////////////////////////////
#if (defined FSL_RTOS_MQX) && (MQX_COMMON_CONFIG != MQX_LITE_CONFIG)
void main_task(uint32_t param)
#else /* (FSL_RTOS_MQX) && (MQX_COMMON_CONFIG != MQX_LITE_CONFIG) */
int main(void)
#endif /* (FSL_RTOS_MQX) && (MQX_COMMON_CONFIG != MQX_LITE_CONFIG) */
{
#if (defined FSL_RTOS_MQX)
// In deffault, MQX enables echo flag for stdin.
// For power manager demo, disable MQX flag to doesn't echo character.
ioctl( 0, IOCTL_NIO_TTY_SET_FLAGS, NIO_TTY_FLAGS_EOL_RN); // 0 - stdin
#endif
memset(&s_dbgState, 0, sizeof(s_dbgState));
hardware_init();
OSA_Init();
#if (!defined FSL_RTOS_MQX)
//init the uart module with base address and config structure
g_uartStatePtr[BOARD_DEBUG_UART_INSTANCE] = &s_dbgState;
/* Init the interrupt sync object. */
OSA_SemaCreate(&s_dbgState.txIrqSync, 0);
OSA_SemaCreate(&s_dbgState.rxIrqSync, 0);
NVIC_EnableIRQ(g_uartRxTxIrqId[BOARD_DEBUG_UART_INSTANCE]);
#endif
// Initializes GPIO driver for LEDs and buttons
#if (defined FSL_RTOS_BM)
GPIO_DRV_Init(switchPins, 0);
#else
GPIO_DRV_Init(switchPins, ledPins);
#endif
NVIC_SetPriority(PM_DBG_UART_IRQn, 6U);
NVIC_SetPriority(RTC_IRQn, 6U);
NVIC_SetPriority(LPTMR0_IRQn, 6U);
NVIC_SetPriority(ADC_IRQ_N, 6U);
NVIC_SetPriority(LLWU_IRQn, 6U);
#if (defined FSL_RTOS_MQX)
OSA_InstallIntHandler(PM_DBG_UART_IRQn, PM_MQX_DBG_UART_IRQ_HANDLER);
#endif
adc16Init(&adcUserConfig, &adcChnConfig, &adcCalibraitionParam);
// Low power manager task.
s_result = OSA_TaskCreate(task_lpm,
(uint8_t *)"lpm",
TASK_LPM_STACK_SIZE,
task_lpm_stack,
TASK_LPM_PRIO,
(task_param_t)0,
false,
&task_lpm_task_handler);
if (s_result != kStatus_OSA_Success)
{
PRINTF("Failed to create lpm task\r\n");
}
// These tasks will not start in BM.
#if (!defined FSL_RTOS_BM)
s_result = OSA_TaskCreate(task_led_rtos,
(uint8_t *)"led_rtos",
TASK_LED_RTOS_STACK_SIZE,
task_led_rtos_stack,
TASK_LED_RTOS_PRIO,
(task_param_t)0,
false,
&task_led_rtos_task_handler);
if (s_result != kStatus_OSA_Success)
{
PRINTF("Failed to create led_rtos task\r\n");
}
s_result = OSA_TaskCreate(task_led_clock,
(uint8_t *)"led_clock",
TASK_LED_CLOCK_STACK_SIZE,
task_led_clock_stack,
TASK_LED_CLOCK_PRIO,
(task_param_t)0,
false,
&task_led_clock_task_handler);
if (s_result != kStatus_OSA_Success)
{
PRINTF("Failed to create led_clock task\r\n");
}
#endif
OSA_Start();
for(;;) {} // Should not achieve here
}
/*FUNCTION**********************************************************************
*
* Function Name : LPSCI_DRV_DmaInit
* Description : This function initializes a LPSCI instance for operation.
* This function will initialize the run-time state structure to keep track of
* the on-going transfers, ungate the clock to the LPSCI module, initialize the
* module to user defined settings and default settings, configure LPSCI DMA
* and enable the LPSCI module transmitter and receiver.
* The following is an example of how to set up the lpsci_dma_state_t and the
* lpsci_user_config_t parameters and how to call the LPSCI_DRV_DmaInit function
* by passing in these parameters:
* lpsci_user_config_t lpsciConfig;
* lpsciConfig.baudRate = 9600;
* lpsciConfig.bitCountPerChar = kLpsci8BitsPerChar;
* lpsciConfig.parityMode = kLpsciParityDisabled;
* lpsciConfig.stopBitCount = kLpsciOneStopBit;
* lpsci_dma_state_t lpsciDmaState;
* LPSCI_DRV_DmaInit(instance, &lpsciDmaState, &lpsciConfig);
*
*END**************************************************************************/
lpsci_status_t LPSCI_DRV_DmaInit(uint32_t instance,
lpsci_dma_state_t * lpsciDmaStatePtr,
const lpsci_dma_user_config_t * lpsciUserConfig)
{
assert(lpsciDmaStatePtr && lpsciUserConfig);
assert(instance < UART0_INSTANCE_COUNT);
UART0_Type * base = g_lpsciBase[instance];
uint32_t lpsciSourceClock = 0;
dma_request_source_t lpsciTxDmaRequest = kDmaRequestMux0Disable;
dma_request_source_t lpsciRxDmaRequest = kDmaRequestMux0Disable;
dma_channel_t *chn;
DMA_Type * dmaBase;
dma_channel_link_config_t config;
config.channel1 = 0;
config.channel2 = 0;
config.linkType = kDmaChannelLinkDisable;
/* Exit if current instance is already initialized. */
if (g_lpsciStatePtr[instance])
{
return kStatus_LPSCI_Initialized;
}
/* Clear the state structure for this instance. */
memset(lpsciDmaStatePtr, 0, sizeof(lpsci_dma_state_t));
/* Save runtime structure pointer.*/
g_lpsciStatePtr[instance] = lpsciDmaStatePtr;
/* Un-gate LPSCI module clock */
CLOCK_SYS_EnableLpsciClock(instance);
/* Set LPSCI clock source */
CLOCK_SYS_SetLpsciSrc(instance, lpsciUserConfig->clockSource);
/* Initialize LPSCI to a known state. */
LPSCI_HAL_Init(base);
/* Create Semaphore for txIrq and rxIrq. */
OSA_SemaCreate(&lpsciDmaStatePtr->txIrqSync, 0);
OSA_SemaCreate(&lpsciDmaStatePtr->rxIrqSync, 0);
/* LPSCI clock source is either system or bus clock depending on instance */
lpsciSourceClock = CLOCK_SYS_GetLpsciFreq(instance);
/* Initialize LPSCI baud rate, bit count, parity and stop bit. */
LPSCI_HAL_SetBaudRate(base, lpsciSourceClock, lpsciUserConfig->baudRate);
LPSCI_HAL_SetBitCountPerChar(base, lpsciUserConfig->bitCountPerChar);
LPSCI_HAL_SetParityMode(base, lpsciUserConfig->parityMode);
#if FSL_FEATURE_LPSCI_HAS_STOP_BIT_CONFIG_SUPPORT
LPSCI_HAL_SetStopBitCount(base, lpsciUserConfig->stopBitCount);
#endif
/* Enable DMA trigger when transmit data register empty,
* and receive data register full. */
LPSCI_HAL_SetTxDmaCmd(base, true);
LPSCI_HAL_SetRxDmaCmd(base, true);
switch (instance)
{
case 0:
lpsciRxDmaRequest = kDmaRequestMux0LPSCI0Rx;
lpsciTxDmaRequest = kDmaRequestMux0LPSCI0Tx;
break;
default :
break;
}
/* Request DMA channels for RX FIFO. */
DMA_DRV_RequestChannel(kDmaAnyChannel, lpsciRxDmaRequest,
&lpsciDmaStatePtr->dmaLpsciRx);
DMA_DRV_RegisterCallback(&lpsciDmaStatePtr->dmaLpsciRx,
LPSCI_DRV_DmaRxCallback, (void *)instance);
chn = &lpsciDmaStatePtr->dmaLpsciRx;
dmaBase = g_dmaBase[chn->channel/FSL_FEATURE_DMA_DMAMUX_CHANNELS];
DMA_HAL_SetAutoAlignCmd(dmaBase, chn->channel, false);
DMA_HAL_SetCycleStealCmd(dmaBase, chn->channel, true);
DMA_HAL_SetAsyncDmaRequestCmd(dmaBase, chn->channel, false);
DMA_HAL_SetDisableRequestAfterDoneCmd(dmaBase, chn->channel, true);
DMA_HAL_SetChanLink(dmaBase, chn->channel, &config);
DMA_HAL_SetSourceAddr(dmaBase, chn->channel, LPSCI_HAL_GetDataRegAddr(base));
DMA_HAL_SetSourceModulo(dmaBase, chn->channel, kDmaModuloDisable);
DMA_HAL_SetSourceTransferSize(dmaBase, chn->channel, kDmaTransfersize8bits);
DMA_HAL_SetSourceIncrementCmd(dmaBase, chn->channel, false);
DMA_HAL_SetDestModulo(dmaBase, chn->channel, kDmaModuloDisable);
DMA_HAL_SetDestTransferSize(dmaBase, chn->channel, kDmaTransfersize8bits);
DMA_HAL_SetDestIncrementCmd(dmaBase, chn->channel, true);
DMA_HAL_SetIntCmd(dmaBase, chn->channel, true);
/* Request DMA channels for TX FIFO. */
DMA_DRV_RequestChannel(kDmaAnyChannel, lpsciTxDmaRequest,
&lpsciDmaStatePtr->dmaLpsciTx);
DMA_DRV_RegisterCallback(&lpsciDmaStatePtr->dmaLpsciTx,
LPSCI_DRV_DmaTxCallback, (void *)instance);
chn = &lpsciDmaStatePtr->dmaLpsciTx;
dmaBase = g_dmaBase[chn->channel/FSL_FEATURE_DMA_DMAMUX_CHANNELS];
DMA_HAL_SetAutoAlignCmd(dmaBase, chn->channel, false);
DMA_HAL_SetCycleStealCmd(dmaBase, chn->channel, true);
DMA_HAL_SetAsyncDmaRequestCmd(dmaBase, chn->channel, false);
DMA_HAL_SetDisableRequestAfterDoneCmd(dmaBase, chn->channel, true);
DMA_HAL_SetChanLink(dmaBase, chn->channel, &config);
DMA_HAL_SetSourceModulo(dmaBase, chn->channel, kDmaModuloDisable);
DMA_HAL_SetSourceTransferSize(dmaBase, chn->channel, kDmaTransfersize8bits);
DMA_HAL_SetSourceIncrementCmd(dmaBase, chn->channel, true);
DMA_HAL_SetDestAddr(dmaBase, chn->channel, LPSCI_HAL_GetDataRegAddr(base));
DMA_HAL_SetDestModulo(dmaBase, chn->channel, kDmaModuloDisable);
DMA_HAL_SetDestTransferSize(dmaBase, chn->channel, kDmaTransfersize8bits);
DMA_HAL_SetDestIncrementCmd(dmaBase, chn->channel, false);
DMA_HAL_SetIntCmd(dmaBase, chn->channel, true);
/* Finally, enable the LPSCI transmitter and receiver*/
LPSCI_HAL_EnableTransmitter(base);
LPSCI_HAL_EnableReceiver(base);
return kStatus_LPSCI_Success;
}
/*FUNCTION**********************************************************************
*
* Function Name : TSI_DRV_Init
* Description : Initialize whole the TSI peripheral to be ready to read capacitance changes
* To initialize the TSI driver, the configuration structure should be handled.
*
*END**************************************************************************/
tsi_status_t TSI_DRV_Init(uint32_t instance, tsi_state_t * tsiState, const tsi_user_config_t * tsiUserConfig)
{
assert(instance < TSI_INSTANCE_COUNT);
TSI_Type * base = g_tsiBase[instance];
tsi_state_t * tsiSt = g_tsiStatePtr[instance];
/* Critical section. */
OSA_EnterCritical(kCriticalDisableInt);
/* Exit if current instance is already initialized. */
if(tsiSt)
{
/* End of critical section. */
OSA_ExitCritical(kCriticalDisableInt);
return kStatus_TSI_Initialized;
}
/* Save runtime structure pointer.*/
tsiSt = g_tsiStatePtr[instance] = tsiState;
/* Clear the state structure for this instance. */
memset(tsiSt, 0, sizeof(tsi_state_t));
/* Create the mutex used by whole driver. */
OSA_MutexCreate(&tsiSt->lock);
/* Create the mutex used by change mode function. */
OSA_MutexCreate(&tsiSt->lockChangeMode);
/* Critical section. Access to global variable */
if (kStatus_OSA_Success != OSA_MutexLock(&tsiSt->lock, OSA_WAIT_FOREVER))
{
/* End of critical section. */
OSA_ExitCritical(kCriticalDisableInt);
return kStatus_TSI_Error;
}
/* End of critical section. */
OSA_ExitCritical(kCriticalDisableInt);
tsiSt->opMode = tsi_OpModeNormal;
tsiSt->opModesData[tsiSt->opMode].config = *tsiUserConfig->config; /* Store the hardware configuration. */
tsiSt->pCallBackFunc = tsiUserConfig->pCallBackFunc;
tsiSt->usrData = tsiUserConfig->usrData;
tsiSt->isBlockingMeasure = false;
/* Un-gate TSI module clock */
CLOCK_SYS_EnableTsiClock(instance);
/* Initialize the interrupt sync object. */
OSA_SemaCreate(&tsiSt->irqSync, 0);
TSI_HAL_Init(base);
TSI_HAL_SetConfiguration(base, &tsiSt->opModesData[tsiSt->opMode].config);
TSI_HAL_EnableInterrupt(base);
TSI_HAL_EnableEndOfScanInterrupt(base);
TSI_HAL_EnableSoftwareTriggerScan(base);
/* Disable all electrodes */
tsiState->opModesData[tsiState->opMode].enabledElectrodes = 0;
/* Enable TSI interrupt on NVIC level. */
INT_SYS_EnableIRQ(g_tsiIrqId[instance]);
tsiSt->status = kStatus_TSI_Initialized;
/* End of critical section. */
OSA_MutexUnlock(&tsiSt->lock);
return kStatus_TSI_Success;
}
/*FUNCTION**********************************************************************
*
* Function Name : DSPI_DRV_DmaMasterInit
* Description : Initializes a DSPI instance for master mode operation to work with DMA.
* This function uses a dma driven method for transferring data.
* This function initializes the run-time state structure to track the ongoing
* transfers, ungates the clock to the DSPI module, resets the DSPI module, initializes the module
* to user defined settings and default settings, configures the IRQ state structure, enables
* the module-level interrupt to the core, and enables the DSPI module.
* The CTAR parameter is special in that it allows the user to have different SPI devices
* connected to the same DSPI module instance in addition to different peripheral chip
* selects. Each CTAR contains the bus attributes associated with that particular SPI device.
* For most use cases where only one SPI device is connected per DSPI module
* instance, use CTAR0.
* This is an example to set up and call the DSPI_DRV_DmaMasterInit function by passing
* in these parameters:
* dspi_dma_master_state_t dspiDmaState; <- the user simply allocates memory for this struct
* uint32_t calculatedBaudRate;
* dspi_dma_master_user_config_t userConfig; <- the user fills out members for this struct
* userConfig.isChipSelectContinuous = false;
* userConfig.isSckContinuous = false;
* userConfig.pcsPolarity = kDspiPcs_ActiveLow;
* userConfig.whichCtar = kDspiCtar0;
* userConfig.whichPcs = kDspiPcs0;
* DSPI_DRV_DmaMasterInit(masterInstance, &dspiDmaState, &userConfig);
*
*END**************************************************************************/
dspi_status_t DSPI_DRV_DmaMasterInit(uint32_t instance,
dspi_dma_master_state_t * dspiDmaState,
const dspi_dma_master_user_config_t * userConfig)
{
uint32_t dspiSourceClock;
SPI_Type *base = g_dspiBase[instance];
dma_request_source_t dspiTxDmaRequest = kDmaRequestMux0Disable;
dma_request_source_t dspiRxDmaRequest = kDmaRequestMux0Disable;
/* Check parameter pointers to make sure there are not NULL */
if ((dspiDmaState == NULL) || (userConfig == NULL))
{
return kStatus_DSPI_InvalidParameter;
}
/* Clear the run-time state struct for this instance.*/
memset(dspiDmaState, 0, sizeof(* dspiDmaState));
/* Note, remember to first enable clocks to the DSPI module before making any register accesses
* Enable clock for DSPI
*/
CLOCK_SYS_EnableSpiClock(instance);
/* Get module clock freq*/
dspiSourceClock = CLOCK_SYS_GetSpiFreq(instance);
/* Configure the run-time state struct with the DSPI source clock */
dspiDmaState->dspiSourceClock = dspiSourceClock;
/* Configure the run-time state struct with the data command parameters*/
dspiDmaState->whichCtar = userConfig->whichCtar; /* set the dspiDmaState struct CTAR*/
dspiDmaState->whichPcs = userConfig->whichPcs; /* set the dspiDmaState struct whichPcs*/
dspiDmaState->isChipSelectContinuous = userConfig->isChipSelectContinuous; /* continuous PCS*/
/* Initialize the DSPI module registers to default value, which disables the module */
DSPI_HAL_Init(base);
/* Init the interrupt sync object.*/
if (OSA_SemaCreate(&dspiDmaState->irqSync, 0) != kStatus_OSA_Success)
{
return kStatus_DSPI_Error;
}
/* Set to master mode.*/
DSPI_HAL_SetMasterSlaveMode(base, kDspiMaster);
/* Configure for continuous SCK operation*/
DSPI_HAL_SetContinuousSckCmd(base, userConfig->isSckContinuous);
/* Configure for peripheral chip select polarity*/
DSPI_HAL_SetPcsPolarityMode(base, userConfig->whichPcs, userConfig->pcsPolarity);
/* Enable fifo operation (regardless of FIFO depth) */
DSPI_HAL_SetFifoCmd(base, true, true);
/* Initialize the configurable delays: PCS-to-SCK, prescaler = 0, scaler = 1 */
DSPI_HAL_SetDelay(base, userConfig->whichCtar, 0, 1, kDspiPcsToSck);
/* Save runtime structure pointers to irq handler can point to the correct state structure*/
g_dspiStatePtr[instance] = dspiDmaState;
/* enable the interrupt*/
INT_SYS_EnableIRQ(g_dspiIrqId[instance]);
/* DSPI system enable */
DSPI_HAL_Enable(base);
/* Request DMA channels from the DMA peripheral driver.
* Note, some MCUs have a separate RX and TX DMA request for each DSPI instance, while
* other MCUs have a separate RX and TX DMA request for DSPI instance 0 only and shared DMA
* requests for all other instances. Therefore, use the DSPI feature file to distinguish
* how to request DMA channels between the various MCU DSPI instances.
* For DSPI instances with shared RX/TX DMA requests, we'll use the RX DMA request to
* trigger ongoing transfers and will link to the TX DMA channel from the RX DMA channel.
*/
switch (instance)
{
case 0:
/* SPI0 */
#if FSL_FEATURE_DSPI_HAS_SEPARATE_DMA_RX_TX_REQn(0)
dspiRxDmaRequest = kDmaRequestMux0SPI0Rx;
dspiTxDmaRequest = kDmaRequestMux0SPI0Tx;
#else
/* DMA is simple link control, so DSPI - DMA driver does not support the case that DSPI have
* shared DMA channels
*/
return kStatus_DSPI_DMAChannelInvalid;
#endif
break;
#if (SPI_INSTANCE_COUNT > 1)
case 1:
/* SPI1 */
#if FSL_FEATURE_DSPI_HAS_SEPARATE_DMA_RX_TX_REQn(1)
dspiRxDmaRequest = kDmaRequestMux0SPI1Rx;
dspiTxDmaRequest = kDmaRequestMux0SPI1Tx;
#else
/* DMA is simple link control, so DSPI - DMA driver does not support the case that DSPI have
* shared DMA channels
*/
return kStatus_DSPI_DMAChannelInvalid;
#endif
break;
#endif
#if (SPI_INSTANCE_COUNT > 2)
case 2:
/* SPI2 */
#if FSL_FEATURE_DSPI_HAS_SEPARATE_DMA_RX_TX_REQn(2)
dspiRxDmaRequest = kDmaRequestMux0SPI2Rx;
dspiTxDmaRequest = kDmaRequestMux0SPI2Tx;
#else
/* DMA is simple link control, so DSPI - DMA driver does not support the case that DSPI have
* shared DMA channels
*/
return kStatus_DSPI_DMAChannelInvalid;
#endif
break;
#endif
default :
return kStatus_DSPI_InvalidInstanceNumber;
}
/* This channel transfers data from RX FIFO to receiveBuffer */
if (kDmaInvalidChannel == DMA_DRV_RequestChannel(kDmaAnyChannel,
dspiRxDmaRequest,
&dspiDmaState->dmaRxChannel))
{
return kStatus_DSPI_DMAChannelInvalid;
}
/* This channel transfers data from transmitBuffer to TX FIFO */
if (kDmaInvalidChannel == DMA_DRV_RequestChannel(kDmaAnyChannel,
dspiTxDmaRequest,
&dspiDmaState->dmaTxDataChannel))
{
return kStatus_DSPI_DMAChannelInvalid;
}
/* Source buffer to intermediate command/data
* This channel is not activated by dma request, but by channel link.
*/
if (DMA_DRV_RequestChannel(kDmaAnyChannel,
kDmaRequestMux0Disable,
&dspiDmaState->dmaTxCmdChannel) == kDmaInvalidChannel)
{
return kStatus_DSPI_DMAChannelInvalid;
}
/* Start the transfer process in the hardware */
DSPI_HAL_StartTransfer(base);
return kStatus_DSPI_Success;
}
/*FUNCTION**********************************************************************
*
* Function Name : LPUART_DRV_EdmaInit
* Description : This function initializes a LPUART instance for operation.
* This function will initialize the run-time state structure to keep track of
* the on-going transfers, ungate the clock to the LPUART module, initialize the
* module to user defined settings and default settings, configure LPUART DMA
* and enable the LPUART module transmitter and receiver.
* The following is an example of how to set up the lpuart_edma_state_t and the
* lpuart_user_config_t parameters and how to call the LPUART_DRV_EdmaInit function
* by passing in these parameters:
* lpuart_user_config_t lpuartConfig;
* lpuartConfig.clockSource = kClockLpuartSrcPllFllSel;
* lpuartConfig.baudRate = 9600;
* lpuartConfig.bitCountPerChar = kLpuart8BitsPerChar;
* lpuartConfig.parityMode = kLpuartParityDisabled;
* lpuartConfig.stopBitCount = kLpuartOneStopBit;
* lpuart_edma_state_t lpuartEdmaState;
* LPUART_DRV_EdmaInit(instance, &lpuartEdmaState, &lpuartConfig);
*
*END**************************************************************************/
lpuart_status_t LPUART_DRV_EdmaInit(uint32_t instance,
lpuart_edma_state_t * lpuartEdmaStatePtr,
const lpuart_edma_user_config_t * lpuartUserConfig)
{
assert(lpuartEdmaStatePtr && lpuartUserConfig);
assert(instance < LPUART_INSTANCE_COUNT);
/* This driver only support UART instances with separate DMA channels for
* both Tx and Rx.*/
assert(FSL_FEATURE_LPUART_HAS_SEPARATE_DMA_RX_TX_REQn(instance) == 1);
LPUART_Type * base = g_lpuartBase[instance];
uint32_t lpuartSourceClock = 0;
dma_request_source_t lpuartTxEdmaRequest = kDmaRequestMux0Disable;
dma_request_source_t lpuartRxEdmaRequest = kDmaRequestMux0Disable;
/* Exit if current instance is already initialized. */
if (g_lpuartStatePtr[instance])
{
return kStatus_LPUART_Initialized;
}
/* Clear the state structure for this instance. */
memset(lpuartEdmaStatePtr, 0, sizeof(lpuart_edma_state_t));
/* Save runtime structure pointer.*/
g_lpuartStatePtr[instance] = lpuartEdmaStatePtr;
/* Set LPUART clock source */
CLOCK_SYS_SetLpuartSrc(instance, lpuartUserConfig->clockSource);
/* Un-gate LPUART module clock */
CLOCK_SYS_EnableLpuartClock(instance);
/* Initialize LPUART to a known state. */
LPUART_HAL_Init(base);
/* Create Semaphore for txIrq and rxIrq. */
OSA_SemaCreate(&lpuartEdmaStatePtr->txIrqSync, 0);
OSA_SemaCreate(&lpuartEdmaStatePtr->rxIrqSync, 0);
/* LPUART clock source is either system or bus clock depending on instance */
lpuartSourceClock = CLOCK_SYS_GetLpuartFreq(instance);
/* Initialize LPUART baud rate, bit count, parity and stop bit. */
LPUART_HAL_SetBaudRate(base, lpuartSourceClock, lpuartUserConfig->baudRate);
LPUART_HAL_SetBitCountPerChar(base, lpuartUserConfig->bitCountPerChar);
LPUART_HAL_SetParityMode(base, lpuartUserConfig->parityMode);
LPUART_HAL_SetStopBitCount(base, lpuartUserConfig->stopBitCount);
switch (instance)
{
#if (FSL_FEATURE_LPUART_HAS_SEPARATE_DMA_RX_TX_REQn(0) == 1)
case 0:
lpuartRxEdmaRequest = kDmaRequestMux0LPUART0Rx;
lpuartTxEdmaRequest = kDmaRequestMux0LPUART0Tx;
break;
#endif
#if (FSL_FEATURE_LPUART_HAS_SEPARATE_DMA_RX_TX_REQn(1) == 1)
case 1:
lpuartRxEdmaRequest = kDmaRequestMux0LPUART1Rx;
lpuartTxEdmaRequest = kDmaRequestMux0LPUART1Tx;
break;
#endif
#if (FSL_FEATURE_LPUART_HAS_SEPARATE_DMA_RX_TX_REQn(2) == 1)
case 2:
lpuartRxEdmaRequest = kDmaRequestMux0LPUART2Rx;
lpuartTxEdmaRequest = kDmaRequestMux0LPUART2Tx;
break;
#endif
#if (FSL_FEATURE_LPUART_HAS_SEPARATE_DMA_RX_TX_REQn(3) == 1)
case 3:
lpuartRxEdmaRequest = kDmaRequestMux0LPUART3Rx;
lpuartTxEdmaRequest = kDmaRequestMux0LPUART3Tx;
break;
#endif
#if (FSL_FEATURE_LPUART_HAS_SEPARATE_DMA_RX_TX_REQn(4) == 1)
case 4:
lpuartRxEdmaRequest = kDmaRequestMux0LPUART4Rx;
lpuartTxEdmaRequest = kDmaRequestMux0LPUART4Tx;
break;
#endif
default :
break;
}
/*--------------- Setup RX ------------------*/
/* Request DMA channels for RX FIFO. */
EDMA_DRV_RequestChannel(kEDMAAnyChannel, lpuartRxEdmaRequest,
&lpuartEdmaStatePtr->edmaLpuartRx);
EDMA_DRV_InstallCallback(&lpuartEdmaStatePtr->edmaLpuartRx,
LPUART_DRV_EdmaRxCallback, (void *)instance);
/*--------------- Setup TX ------------------*/
/* Request DMA channels for TX FIFO. */
EDMA_DRV_RequestChannel(kEDMAAnyChannel, lpuartTxEdmaRequest,
&lpuartEdmaStatePtr->edmaLpuartTx);
EDMA_DRV_InstallCallback(&lpuartEdmaStatePtr->edmaLpuartTx,
LPUART_DRV_EdmaTxCallback, (void *)instance);
/* Finally, enable the LPUART transmitter and receiver.
* Enable DMA trigger when transmit data register empty,
* and receive data register full. */
LPUART_HAL_SetTxDmaCmd(base, true);
LPUART_HAL_SetRxDmaCmd(base, true);
LPUART_HAL_SetTransmitterCmd(base, true);
LPUART_HAL_SetReceiverCmd(base, true);
return kStatus_LPUART_Success;
}
/*FUNCTION**********************************************************************
*
* Function Name : UART_DRV_DmaInit
* Description : This function initializes a UART instance for operation.
* This function will initialize the run-time state structure to keep track of
* the on-going transfers, ungate the clock to the UART module, initialize the
* module to user defined settings and default settings, configure UART DMA
* and enable the UART module transmitter and receiver.
* The following is an example of how to set up the uart_dma_state_t and the
* uart_user_config_t parameters and how to call the UART_DRV_DmaInit function
* by passing in these parameters:
* uart_user_config_t uartConfig;
* uartConfig.baudRate = 9600;
* uartConfig.bitCountPerChar = kUart8BitsPerChar;
* uartConfig.parityMode = kUartParityDisabled;
* uartConfig.stopBitCount = kUartOneStopBit;
* uart_dma_state_t uartDmaState;
* UART_DRV_DmaInit(instance, &uartDmaState, &uartConfig);
*
*END**************************************************************************/
uart_status_t UART_DRV_DmaInit(uint32_t instance,
uart_dma_state_t * uartDmaStatePtr,
const uart_dma_user_config_t * uartUserConfig)
{
assert(uartDmaStatePtr && uartUserConfig);
assert(g_uartBase[instance]);
assert(instance < UART_INSTANCE_COUNT);
/* This driver only support UART instances with separate DMA channels for
* both Tx and Rx.*/
assert(FSL_FEATURE_UART_HAS_SEPARATE_DMA_RX_TX_REQn(instance) == 1);
UART_Type * base = g_uartBase[instance];
uint32_t uartSourceClock = 0;
dma_request_source_t uartTxDmaRequest = kDmaRequestMux0Disable;
dma_request_source_t uartRxDmaRequest = kDmaRequestMux0Disable;
/* Exit if current instance is already initialized. */
if (g_uartStatePtr[instance])
{
return kStatus_UART_Initialized;
}
/* Clear the state structure for this instance. */
memset(uartDmaStatePtr, 0, sizeof(uart_dma_state_t));
/* Save runtime structure pointer.*/
g_uartStatePtr[instance] = uartDmaStatePtr;
/* Un-gate UART module clock */
CLOCK_SYS_EnableUartClock(instance);
/* Initialize UART to a known state. */
UART_HAL_Init(base);
/* Create Semaphore for txIrq and rxIrq. */
OSA_SemaCreate(&uartDmaStatePtr->txIrqSync, 0);
OSA_SemaCreate(&uartDmaStatePtr->rxIrqSync, 0);
/* UART clock source is either system or bus clock depending on instance */
uartSourceClock = CLOCK_SYS_GetUartFreq(instance);
/* Initialize UART baud rate, bit count, parity and stop bit. */
UART_HAL_SetBaudRate(base, uartSourceClock, uartUserConfig->baudRate);
UART_HAL_SetBitCountPerChar(base, uartUserConfig->bitCountPerChar);
UART_HAL_SetParityMode(base, uartUserConfig->parityMode);
#if FSL_FEATURE_UART_HAS_STOP_BIT_CONFIG_SUPPORT
UART_HAL_SetStopBitCount(base, uartUserConfig->stopBitCount);
#endif
/* Enable DMA trigger when transmit data register empty,
* and receive data register full. */
UART_HAL_SetTxDmaCmd(base, true);
UART_HAL_SetRxDmaCmd(base, true);
switch (instance)
{
#if (FSL_FEATURE_UART_HAS_SEPARATE_DMA_RX_TX_REQn(0) == 1)
case 0:
uartRxDmaRequest = kDmaRequestMux0UART0Rx;
uartTxDmaRequest = kDmaRequestMux0UART0Tx;
break;
#endif
#if (FSL_FEATURE_UART_HAS_SEPARATE_DMA_RX_TX_REQn(1) == 1)
case 1:
uartRxDmaRequest = kDmaRequestMux0UART1Rx;
uartTxDmaRequest = kDmaRequestMux0UART1Tx;
break;
#endif
#if (FSL_FEATURE_UART_HAS_SEPARATE_DMA_RX_TX_REQn(2) == 1)
case 2:
uartRxDmaRequest = kDmaRequestMux0UART2Rx;
uartTxDmaRequest = kDmaRequestMux0UART2Tx;
break;
#endif
default :
break;
}
/* Request DMA channels for RX FIFO. */
DMA_DRV_RequestChannel(kDmaAnyChannel, uartRxDmaRequest,
&uartDmaStatePtr->dmaUartRx);
DMA_DRV_RegisterCallback(&uartDmaStatePtr->dmaUartRx,
UART_DRV_DmaRxCallback, (void *)instance);
/* Request DMA channels for TX FIFO. */
DMA_DRV_RequestChannel(kDmaAnyChannel, uartTxDmaRequest,
&uartDmaStatePtr->dmaUartTx);
DMA_DRV_RegisterCallback(&uartDmaStatePtr->dmaUartTx,
UART_DRV_DmaTxCallback, (void *)instance);
/* Finally, enable the UART transmitter and receiver*/
UART_HAL_EnableTransmitter(base);
UART_HAL_EnableReceiver(base);
return kStatus_UART_Success;
}
/*FUNCTION**********************************************************************
*
* Function Name : DSPI_DRV_MasterInit
* Description : Initialize a DSPI instance for master mode operation.
* This function uses a CPU interrupt driven method for transferring data.
* This function will initialize the run-time state structure to keep track of the on-going
* transfers, ungate the clock to the DSPI module, reset the DSPI module, initialize the module
* to user defined settings and default settings, configure the IRQ state structure and enable
* the module-level interrupt to the core, and enable the DSPI module.
* The CTAR parameter is special in that it allows the user to have different SPI devices
* connected to the same DSPI module instance in conjunction with different peripheral chip
* selects. Each CTAR contains the bus attributes associated with that particular SPI device.
* For simplicity and for most use cases where only one SPI device is connected per DSPI module
* instance, it is recommended to use CTAR0.
* The following is an example of how to set up the dspi_master_state_t and the
* dspi_master_user_config_t parameters and how to call the DSPI_DRV_MasterInit function by passing
* in these parameters:
* dspi_master_state_t dspiMasterState; <- the user simply allocates memory for this struct
* uint32_t calculatedBaudRate;
* dspi_master_user_config_t userConfig; <- the user fills out members for this struct
* userConfig.isChipSelectContinuous = false;
* userConfig.isSckContinuous = false;
* userConfig.pcsPolarity = kDspiPcs_ActiveLow;
* userConfig.whichCtar = kDspiCtar0;
* userConfig.whichPcs = kDspiPcs0;
* DSPI_DRV_MasterInit(masterInstance, &dspiMasterState, &userConfig);
*
*END**************************************************************************/
dspi_status_t DSPI_DRV_MasterInit(uint32_t instance,
dspi_master_state_t * dspiState,
const dspi_master_user_config_t * userConfig)
{
uint32_t dspiSourceClock;
dspi_status_t errorCode = kStatus_DSPI_Success;
SPI_Type *base = g_dspiBase[instance];
/* Clear the run-time state struct for this instance.*/
memset(dspiState, 0, sizeof(* dspiState));
/* Note, remember to first enable clocks to the DSPI module before making any register accesses
* Enable clock for DSPI
*/
CLOCK_SYS_EnableSpiClock(instance);
/* Get module clock freq*/
dspiSourceClock = CLOCK_SYS_GetSpiFreq(instance);
/* Configure the run-time state struct with the DSPI source clock */
dspiState->dspiSourceClock = dspiSourceClock;
/* Configure the run-time state struct with the data command parameters*/
dspiState->whichCtar = userConfig->whichCtar; /* set the dspiState struct CTAR*/
dspiState->whichPcs = userConfig->whichPcs; /* set the dspiState struct whichPcs*/
dspiState->isChipSelectContinuous = userConfig->isChipSelectContinuous; /* continuous PCS*/
/* Initialize the DSPI module registers to default value, which disables the module */
DSPI_HAL_Init(base);
/* Init the interrupt sync object.*/
OSA_SemaCreate(&dspiState->irqSync, 0);
/* Initialize the DSPI module with user config */
/* Set to master mode.*/
DSPI_HAL_SetMasterSlaveMode(base, kDspiMaster);
/* Configure for continuous SCK operation*/
DSPI_HAL_SetContinuousSckCmd(base, userConfig->isSckContinuous);
/* Configure for peripheral chip select polarity*/
DSPI_HAL_SetPcsPolarityMode(base, userConfig->whichPcs, userConfig->pcsPolarity);
/* Enable fifo operation (regardless of FIFO depth) */
DSPI_HAL_SetFifoCmd(base, true, true);
/* Initialize the configurable delays: PCS-to-SCK, prescaler = 0, scaler = 1 */
DSPI_HAL_SetDelay(base, userConfig->whichCtar, 0, 1, kDspiPcsToSck);
/* Save runtime structure pointers to irq handler can point to the correct state structure*/
g_dspiStatePtr[instance] = dspiState;
/* enable the interrupt*/
INT_SYS_EnableIRQ(g_dspiIrqId[instance]);
/* DSPI system enable */
DSPI_HAL_Enable(base);
/* Start the transfer process in the hardware */
DSPI_HAL_StartTransfer(base);
return errorCode;
}
/*FUNCTION**********************************************************************
*
* Function Name : SPI_DRV_DmaMasterInit
* Description : Initializes a SPI instance for master mode operation to work with DMA.
* This function uses a dma driven method for transferring data.
* this function initializes the run-time state structure to track the ongoing
* transfers, ungates the clock to the SPI module, resets the SPI module, initializes the module
* to user defined settings and default settings, configures the IRQ state structure, enables
* the module-level interrupt to the core, and enables the SPI module.
*
* This initialization function also configures the DMA module by requesting channels for DMA
* operation.
*
*END**************************************************************************/
spi_status_t SPI_DRV_DmaMasterInit(uint32_t instance, spi_dma_master_state_t * spiDmaState)
{
SPI_Type *base = g_spiBase[instance];
/* Clear the state for this instance.*/
memset(spiDmaState, 0, sizeof(* spiDmaState));
/* Enable clock for SPI*/
CLOCK_SYS_EnableSpiClock(instance);
/* configure the run-time state struct with the source clock value */
spiDmaState->spiSourceClock = CLOCK_SYS_GetSpiFreq(instance);
/* Reset the SPI module to it's default state, which includes SPI disabled */
SPI_HAL_Init(base);
/* Init the interrupt sync object.*/
if (OSA_SemaCreate(&spiDmaState->irqSync, 0) != kStatus_OSA_Success)
{
return kStatus_SPI_Error;
}
/* Set SPI to master mode */
SPI_HAL_SetMasterSlave(base, kSpiMaster);
/* Set slave select to automatic output mode */
SPI_HAL_SetSlaveSelectOutputMode(base, kSpiSlaveSelect_AutomaticOutput);
/* Set the SPI pin mode to normal mode */
SPI_HAL_SetPinMode(base, kSpiPinMode_Normal);
#if FSL_FEATURE_SPI_FIFO_SIZE
if (g_spiFifoSize[instance] != 0)
{
/* If SPI module contains a FIFO, enable it and set watermarks to half full/empty */
SPI_HAL_SetFifoMode(base, true, kSpiTxFifoOneHalfEmpty, kSpiRxFifoOneHalfFull);
/* Set the interrupt clearing mechansim select for later use in driver to clear
* status flags
*/
SPI_HAL_SetIntClearCmd(base, true);
}
#endif
/* Save runtime structure pointers to irq handler can point to the correct state structure*/
g_spiStatePtr[instance] = spiDmaState;
/*****************************************
* Request DMA channel for RX and TX FIFO
*****************************************/
/* This channel transfers data from RX FIFO to receiveBuffer */
if (instance == 0)
{
/* Request DMA channel for RX FIFO */
DMA_DRV_RequestChannel(kDmaAnyChannel, kDmaRequestMux0SPI0Rx, &spiDmaState->dmaReceive);
/* Request DMA channel for TX FIFO */
DMA_DRV_RequestChannel(kDmaAnyChannel, kDmaRequestMux0SPI0Tx, &spiDmaState->dmaTransmit);
}
#if (SPI_INSTANCE_COUNT > 1)
else
{
/* Request DMA channel for RX FIFO */
DMA_DRV_RequestChannel(kDmaAnyChannel, kDmaRequestMux0SPI1Rx, &spiDmaState->dmaReceive);
/* Request DMA channel for TX FIFO */
DMA_DRV_RequestChannel(kDmaAnyChannel, kDmaRequestMux0SPI1Tx, &spiDmaState->dmaTransmit);
}
#endif
/* Enable SPI interrupt.*/
INT_SYS_EnableIRQ(g_spiIrqId[instance]);
/* SPI system Enable */
SPI_HAL_Enable(base);
return kStatus_SPI_Success;
}
/*FUNCTION**********************************************************************
*
* Function Name : LPUART_DRV_DmaInit
* Description : This function initializes a LPUART instance for operation.
* This function will initialize the run-time state structure to keep track of
* the on-going transfers, ungate the clock to the LPUART module, initialize the
* module to user defined settings and default settings, configure LPUART DMA
* and enable the LPUART module transmitter and receiver.
* The following is an example of how to set up the lpuart_dma_state_t and the
* lpuart_user_config_t parameters and how to call the LPUART_DRV_DmaInit function
* by passing in these parameters:
* lpuart_user_config_t lpuartConfig;
* lpuartConfig.baudRate = 9600;
* lpuartConfig.bitCountPerChar = kLpuart8BitsPerChar;
* lpuartConfig.parityMode = kLpuartParityDisabled;
* lpuartConfig.stopBitCount = kLpuartOneStopBit;
* lpuart_dma_state_t lpuartDmaState;
* LPUART_DRV_DmaInit(instance, &lpuartDmaState, &lpuartConfig);
*
*END**************************************************************************/
lpuart_status_t LPUART_DRV_DmaInit(uint32_t instance,
lpuart_dma_state_t * lpuartDmaStatePtr,
const lpuart_dma_user_config_t * lpuartUserConfig)
{
assert(lpuartDmaStatePtr && lpuartUserConfig);
assert(instance < LPUART_INSTANCE_COUNT);
LPUART_Type * base = g_lpuartBase[instance];
uint32_t lpuartSourceClock = 0;
dma_request_source_t lpuartTxDmaRequest = kDmaRequestMux0Disable;
dma_request_source_t lpuartRxDmaRequest = kDmaRequestMux0Disable;
/* Exit if current instance is already initialized. */
if (g_lpuartStatePtr[instance])
{
return kStatus_LPUART_Initialized;
}
/* Clear the state structure for this instance. */
memset(lpuartDmaStatePtr, 0, sizeof(lpuart_dma_state_t));
/* Save runtime structure pointer.*/
g_lpuartStatePtr[instance] = lpuartDmaStatePtr;
/* Un-gate LPUART module clock */
CLOCK_SYS_EnableLpuartClock(instance);
/* Set LPUART clock source */
CLOCK_SYS_SetLpuartSrc(instance, lpuartUserConfig->clockSource);
/* Initialize LPUART to a known state. */
LPUART_HAL_Init(base);
/* Create Semaphore for txIrq and rxIrq. */
OSA_SemaCreate(&lpuartDmaStatePtr->txIrqSync, 0);
OSA_SemaCreate(&lpuartDmaStatePtr->rxIrqSync, 0);
/* LPUART clock source is either system or bus clock depending on instance */
lpuartSourceClock = CLOCK_SYS_GetLpuartFreq(instance);
/* Initialize LPUART baud rate, bit count, parity and stop bit. */
LPUART_HAL_SetBaudRate(base, lpuartSourceClock, lpuartUserConfig->baudRate);
LPUART_HAL_SetBitCountPerChar(base, lpuartUserConfig->bitCountPerChar);
LPUART_HAL_SetParityMode(base, lpuartUserConfig->parityMode);
#if FSL_FEATURE_LPUART_HAS_STOP_BIT_CONFIG_SUPPORT
LPUART_HAL_SetStopBitCount(base, lpuartUserConfig->stopBitCount);
#endif
/* Enable DMA trigger when transmit data register empty,
* and receive data register full. */
LPUART_HAL_SetTxDmaCmd(base, true);
LPUART_HAL_SetRxDmaCmd(base, true);
switch (instance)
{
case 0:
lpuartRxDmaRequest = kDmaRequestMux0LPUART0Rx;
lpuartTxDmaRequest = kDmaRequestMux0LPUART0Tx;
break;
default :
break;
}
/* Request DMA channels for RX FIFO. */
DMA_DRV_RequestChannel(kDmaAnyChannel, lpuartRxDmaRequest,
&lpuartDmaStatePtr->dmaLpuartRx);
DMA_DRV_RegisterCallback(&lpuartDmaStatePtr->dmaLpuartRx,
LPUART_DRV_DmaRxCallback, (void *)instance);
/* Request DMA channels for TX FIFO. */
DMA_DRV_RequestChannel(kDmaAnyChannel, lpuartTxDmaRequest,
&lpuartDmaStatePtr->dmaLpuartTx);
DMA_DRV_RegisterCallback(&lpuartDmaStatePtr->dmaLpuartTx,
LPUART_DRV_DmaTxCallback, (void *)instance);
/* Finally, enable the LPUART transmitter and receiver*/
LPUART_HAL_SetTransmitterCmd(base, true);
LPUART_HAL_SetReceiverCmd(base, true);
return kStatus_LPUART_Success;
}
