void LCD_Clear( void )
{
OSRAMClear();
gX = 0;
gY = 0;
} // LCD_Clear
static void vPrintTask( void *pvParameters )
{
char *pcMessage;
unsigned portBASE_TYPE uxLine = 0, uxRow = 0;
for( ;; ) {
/* Wait for a message to arrive. */
xQueueReceive( xPrintQueue, &pcMessage, portMAX_DELAY );
/* Write the message to the LCD. */
uxRow++;
uxLine++;
OSRAMClear();
OSRAMStringDraw( pcMessage, uxLine & 0x3f, uxRow & 0x01);
}
}
//*****************************************************************************
//
//! Initialize the OLED display.
//!
//! \param bFast is a boolean that is \e true if the I2C interface should be
//! run at 400 kbps and \e false if it should be run at 100 kbps.
//!
//! This function initializes the I2C interface to the OLED display and
//! configures the SSD0303 controller on the panel.
//!
//! This function is contained in <tt>osram96x16.c</tt>, with
//! <tt>osram96x16.h</tt> containing the API definition for use by
//! applications.
//!
//! \return None.
//
//*****************************************************************************
void
OSRAMInit(tBoolean bFast)
{
unsigned long ulIdx;
//
// Enable the I2C and GPIO port B blocks as they are needed by this driver.
//
SysCtlPeripheralEnable(SYSCTL_PERIPH_I2C);
SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOB);
//
// Configure the I2C SCL and SDA pins for I2C operation.
//
GPIOPinTypeI2C(GPIO_PORTB_BASE, GPIO_PIN_2 | GPIO_PIN_3);
//
// Initialize the I2C master.
//
I2CMasterInitExpClk(I2C_MASTER_BASE, SysCtlClockGet(), bFast);
//
// Compute the inter-byte delay for the SSD0303 controller. This delay is
// dependent upon the I2C bus clock rate; the slower the clock the longer
// the delay required.
//
// The derivation of this formula is based on a measured delay of
// OSRAMDelay(1700) for a 100 kHz I2C bus with the CPU running at 50 MHz
// (referred to as C). To scale this to the delay for a different CPU
// speed (since this is just a CPU-based delay loop) is:
//
// f(CPU)
// C * ----------
// 50,000,000
//
// To then scale this to the actual I2C rate (since it won't always be
// precisely 100 kHz):
//
// f(CPU) 100,000
// C * ---------- * -------
// 50,000,000 f(I2C)
//
// This equation will give the inter-byte delay required for any
// configuration of the I2C master. But, as arranged it is impossible to
// directly compute in 32-bit arithmetic (without loosing a lot of
// accuracy). So, the equation is simplified.
//
// Since f(I2C) is generated by dividing down from f(CPU), replace it with
// the equivalent (where TPR is the value programmed into the Master Timer
// Period Register of the I2C master, with the 1 added back):
//
// 100,000
// f(CPU) -------
// C * ---------- * f(CPU)
// 50,000,000 ------------
// 2 * 10 * TPR
//
// Inverting the dividend in the last term:
//
// f(CPU) 100,000 * 2 * 10 * TPR
// C * ---------- * ----------------------
// 50,000,000 f(CPU)
//
// The f(CPU) now cancels out.
//
// 100,000 * 2 * 10 * TPR
// C * ----------------------
// 50,000,000
//
// Since there are no clock frequencies left in the equation, this equation
// also works for 400 kHz bus operation as well, since the 100,000 in the
// numerator becomes 400,000 but C is 1/4, which cancel out each other.
// Reducing the constants gives:
//
// TPR TPR TPR
// C * --- = 1700 * --- = 340 * --- = 68 * TPR
// 25 25 5
//
// Note that the constant C is actually a bit larger than it needs to be in
// order to provide some safety margin.
//
g_ulDelay = 68 * (HWREG(I2C_MASTER_BASE + I2C_MASTER_O_TPR) + 1);
//
// Initialize the SSD0303 controller. Loop through the initialization
// sequence doing a single I2C transfer for each command.
//
for(ulIdx = 0; ulIdx < sizeof(g_pucOSRAMInit);
ulIdx += g_pucOSRAMInit[ulIdx] + 1) {
//
// Send this command.
//
OSRAMWriteFirst(g_pucOSRAMInit[ulIdx + 1]);
OSRAMWriteArray(g_pucOSRAMInit + ulIdx + 2, g_pucOSRAMInit[ulIdx] - 2);
OSRAMWriteFinal(g_pucOSRAMInit[ulIdx + g_pucOSRAMInit[ulIdx]]);
}
//
// Clear the frame buffer.
//
OSRAMClear();
}