int task_create(task_t* tasks, size_t num_tasks) { // Sanity checks. if (num_tasks > OS_AVAIL_TASKS) return -EINVAL; /* * Assign schedule via RMA scheduling. */ task_t* sorted_tasks[num_tasks]; size_t i; // Prep for (i = 0; i < num_tasks; i++) { sorted_tasks[i] = tasks + i; } INT_ATOMIC_START; // Perform UB test. if (!assign_schedule(sorted_tasks, num_tasks)) return -EFAULT; // Init TCBs if (!allocate_tasks(sorted_tasks, num_tasks)) return -EFAULT; // Start device interrupt timer. reg_write(OSTMR_OSMR_ADDR(2), reg_read(OSTMR_OSCR_ADDR) + get_ticks(DEV_INT_PERIOD)); // Start tasks dispatch_nosave(); INT_ATOMIC_END; return 0; }
void init_timer(void) { reg_write(INT_ICMR_ADDR, 1<<INT_OSTMR_0); reg_write(OSTMR_OSMR_ADDR(0), OSTMR_FREQ/100); reg_write(OSTMR_OIER_ADDR, OSTMR_OIER_E0); reg_write(OSTMR_OSCR_ADDR, 0x0); }
int C_IRQ_Handler() { // get the content of OSCR and OSSR volatile uint32_t oscr_val = reg_read(OSTMR_OSCR_ADDR); volatile uint32_t ossr_val = reg_read(OSTMR_OSSR_ADDR); uint32_t next_match_time; // If interrupt on OSMR0 happened if (ossr_val == 1) { // clear OSSR bit reg_set(OSTMR_OSSR_ADDR, OSTMR_OSSR_M0); // increment time interval by 10ms global_time += TIME_INTERVAL; // increment match register to next match value next_match_time += oscr_val + OSTMR_FREQ / OSTMR_DIVISOR; // store value to OSMR0 reg_write(OSTMR_OSMR_ADDR(0), next_match_time); } int value=0; // value=write(regs[0],(void *)regs[1],regs[2]); return value; }
void C_IRQ_Handler() { printf("In C_IRQ_Handler\n"); uint32_t next_time; // unsigned int icpInt = reg_read(INT_ICIP_ADDR); // printf("icpInt: %x\n", icpInt); uint32_t OSCR = reg_read(OSTMR_OSCR_ADDR); // uint32_t OSMR = reg_read(OSTMR_OSMR_ADDR(0)); // uint32_t OSSR = reg_read(OSTMR_OSSR_ADDR); // printf("OSCR: %d, OSMR: %d, OSSR: %d\n", OSCR, OSMR, OSSR); if(reg_read(OSTMR_OSSR_ADDR) == 1) { // printf("\n\n\n\ndo you get here???\n\n\n\n"); //Incrementing by 10 milliseconds addTimer(1); //Increment Match Register next_time = OSCR + (OSTMR_FREQ_VERDEX); // printf("New OSMR: %d\n", next_time); //Store incremented value reg_write(OSTMR_OSMR_ADDR(0), next_time); //irq reg_set(OSTMR_OSSR_ADDR, OSTMR_OSSR_M0); } //return; printf("\n leaving C_IRQ_handler\n"); I_Handler_Cleanup(); return; }
void c_irq_handler() { //i_bit indicates if timer interrupt has occurred uint32_t i_bit = reg_read(INT_ICPR_ADDR); uint32_t next_time; if((i_bit & (1<<INT_OSTMR_0)) == (1<<INT_OSTMR_0)) { /*printf("IRQ!\n"); //reload the match register with the max value reg_write(OSTMR_OSMR_ADDR(0), 0xffffffff); reg_set(OSTMR_OSSR_ADDR, OSTMR_OSSR_M0); // clear OSSR bit */ //os_timer_interrupt_handler(); next_time = reg_read(OSTMR_OSMR_ADDR(0)); next_time += TICKS_FROM_10MILLIS(1); // notes next interrupt time reg_write(OSTMR_OSMR_ADDR(0), next_time); // writes it in to OSMR reg_set(OSTMR_OSSR_ADDR, 0x1); // clears OSSR to allow intterupt incrTimer(); // increases personal timer } }
//This function is called on all IRQ interrupts void timer_inc(void) { //increment the number of the timer ticks ++num_timer_tick; //reset the OSSR[M0]bit reg_set(OSTMR_OSSR_ADDR, OSTMR_OSSR_M0); osmr_count += CLOCKS_PER_TICK; //reset the OSCR to 0 reg_write(OSTMR_OSMR_ADDR(0), osmr_count); }
void irq_handler(void){ if((reg_read(INT_ICPR_ADDR) & (INT_ICCR_DIM << INT_OSTMR_0)) && (reg_read(OSTMR_OSSR_ADDR) & OSTMR_OSSR_M0)){ kernel_time += irq_elapse_time; reg_write(OSTMR_OSMR_ADDR(0), reg_read(OSTMR_OSCR_ADDR) + irq_elapse_count); reg_set(OSTMR_OSSR_ADDR, OSTMR_OSSR_M0); } return ; }
/* in this function, we configure the OS timer register */ void timer_init(void) { osmr_count = CLOCKS_PER_TICK; // init OSCR to 0 reg_write(OSTMR_OSCR_ADDR, 0); // init OSMR0 to num_clock reg_write(OSTMR_OSMR_ADDR(0), osmr_count); /* * set OIER last bit 1 to enbale match between OSCR * and OSMR0 to assert OSSR[M0] */ reg_set(OSTMR_OIER_ADDR, OSTMR_OIER_E0); }
void setup_peripheral_device(unsigned *ICMR, unsigned *ICLR, unsigned *OIER){ *ICMR = reg_read(INT_ICMR_ADDR); *ICLR = reg_read(INT_ICLR_ADDR); *OIER = reg_read(OSTMR_OIER_ADDR); reg_write(INT_ICMR_ADDR,INT_ICCR_DIM<<INT_OSTMR_0); reg_write(INT_ICLR_ADDR,0x0); reg_clear(OSTMR_OIER_ADDR,OSTMR_OIER_E0|OSTMR_OIER_E1|OSTMR_OIER_E2|OSTMR_OIER_E3); reg_set(OSTMR_OIER_ADDR,OSTMR_OIER_E0); reg_write(OSTMR_OSMR_ADDR(0),reg_read(OSTMR_OSCR_ADDR)+irq_elapse_count); }
// This function is called on all IRQ interrupts void timer_inc(void) { uint32_t ossr; /* increment the number of the timer ticks */ ++num_timer_tick; /* add clocks to OSMR */ osmr_count += CLOCKS_PER_TICK; reg_write(OSTMR_OSMR_ADDR(0), osmr_count); /* acknowledge interupt and set OSSR */ ossr = reg_read(OSTMR_OSSR_ADDR); ossr |= OSTMR_OSSR_M0; reg_write(OSTMR_OSSR_ADDR, ossr); /* wake up any tasks waiting on devices */ dev_update(num_timer_tick * MS_PER_TICK); }
/* IRQ_Handler updates system time whenever OS timer match 0 IRQ is serviced */ void irq_handler() { // ensure the irq is that from the match0 and counter0 if (reg_read(INT_ICPR_ADDR) & (1 << 26)) { // update the current time current_time += 10; //handshake reg_set(OSTMR_OSSR_ADDR,OSTMR_OSSR_M0); // call again in 10 millis unsigned new_time = (unsigned)CLOCK_TO_10_MILLI + reg_read(OSTMR_OSCR_ADDR); reg_write(OSTMR_OSMR_ADDR(0), new_time); if (task_created) { dev_update(current_time); } } }
/* in this function, we configure the OS timer register */ void timer_init(void) { //size_t num_clock; //calculate the clocks for a time unit: 10ms for now //Will change to the following line if set to 10ms //num_clock = OSTMR_FREQ/OS_TICKS_PER_SEC; //num_clock = OSTMR_FREQ/(S_TO_MS/MS_PER_TICK); osmr_count = CLOCKS_PER_TICK; //init OSCR to 0 reg_write(OSTMR_OSCR_ADDR, 0); //init OSMR0 to num_clock reg_write(OSTMR_OSMR_ADDR(0), osmr_count); /* * set OIER last bit 1 to enbale match between OSCR * and OSMR0 to assert OSSR[M0] */ reg_set(OSTMR_OIER_ADDR, OSTMR_OIER_E0); }
sys_time = 0; time_drift = 0; // Save regs //unsigned ICMR, ICLR, OIER; //ICMR = reg_read(INT_ICMR_ADDR); //ICLR = reg_read(INT_ICLR_ADDR); //OIER = reg_read(OSTMR_OIER_ADDR); // Set regs reg_write(INT_ICMR_ADDR, 1<<INT_OSTMR_0);//Only enable OSTMR0 reg_write(INT_ICLR_ADDR, 0x0);//Set all interrupts from OSTMR0 to be IRQ reg_clear(OSTMR_OIER_ADDR, OSTMR_OIER_E1|OSTMR_OIER_E2|OSTMR_OIER_E3); reg_set(OSTMR_OIER_ADDR, OSTMR_OIER_E0); reg_write(OSTMR_OSMR_ADDR(0), reg_read(OSTMR_OSCR_ADDR)+TIME_COUNTER_STEP); //printf("mutex_init start\n"); mutex_init(); //printf("mutex init finished\n"); // Change mode, jump to usr program //printf("set up start\n"); setup(argc, argv); //printf("set up finished\n"); /*// Restore regs reg_write(INT_ICMR_ADDR, ICMR); reg_write(INT_ICLR_ADDR, ICLR); reg_write(OSTMR_OIER_ADDR, OIER); // Recover old SWI Handler recover_MyHandler(swi_vec_addr, swi_instr1, swi_instr2);
int kmain(int argc, char** argv, uint32_t table) { app_startup(); /* bss is valid after this point */ global_data = table; unsigned long int oldInstr, oldInstr2, exitVal, *s_addr; unsigned long int *irq_addr, oldIrq, oldIrq2, *ubootIrqAddr; unsigned long int *pointer, *ubootSwiAddr; unsigned long int *irqPointer; uint32_t ICMR, ICLR, OIER; pointer = (unsigned long int*) 0x08; irqPointer = (unsigned long int*) 0x18; initializeTimer(); oldInstr = *pointer; oldInstr2 = *(pointer+1); if((oldInstr & 0xfe1ff000) != 0xe41ff000) { return 0xbadc0de; } if((oldInstr & 0x00800000) == 0x00800000) s_addr = (unsigned long int*) ((oldInstr & 0xfff) + 0x10); else s_addr = (unsigned long int*) (0x10 - (oldInstr & 0xfff)); ubootSwiAddr = (unsigned long int*) *(s_addr); oldIrq = *irqPointer; oldIrq2 = *(irqPointer+1); printf("hello"); if((oldIrq & 0xfe1ff000) != 0xe41ff000) { return 0xbadc0de; } if((oldIrq & 0x00800000) == 0x00800000) irq_addr = (unsigned long int*) ((oldIrq & 0xfff) + 0x10); else irq_addr = (unsigned long int*) (0x10 - (oldIrq & 0xfff)); ubootIrqAddr = (unsigned long int*) *(irq_addr); *(ubootSwiAddr) = 0xe51ff004; *(ubootSwiAddr + 1) = (unsigned) &S_Handler; *(ubootIrqAddr) = 0xe51ff004; *(ubootIrqAddr+1) = (unsigned) &I_Handler; printf("hey"); ICMR = reg_read(INT_ICMR_ADDR); ICLR = reg_read(INT_ICLR_ADDR); OIER = reg_read(OSTMR_OIER_ADDR); // set osmr match reg bit to 1 for interrupts reg_write(INT_ICMR_ADDR, 0x04000000); //make interrupts irq reg_write(INT_ICLR_ADDR, 0x0); // set match reg reg_write(OSTMR_OSMR_ADDR(0), 32500); // enable os timer interrupt for match 0 reg reg_write(OSTMR_OIER_ADDR, OSTMR_OIER_E0); // set clock reg to 0 reg_write(OSTMR_OSCR_ADDR, 0x0); //clear status reg reg_write(OSTMR_OSSR_ADDR, 0x0); printf("tit"); exitVal = (int)load_user_prog(argc, argv); *(ubootSwiAddr) = (unsigned long int) oldInstr; *(ubootSwiAddr + 1) = (unsigned long int) oldInstr2; *(ubootIrqAddr) = (unsigned long int) oldIrq; *(ubootIrqAddr+1) = (unsigned long int) oldIrq2; // restore interrupt shit reg_write(INT_ICMR_ADDR, ICMR); reg_write(INT_ICLR_ADDR, ICLR); reg_write(OSTMR_OIER_ADDR, OIER); return exitVal; }
int kmain(int argc, char** argv, uint32_t table) { app_startup(); /* bss is valid after this point */ global_data = table; unsigned long int oldSwi, oldSwi2, exitVal, *s_addr; unsigned long int *irq_addr, oldIrq, oldIrq2, *ubootIrqAddr, *ubootSwiAddr; uint32_t ICMR, ICLR, OIER, OSCR, OSMR, OSSR; oldSwi = *(unsigned long int *)SWI_PTR; oldSwi2 = *(unsigned long int *)(SWI_PTR+1); if((oldSwi & LDR_MASK) != GOOD_INSTRUCTION) { return BAD_CODE; } if((oldSwi & POSITIVE_OFFSET) == POSITIVE_OFFSET) s_addr = (unsigned long int*) ((oldSwi & OFFSET_MASK) + UBOOT_SWI_PC); else s_addr = (unsigned long int*) (UBOOT_SWI_PC - (oldSwi & OFFSET_MASK)); ubootSwiAddr = (unsigned long int*) *(s_addr); oldIrq = * (unsigned long int *) IRQ_PTR; oldIrq2 = *(unsigned long int *)(IRQ_PTR + 1); if((oldIrq & LDR_MASK) != GOOD_INSTRUCTION) { return BAD_CODE; } if((oldIrq & POSITIVE_OFFSET) == POSITIVE_OFFSET) irq_addr = (unsigned long int*) ((oldIrq & OFFSET_MASK) + UBOOT_IRQ_PC); else irq_addr = (unsigned long int*) (UBOOT_IRQ_PC - (oldIrq & OFFSET_MASK)); ubootIrqAddr = (unsigned long int*) *(irq_addr); *(ubootSwiAddr) = LDR_PC_OPCODE; *(ubootSwiAddr + 1) = (unsigned) &S_Handler; *(ubootIrqAddr) = LDR_PC_OPCODE; *(ubootIrqAddr+1) = (unsigned) &I_Handler; ICMR = reg_read(INT_ICMR_ADDR); ICLR = reg_read(INT_ICLR_ADDR); OIER = reg_read(OSTMR_OIER_ADDR); OSMR = reg_read(OSTMR_OSMR_ADDR(0)); OSCR = reg_read(OSTMR_OSCR_ADDR); OSSR = reg_read(OSTMR_OSSR_ADDR); // set osmr match reg bit to 1 for interrupts reg_write(INT_ICMR_ADDR, SET_ICMR_M0_IRQ); //make interrupts irq reg_write(INT_ICLR_ADDR, 0x0); // set match reg reg_write(OSTMR_OSMR_ADDR(0), OSTMR_FREQ_VERDEX/FREQ_MS_FACTOR); // enable os timer interrupt for match 0 reg reg_write(OSTMR_OIER_ADDR, OSTMR_OIER_E0); // set clock reg to 0 reg_write(OSTMR_OSCR_ADDR, 0x0); //clear status reg reg_write(OSTMR_OSSR_ADDR, 0x0); init_irq(); exitVal = (int)load_user_prog(argc, argv); *(ubootSwiAddr) = (unsigned long int) oldSwi; *(ubootSwiAddr + 1) = (unsigned long int) oldSwi2; *(ubootIrqAddr) = (unsigned long int) oldIrq; *(ubootIrqAddr+1) = (unsigned long int) oldIrq2; // restore interrupt registers reg_write(INT_ICMR_ADDR, ICMR); reg_write(INT_ICLR_ADDR, ICLR); reg_write(OSTMR_OIER_ADDR, OIER); reg_write(OSTMR_OSSR_ADDR, OSSR); reg_write(OSTMR_OSCR_ADDR, OSCR); reg_write(OSTMR_OSMR_ADDR(0), OSMR); return exitVal; }