static inline void emit_cb_setup(struct r200_context *r200, struct radeon_bo *bo, intptr_t offset, gl_format mesa_format, unsigned pitch, unsigned width, unsigned height) { uint32_t dst_pitch = pitch; uint32_t dst_format = 0; BATCH_LOCALS(&r200->radeon); /* XXX others? BE/LE? */ switch (mesa_format) { case MESA_FORMAT_ARGB8888: case MESA_FORMAT_XRGB8888: case MESA_FORMAT_RGBA8888: case MESA_FORMAT_RGBA8888_REV: dst_format = RADEON_COLOR_FORMAT_ARGB8888; break; case MESA_FORMAT_RGB565: dst_format = RADEON_COLOR_FORMAT_RGB565; break; case MESA_FORMAT_ARGB4444: dst_format = RADEON_COLOR_FORMAT_ARGB4444; break; case MESA_FORMAT_ARGB1555: dst_format = RADEON_COLOR_FORMAT_ARGB1555; break; case MESA_FORMAT_A8: case MESA_FORMAT_L8: case MESA_FORMAT_I8: dst_format = RADEON_COLOR_FORMAT_RGB8; break; default: break; } if (bo->flags & RADEON_BO_FLAGS_MACRO_TILE) dst_pitch |= R200_COLOR_TILE_ENABLE; if (bo->flags & RADEON_BO_FLAGS_MICRO_TILE) dst_pitch |= R200_COLOR_MICROTILE_ENABLE; BEGIN_BATCH_NO_AUTOSTATE(22); OUT_BATCH_REGVAL(R200_RE_AUX_SCISSOR_CNTL, 0); OUT_BATCH_REGVAL(R200_RE_CNTL, 0); OUT_BATCH_REGVAL(RADEON_RE_TOP_LEFT, 0); OUT_BATCH_REGVAL(RADEON_RE_WIDTH_HEIGHT, (((width - 1) << RADEON_RE_WIDTH_SHIFT) | ((height - 1) << RADEON_RE_HEIGHT_SHIFT))); OUT_BATCH_REGVAL(RADEON_RB3D_PLANEMASK, 0xffffffff); OUT_BATCH_REGVAL(RADEON_RB3D_BLENDCNTL, RADEON_SRC_BLEND_GL_ONE | RADEON_DST_BLEND_GL_ZERO); OUT_BATCH_REGVAL(RADEON_RB3D_CNTL, dst_format); OUT_BATCH_REGSEQ(RADEON_RB3D_COLOROFFSET, 1); OUT_BATCH_RELOC(offset, bo, offset, 0, RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0); OUT_BATCH_REGSEQ(RADEON_RB3D_COLORPITCH, 1); OUT_BATCH_RELOC(dst_pitch, bo, dst_pitch, 0, RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0); END_BATCH(); }
static void tex_emit(GLcontext *ctx, struct radeon_state_atom *atom) { r100ContextPtr r100 = R100_CONTEXT(ctx); BATCH_LOCALS(&r100->radeon); uint32_t dwords = atom->cmd_size; int i = atom->idx; radeonTexObj *t = r100->state.texture.unit[i].texobj; radeon_mipmap_level *lvl; if (t && t->mt && !t->image_override) dwords += 2; BEGIN_BATCH_NO_AUTOSTATE(dwords); OUT_BATCH_TABLE(atom->cmd, 3); if (t && t->mt && !t->image_override) { if ((ctx->Texture.Unit[i]._ReallyEnabled & TEXTURE_CUBE_BIT)) { lvl = &t->mt->levels[0]; OUT_BATCH_RELOC(lvl->faces[5].offset, t->mt->bo, lvl->faces[5].offset, RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, 0); } else { OUT_BATCH_RELOC(t->tile_bits, t->mt->bo, 0, RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, 0); } } else if (!t) { /* workaround for old CS mechanism */ OUT_BATCH(r100->radeon.radeonScreen->texOffset[RADEON_LOCAL_TEX_HEAP]); // OUT_BATCH(r100->radeon.radeonScreen); } else { OUT_BATCH(t->override_offset); } OUT_BATCH_TABLE((atom->cmd+4), 5); END_BATCH(); }
static void tex_emit_cs(struct gl_context *ctx, struct radeon_state_atom *atom) { r100ContextPtr r100 = R100_CONTEXT(ctx); BATCH_LOCALS(&r100->radeon); uint32_t dwords = atom->cmd_size; int i = atom->idx; radeonTexObj *t = r100->state.texture.unit[i].texobj; radeon_mipmap_level *lvl; int hastexture = 1; if (!t) hastexture = 0; else { if (!t->mt && !t->bo) hastexture = 0; } dwords += 1; if (hastexture) dwords += 2; else dwords -= 2; BEGIN_BATCH_NO_AUTOSTATE(dwords); OUT_BATCH(CP_PACKET0(RADEON_PP_TXFILTER_0 + (24 * i), 1)); OUT_BATCH_TABLE((atom->cmd + 1), 2); if (hastexture) { OUT_BATCH(CP_PACKET0(RADEON_PP_TXOFFSET_0 + (24 * i), 0)); if (t->mt && !t->image_override) { if ((ctx->Texture.Unit[i]._ReallyEnabled & TEXTURE_CUBE_BIT)) { lvl = &t->mt->levels[t->minLod]; OUT_BATCH_RELOC(lvl->faces[5].offset, t->mt->bo, lvl->faces[5].offset, RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, 0); } else { OUT_BATCH_RELOC(t->tile_bits, t->mt->bo, get_base_teximage_offset(t), RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, 0); } } else { if (t->bo) OUT_BATCH_RELOC(t->tile_bits, t->bo, 0, RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, 0); } } OUT_BATCH(CP_PACKET0(RADEON_PP_TXCBLEND_0 + (i * 24), 1)); OUT_BATCH_TABLE((atom->cmd+4), 2); OUT_BATCH(CP_PACKET0(RADEON_PP_BORDER_COLOR_0 + (i * 4), 0)); OUT_BATCH((atom->cmd[TEX_PP_BORDER_COLOR])); END_BATCH(); }
static inline void emit_cb_setup(struct r100_context *r100, struct radeon_bo *bo, intptr_t offset, gl_format mesa_format, unsigned pitch, unsigned width, unsigned height) { uint32_t dst_pitch = pitch; uint32_t dst_format = 0; BATCH_LOCALS(&r100->radeon); /* XXX others? BE/LE? */ switch (mesa_format) { case MESA_FORMAT_ARGB8888: case MESA_FORMAT_XRGB8888: dst_format = RADEON_COLOR_FORMAT_ARGB8888; break; case MESA_FORMAT_RGB565: dst_format = RADEON_COLOR_FORMAT_RGB565; break; case MESA_FORMAT_ARGB4444: dst_format = RADEON_COLOR_FORMAT_ARGB4444; break; case MESA_FORMAT_ARGB1555: dst_format = RADEON_COLOR_FORMAT_ARGB1555; break; case MESA_FORMAT_A8: dst_format = RADEON_COLOR_FORMAT_RGB8; break; default: break; } BEGIN_BATCH_NO_AUTOSTATE(18); OUT_BATCH_REGVAL(RADEON_RE_TOP_LEFT, 0); OUT_BATCH_REGVAL(RADEON_RE_WIDTH_HEIGHT, ((width << RADEON_RE_WIDTH_SHIFT) | (height << RADEON_RE_HEIGHT_SHIFT))); OUT_BATCH_REGVAL(RADEON_RB3D_PLANEMASK, 0xffffffff); OUT_BATCH_REGVAL(RADEON_RB3D_BLENDCNTL, RADEON_SRC_BLEND_GL_ONE | RADEON_DST_BLEND_GL_ZERO); OUT_BATCH_REGVAL(RADEON_RB3D_CNTL, dst_format); OUT_BATCH_REGSEQ(RADEON_RB3D_COLOROFFSET, 1); OUT_BATCH_RELOC(0, bo, 0, 0, RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0); OUT_BATCH_REGSEQ(RADEON_RB3D_COLORPITCH, 1); OUT_BATCH_RELOC(dst_pitch, bo, dst_pitch, 0, RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0); END_BATCH(); }
static void cube_emit(GLcontext *ctx, struct radeon_state_atom *atom) { r100ContextPtr r100 = R100_CONTEXT(ctx); BATCH_LOCALS(&r100->radeon); uint32_t dwords = atom->check(ctx, atom); int i = atom->idx, j; radeonTexObj *t = r100->state.texture.unit[i].texobj; radeon_mipmap_level *lvl; if (!(ctx->Texture.Unit[i]._ReallyEnabled & TEXTURE_CUBE_BIT)) return; if (!t) return; if (!t->mt) return; BEGIN_BATCH_NO_AUTOSTATE(dwords); OUT_BATCH_TABLE(atom->cmd, 3); lvl = &t->mt->levels[0]; for (j = 0; j < 5; j++) { OUT_BATCH_RELOC(lvl->faces[j].offset, t->mt->bo, lvl->faces[j].offset, RADEON_GEM_DOMAIN_VRAM, 0, 0); } END_BATCH(); }
static void cube_emit_cs(struct gl_context *ctx, struct radeon_state_atom *atom) { r100ContextPtr r100 = R100_CONTEXT(ctx); BATCH_LOCALS(&r100->radeon); uint32_t dwords = atom->check(ctx, atom); int i = atom->idx, j; radeonTexObj *t = r100->state.texture.unit[i].texobj; radeon_mipmap_level *lvl; uint32_t base_reg; if (!(ctx->Texture.Unit[i]._ReallyEnabled & TEXTURE_CUBE_BIT)) return; if (!t) return; if (!t->mt) return; switch(i) { case 1: base_reg = RADEON_PP_CUBIC_OFFSET_T1_0; break; case 2: base_reg = RADEON_PP_CUBIC_OFFSET_T2_0; break; default: case 0: base_reg = RADEON_PP_CUBIC_OFFSET_T0_0; break; }; BEGIN_BATCH_NO_AUTOSTATE(dwords); OUT_BATCH_TABLE(atom->cmd, 2); lvl = &t->mt->levels[0]; for (j = 0; j < 5; j++) { OUT_BATCH(CP_PACKET0(base_reg + (4 * j), 0)); OUT_BATCH_RELOC(lvl->faces[j].offset, t->mt->bo, lvl->faces[j].offset, RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, 0); } END_BATCH(); }
static void r200FireEB(r200ContextPtr rmesa, int vertex_count, int type) { BATCH_LOCALS(&rmesa->radeon); if (vertex_count > 0) { BEGIN_BATCH(8+2); OUT_BATCH_PACKET3_CLIP(R200_CP_CMD_3D_DRAW_INDX_2, 0); OUT_BATCH(R200_VF_PRIM_WALK_IND | R200_VF_COLOR_ORDER_RGBA | ((vertex_count + 0) << 16) | type); if (!rmesa->radeon.radeonScreen->kernel_mm) { OUT_BATCH_PACKET3(R200_CP_CMD_INDX_BUFFER, 2); OUT_BATCH((0x80 << 24) | (0 << 16) | 0x810); OUT_BATCH_RELOC(rmesa->radeon.tcl.elt_dma_offset, rmesa->radeon.tcl.elt_dma_bo, rmesa->radeon.tcl.elt_dma_offset, RADEON_GEM_DOMAIN_GTT, 0, 0); OUT_BATCH((vertex_count + 1)/2); } else { OUT_BATCH_PACKET3(R200_CP_CMD_INDX_BUFFER, 2); OUT_BATCH((0x80 << 24) | (0 << 16) | 0x810); OUT_BATCH(rmesa->radeon.tcl.elt_dma_offset); OUT_BATCH((vertex_count + 1)/2); radeon_cs_write_reloc(rmesa->radeon.cmdbuf.cs, rmesa->radeon.tcl.elt_dma_bo, RADEON_GEM_DOMAIN_GTT, 0, 0); } END_BATCH(); } }
static void r100_emit_query_finish(radeonContextPtr radeon) { BATCH_LOCALS(radeon); struct radeon_query_object *query = radeon->query.current; BEGIN_BATCH_NO_AUTOSTATE(4); OUT_BATCH(CP_PACKET0(RADEON_RB3D_ZPASS_ADDR, 0)); OUT_BATCH_RELOC(0, query->bo, query->curr_offset, 0, RADEON_GEM_DOMAIN_GTT, 0); END_BATCH(); query->curr_offset += sizeof(uint32_t); assert(query->curr_offset < RADEON_QUERY_PAGE_SIZE); query->emitted_begin = GL_FALSE; }
/* Fire a section of the retained (indexed_verts) buffer as a regular * primtive. */ extern void radeonEmitVbufPrim( r100ContextPtr rmesa, GLuint vertex_format, GLuint primitive, GLuint vertex_nr ) { BATCH_LOCALS(&rmesa->radeon); assert(!(primitive & RADEON_CP_VC_CNTL_PRIM_WALK_IND)); radeonEmitState(&rmesa->radeon); radeonEmitScissor(rmesa); #if RADEON_OLD_PACKETS BEGIN_BATCH(8); OUT_BATCH_PACKET3_CLIP(RADEON_CP_PACKET3_3D_RNDR_GEN_INDX_PRIM, 3); if (!rmesa->radeon.radeonScreen->kernel_mm) { OUT_BATCH_RELOC(rmesa->ioctl.vertex_offset, rmesa->ioctl.bo, rmesa->ioctl.vertex_offset, RADEON_GEM_DOMAIN_GTT, 0, 0); } else { OUT_BATCH(rmesa->ioctl.vertex_offset); } OUT_BATCH(vertex_nr); OUT_BATCH(vertex_format); OUT_BATCH(primitive | RADEON_CP_VC_CNTL_PRIM_WALK_LIST | RADEON_CP_VC_CNTL_COLOR_ORDER_RGBA | RADEON_CP_VC_CNTL_VTX_FMT_RADEON_MODE | (vertex_nr << RADEON_CP_VC_CNTL_NUM_SHIFT)); if (rmesa->radeon.radeonScreen->kernel_mm) { radeon_cs_write_reloc(rmesa->radeon.cmdbuf.cs, rmesa->ioctl.bo, RADEON_GEM_DOMAIN_GTT, 0, 0); } END_BATCH(); #else BEGIN_BATCH(4); OUT_BATCH_PACKET3_CLIP(RADEON_CP_PACKET3_3D_DRAW_VBUF, 1); OUT_BATCH(vertex_format); OUT_BATCH(primitive | RADEON_CP_VC_CNTL_PRIM_WALK_LIST | RADEON_CP_VC_CNTL_COLOR_ORDER_RGBA | RADEON_CP_VC_CNTL_MAOS_ENABLE | RADEON_CP_VC_CNTL_VTX_FMT_RADEON_MODE | (vertex_nr << RADEON_CP_VC_CNTL_NUM_SHIFT)); END_BATCH(); #endif }
static void r300EmitVertexAOS(r300ContextPtr rmesa, GLuint vertex_size, struct radeon_bo *bo, GLuint offset) { BATCH_LOCALS(&rmesa->radeon); radeon_print(RADEON_SWRENDER, RADEON_TRACE, "%s: vertex_size %d, offset 0x%x \n", __FUNCTION__, vertex_size, offset); BEGIN_BATCH(7); OUT_BATCH_PACKET3(R300_PACKET3_3D_LOAD_VBPNTR, 2); OUT_BATCH(1); OUT_BATCH(vertex_size | (vertex_size << 8)); OUT_BATCH_RELOC(offset, bo, offset, RADEON_GEM_DOMAIN_GTT, 0, 0); END_BATCH(); }
void radeonEmitVertexAOS( r100ContextPtr rmesa, GLuint vertex_size, struct radeon_bo *bo, GLuint offset ) { #if RADEON_OLD_PACKETS rmesa->ioctl.vertex_offset = offset; rmesa->ioctl.bo = bo; #else BATCH_LOCALS(&rmesa->radeon); if (RADEON_DEBUG & (RADEON_PRIMS|DEBUG_IOCTL)) fprintf(stderr, "%s: vertex_size 0x%x offset 0x%x \n", __FUNCTION__, vertex_size, offset); BEGIN_BATCH(7); OUT_BATCH_PACKET3(RADEON_CP_PACKET3_3D_LOAD_VBPNTR, 2); OUT_BATCH(1); OUT_BATCH(vertex_size | (vertex_size << 8)); OUT_BATCH_RELOC(offset, bo, offset, RADEON_GEM_DOMAIN_GTT, 0, 0); END_BATCH(); #endif }
void radeonEmitAOS( r100ContextPtr rmesa, GLuint nr, GLuint offset ) { #if RADEON_OLD_PACKETS assert( nr == 1 ); rmesa->ioctl.bo = rmesa->radeon.tcl.aos[0].bo; rmesa->ioctl.vertex_offset = (rmesa->radeon.tcl.aos[0].offset + offset * rmesa->radeon.tcl.aos[0].stride * 4); rmesa->ioctl.vertex_max = rmesa->radeon.tcl.aos[0].count; #else BATCH_LOCALS(&rmesa->radeon); uint32_t voffset; // int sz = AOS_BUFSZ(nr); int sz = 1 + (nr >> 1) * 3 + (nr & 1) * 2; int i; if (RADEON_DEBUG & RADEON_IOCTL) fprintf(stderr, "%s\n", __FUNCTION__); BEGIN_BATCH(sz+2+(nr * 2)); OUT_BATCH_PACKET3(RADEON_CP_PACKET3_3D_LOAD_VBPNTR, sz - 1); OUT_BATCH(nr); if (!rmesa->radeon.radeonScreen->kernel_mm) { for (i = 0; i + 1 < nr; i += 2) { OUT_BATCH((rmesa->radeon.tcl.aos[i].components << 0) | (rmesa->radeon.tcl.aos[i].stride << 8) | (rmesa->radeon.tcl.aos[i + 1].components << 16) | (rmesa->radeon.tcl.aos[i + 1].stride << 24)); voffset = rmesa->radeon.tcl.aos[i + 0].offset + offset * 4 * rmesa->radeon.tcl.aos[i + 0].stride; OUT_BATCH_RELOC(voffset, rmesa->radeon.tcl.aos[i].bo, voffset, RADEON_GEM_DOMAIN_GTT, 0, 0); voffset = rmesa->radeon.tcl.aos[i + 1].offset + offset * 4 * rmesa->radeon.tcl.aos[i + 1].stride; OUT_BATCH_RELOC(voffset, rmesa->radeon.tcl.aos[i+1].bo, voffset, RADEON_GEM_DOMAIN_GTT, 0, 0); } if (nr & 1) { OUT_BATCH((rmesa->radeon.tcl.aos[nr - 1].components << 0) | (rmesa->radeon.tcl.aos[nr - 1].stride << 8)); voffset = rmesa->radeon.tcl.aos[nr - 1].offset + offset * 4 * rmesa->radeon.tcl.aos[nr - 1].stride; OUT_BATCH_RELOC(voffset, rmesa->radeon.tcl.aos[nr - 1].bo, voffset, RADEON_GEM_DOMAIN_GTT, 0, 0); } } else { for (i = 0; i + 1 < nr; i += 2) { OUT_BATCH((rmesa->radeon.tcl.aos[i].components << 0) | (rmesa->radeon.tcl.aos[i].stride << 8) | (rmesa->radeon.tcl.aos[i + 1].components << 16) | (rmesa->radeon.tcl.aos[i + 1].stride << 24)); voffset = rmesa->radeon.tcl.aos[i + 0].offset + offset * 4 * rmesa->radeon.tcl.aos[i + 0].stride; OUT_BATCH(voffset); voffset = rmesa->radeon.tcl.aos[i + 1].offset + offset * 4 * rmesa->radeon.tcl.aos[i + 1].stride; OUT_BATCH(voffset); } if (nr & 1) { OUT_BATCH((rmesa->radeon.tcl.aos[nr - 1].components << 0) | (rmesa->radeon.tcl.aos[nr - 1].stride << 8)); voffset = rmesa->radeon.tcl.aos[nr - 1].offset + offset * 4 * rmesa->radeon.tcl.aos[nr - 1].stride; OUT_BATCH(voffset); } for (i = 0; i + 1 < nr; i += 2) { voffset = rmesa->radeon.tcl.aos[i + 0].offset + offset * 4 * rmesa->radeon.tcl.aos[i + 0].stride; radeon_cs_write_reloc(rmesa->radeon.cmdbuf.cs, rmesa->radeon.tcl.aos[i+0].bo, RADEON_GEM_DOMAIN_GTT, 0, 0); voffset = rmesa->radeon.tcl.aos[i + 1].offset + offset * 4 * rmesa->radeon.tcl.aos[i + 1].stride; radeon_cs_write_reloc(rmesa->radeon.cmdbuf.cs, rmesa->radeon.tcl.aos[i+1].bo, RADEON_GEM_DOMAIN_GTT, 0, 0); } if (nr & 1) { voffset = rmesa->radeon.tcl.aos[nr - 1].offset + offset * 4 * rmesa->radeon.tcl.aos[nr - 1].stride; radeon_cs_write_reloc(rmesa->radeon.cmdbuf.cs, rmesa->radeon.tcl.aos[nr-1].bo, RADEON_GEM_DOMAIN_GTT, 0, 0); } } END_BATCH(); #endif }
GLushort *radeonAllocEltsOpenEnded( r100ContextPtr rmesa, GLuint vertex_format, GLuint primitive, GLuint min_nr ) { GLushort *retval; int align_min_nr; BATCH_LOCALS(&rmesa->radeon); if (RADEON_DEBUG & RADEON_IOCTL) fprintf(stderr, "%s %d prim %x\n", __FUNCTION__, min_nr, primitive); assert((primitive & RADEON_CP_VC_CNTL_PRIM_WALK_IND)); radeonEmitState(&rmesa->radeon); radeonEmitScissor(rmesa); rmesa->tcl.elt_cmd_start = rmesa->radeon.cmdbuf.cs->cdw; /* round up min_nr to align the state */ align_min_nr = (min_nr + 1) & ~1; #if RADEON_OLD_PACKETS BEGIN_BATCH_NO_AUTOSTATE(2+ELTS_BUFSZ(align_min_nr)/4); OUT_BATCH_PACKET3_CLIP(RADEON_CP_PACKET3_3D_RNDR_GEN_INDX_PRIM, 0); if (!rmesa->radeon.radeonScreen->kernel_mm) { OUT_BATCH_RELOC(rmesa->ioctl.vertex_offset, rmesa->ioctl.bo, rmesa->ioctl.vertex_offset, RADEON_GEM_DOMAIN_GTT, 0, 0); } else { OUT_BATCH(rmesa->ioctl.vertex_offset); } OUT_BATCH(rmesa->ioctl.vertex_max); OUT_BATCH(vertex_format); OUT_BATCH(primitive | RADEON_CP_VC_CNTL_PRIM_WALK_IND | RADEON_CP_VC_CNTL_COLOR_ORDER_RGBA | RADEON_CP_VC_CNTL_VTX_FMT_RADEON_MODE); #else BEGIN_BATCH_NO_AUTOSTATE(ELTS_BUFSZ(align_min_nr)/4); OUT_BATCH_PACKET3_CLIP(RADEON_CP_PACKET3_DRAW_INDX, 0); OUT_BATCH(vertex_format); OUT_BATCH(primitive | RADEON_CP_VC_CNTL_PRIM_WALK_IND | RADEON_CP_VC_CNTL_COLOR_ORDER_RGBA | RADEON_CP_VC_CNTL_MAOS_ENABLE | RADEON_CP_VC_CNTL_VTX_FMT_RADEON_MODE); #endif rmesa->tcl.elt_cmd_offset = rmesa->radeon.cmdbuf.cs->cdw; rmesa->tcl.elt_used = min_nr; retval = (GLushort *)(rmesa->radeon.cmdbuf.cs->packets + rmesa->tcl.elt_cmd_offset); if (RADEON_DEBUG & RADEON_RENDER) fprintf(stderr, "%s: header prim %x \n", __FUNCTION__, primitive); assert(!rmesa->radeon.dma.flush); rmesa->radeon.glCtx->Driver.NeedFlush |= FLUSH_STORED_VERTICES; rmesa->radeon.dma.flush = radeonFlushElts; return retval; }
static void inline emit_tx_setup(struct r200_context *r200, gl_format src_mesa_format, gl_format dst_mesa_format, struct radeon_bo *bo, intptr_t offset, unsigned width, unsigned height, unsigned pitch) { uint32_t txformat = R200_TXFORMAT_NON_POWER2; BATCH_LOCALS(&r200->radeon); assert(width <= 2048); assert(height <= 2048); assert(offset % 32 == 0); /* XXX others? BE/LE? */ switch (src_mesa_format) { case MESA_FORMAT_ARGB8888: txformat |= R200_TXFORMAT_ARGB8888 | R200_TXFORMAT_ALPHA_IN_MAP; break; case MESA_FORMAT_RGBA8888: txformat |= R200_TXFORMAT_RGBA8888 | R200_TXFORMAT_ALPHA_IN_MAP; break; case MESA_FORMAT_RGBA8888_REV: txformat |= R200_TXFORMAT_ABGR8888 | R200_TXFORMAT_ALPHA_IN_MAP; break; case MESA_FORMAT_XRGB8888: txformat |= R200_TXFORMAT_ARGB8888; break; case MESA_FORMAT_RGB565: txformat |= R200_TXFORMAT_RGB565; break; case MESA_FORMAT_ARGB4444: txformat |= R200_TXFORMAT_ARGB4444 | R200_TXFORMAT_ALPHA_IN_MAP; break; case MESA_FORMAT_ARGB1555: txformat |= R200_TXFORMAT_ARGB1555 | R200_TXFORMAT_ALPHA_IN_MAP; break; case MESA_FORMAT_A8: case MESA_FORMAT_I8: txformat |= R200_TXFORMAT_I8 | R200_TXFORMAT_ALPHA_IN_MAP; break; case MESA_FORMAT_L8: txformat |= R200_TXFORMAT_I8; break; case MESA_FORMAT_AL88: txformat |= R200_TXFORMAT_AI88 | R200_TXFORMAT_ALPHA_IN_MAP; break; default: break; } if (bo->flags & RADEON_BO_FLAGS_MACRO_TILE) offset |= R200_TXO_MACRO_TILE; if (bo->flags & RADEON_BO_FLAGS_MICRO_TILE) offset |= R200_TXO_MICRO_TILE; switch (dst_mesa_format) { case MESA_FORMAT_ARGB8888: case MESA_FORMAT_XRGB8888: case MESA_FORMAT_RGB565: case MESA_FORMAT_ARGB4444: case MESA_FORMAT_ARGB1555: case MESA_FORMAT_A8: case MESA_FORMAT_L8: case MESA_FORMAT_I8: default: /* no swizzle required */ BEGIN_BATCH(10); OUT_BATCH_REGVAL(RADEON_PP_CNTL, (RADEON_TEX_0_ENABLE | RADEON_TEX_BLEND_0_ENABLE)); OUT_BATCH_REGVAL(R200_PP_TXCBLEND_0, (R200_TXC_ARG_A_ZERO | R200_TXC_ARG_B_ZERO | R200_TXC_ARG_C_R0_COLOR | R200_TXC_OP_MADD)); OUT_BATCH_REGVAL(R200_PP_TXCBLEND2_0, (R200_TXC_CLAMP_0_1 | R200_TXC_OUTPUT_REG_R0)); OUT_BATCH_REGVAL(R200_PP_TXABLEND_0, (R200_TXA_ARG_A_ZERO | R200_TXA_ARG_B_ZERO | R200_TXA_ARG_C_R0_ALPHA | R200_TXA_OP_MADD)); OUT_BATCH_REGVAL(R200_PP_TXABLEND2_0, (R200_TXA_CLAMP_0_1 | R200_TXA_OUTPUT_REG_R0)); END_BATCH(); break; case MESA_FORMAT_RGBA8888: BEGIN_BATCH(10); OUT_BATCH_REGVAL(RADEON_PP_CNTL, (RADEON_TEX_0_ENABLE | RADEON_TEX_BLEND_0_ENABLE)); OUT_BATCH_REGVAL(R200_PP_TXCBLEND_0, (R200_TXC_ARG_A_ZERO | R200_TXC_ARG_B_ZERO | R200_TXC_ARG_C_R0_COLOR | R200_TXC_OP_MADD)); OUT_BATCH_REGVAL(R200_PP_TXCBLEND2_0, (R200_TXC_CLAMP_0_1 | R200_TXC_OUTPUT_ROTATE_GBA | R200_TXC_OUTPUT_REG_R0)); OUT_BATCH_REGVAL(R200_PP_TXABLEND_0, (R200_TXA_ARG_A_ZERO | R200_TXA_ARG_B_ZERO | R200_TXA_ARG_C_R0_ALPHA | R200_TXA_OP_MADD)); OUT_BATCH_REGVAL(R200_PP_TXABLEND2_0, (R200_TXA_CLAMP_0_1 | (R200_TXA_REPL_RED << R200_TXA_REPL_ARG_C_SHIFT) | R200_TXA_OUTPUT_REG_R0)); END_BATCH(); break; case MESA_FORMAT_RGBA8888_REV: BEGIN_BATCH(34); OUT_BATCH_REGVAL(RADEON_PP_CNTL, (RADEON_TEX_0_ENABLE | RADEON_TEX_BLEND_0_ENABLE | RADEON_TEX_BLEND_1_ENABLE | RADEON_TEX_BLEND_2_ENABLE | RADEON_TEX_BLEND_3_ENABLE)); /* r1.r = r0.b */ OUT_BATCH_REGVAL(R200_PP_TXCBLEND_0, (R200_TXC_ARG_A_ZERO | R200_TXC_ARG_B_ZERO | R200_TXC_ARG_C_R0_COLOR | R200_TXC_OP_MADD)); OUT_BATCH_REGVAL(R200_PP_TXCBLEND2_0, (R200_TXC_CLAMP_0_1 | R200_TXC_OUTPUT_MASK_R | (R200_TXC_REPL_BLUE << R200_TXC_REPL_ARG_C_SHIFT) | R200_TXC_OUTPUT_REG_R1)); /* r1.a = r0.a */ OUT_BATCH_REGVAL(R200_PP_TXABLEND_0, (R200_TXA_ARG_A_ZERO | R200_TXA_ARG_B_ZERO | R200_TXA_ARG_C_R0_ALPHA | R200_TXA_OP_MADD)); OUT_BATCH_REGVAL(R200_PP_TXABLEND2_0, (R200_TXA_CLAMP_0_1 | R200_TXA_OUTPUT_REG_R1)); /* r1.g = r0.g */ OUT_BATCH_REGVAL(R200_PP_TXCBLEND_1, (R200_TXC_ARG_A_ZERO | R200_TXC_ARG_B_ZERO | R200_TXC_ARG_C_R0_COLOR | R200_TXC_OP_MADD)); OUT_BATCH_REGVAL(R200_PP_TXCBLEND2_1, (R200_TXC_CLAMP_0_1 | R200_TXC_OUTPUT_MASK_G | (R200_TXC_REPL_GREEN << R200_TXC_REPL_ARG_C_SHIFT) | R200_TXC_OUTPUT_REG_R1)); /* r1.a = r0.a */ OUT_BATCH_REGVAL(R200_PP_TXABLEND_1, (R200_TXA_ARG_A_ZERO | R200_TXA_ARG_B_ZERO | R200_TXA_ARG_C_R0_ALPHA | R200_TXA_OP_MADD)); OUT_BATCH_REGVAL(R200_PP_TXABLEND2_1, (R200_TXA_CLAMP_0_1 | R200_TXA_OUTPUT_REG_R1)); /* r1.b = r0.r */ OUT_BATCH_REGVAL(R200_PP_TXCBLEND_2, (R200_TXC_ARG_A_ZERO | R200_TXC_ARG_B_ZERO | R200_TXC_ARG_C_R0_COLOR | R200_TXC_OP_MADD)); OUT_BATCH_REGVAL(R200_PP_TXCBLEND2_2, (R200_TXC_CLAMP_0_1 | R200_TXC_OUTPUT_MASK_B | (R200_TXC_REPL_RED << R200_TXC_REPL_ARG_C_SHIFT) | R200_TXC_OUTPUT_REG_R1)); /* r1.a = r0.a */ OUT_BATCH_REGVAL(R200_PP_TXABLEND_2, (R200_TXA_ARG_A_ZERO | R200_TXA_ARG_B_ZERO | R200_TXA_ARG_C_R0_ALPHA | R200_TXA_OP_MADD)); OUT_BATCH_REGVAL(R200_PP_TXABLEND2_2, (R200_TXA_CLAMP_0_1 | R200_TXA_OUTPUT_REG_R1)); /* r0.rgb = r1.rgb */ OUT_BATCH_REGVAL(R200_PP_TXCBLEND_3, (R200_TXC_ARG_A_ZERO | R200_TXC_ARG_B_ZERO | R200_TXC_ARG_C_R1_COLOR | R200_TXC_OP_MADD)); OUT_BATCH_REGVAL(R200_PP_TXCBLEND2_3, (R200_TXC_CLAMP_0_1 | R200_TXC_OUTPUT_REG_R0)); /* r0.a = r1.a */ OUT_BATCH_REGVAL(R200_PP_TXABLEND_3, (R200_TXA_ARG_A_ZERO | R200_TXA_ARG_B_ZERO | R200_TXA_ARG_C_R1_ALPHA | R200_TXA_OP_MADD)); OUT_BATCH_REGVAL(R200_PP_TXABLEND2_3, (R200_TXA_CLAMP_0_1 | R200_TXA_OUTPUT_REG_R0)); END_BATCH(); break; } BEGIN_BATCH(18); OUT_BATCH_REGVAL(R200_PP_CNTL_X, 0); OUT_BATCH_REGVAL(R200_PP_TXMULTI_CTL_0, 0); OUT_BATCH_REGVAL(R200_PP_TXFILTER_0, (R200_CLAMP_S_CLAMP_LAST | R200_CLAMP_T_CLAMP_LAST | R200_MAG_FILTER_NEAREST | R200_MIN_FILTER_NEAREST)); OUT_BATCH_REGVAL(R200_PP_TXFORMAT_0, txformat); OUT_BATCH_REGVAL(R200_PP_TXFORMAT_X_0, 0); OUT_BATCH_REGVAL(R200_PP_TXSIZE_0, ((width - 1) | ((height - 1) << RADEON_TEX_VSIZE_SHIFT))); OUT_BATCH_REGVAL(R200_PP_TXPITCH_0, pitch * _mesa_get_format_bytes(src_mesa_format) - 32); OUT_BATCH_REGSEQ(R200_PP_TXOFFSET_0, 1); OUT_BATCH_RELOC(offset, bo, offset, RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, 0); END_BATCH(); }
static void inline emit_tx_setup(struct r100_context *r100, gl_format mesa_format, struct radeon_bo *bo, intptr_t offset, unsigned width, unsigned height, unsigned pitch) { uint32_t txformat = RADEON_TXFORMAT_NON_POWER2; BATCH_LOCALS(&r100->radeon); assert(width <= 2048); assert(height <= 2048); assert(offset % 32 == 0); /* XXX others? BE/LE? */ switch (mesa_format) { case MESA_FORMAT_ARGB8888: txformat |= RADEON_TXFORMAT_ARGB8888 | RADEON_TXFORMAT_ALPHA_IN_MAP; break; case MESA_FORMAT_RGBA8888: txformat |= RADEON_TXFORMAT_RGBA8888 | RADEON_TXFORMAT_ALPHA_IN_MAP; break; case MESA_FORMAT_XRGB8888: txformat |= RADEON_TXFORMAT_ARGB8888; break; case MESA_FORMAT_RGB565: txformat |= RADEON_TXFORMAT_RGB565; break; case MESA_FORMAT_ARGB4444: txformat |= RADEON_TXFORMAT_ARGB4444 | RADEON_TXFORMAT_ALPHA_IN_MAP; break; case MESA_FORMAT_ARGB1555: txformat |= RADEON_TXFORMAT_ARGB1555 | RADEON_TXFORMAT_ALPHA_IN_MAP; break; case MESA_FORMAT_A8: case MESA_FORMAT_I8: txformat |= RADEON_TXFORMAT_I8 | RADEON_TXFORMAT_ALPHA_IN_MAP; break; case MESA_FORMAT_L8: txformat |= RADEON_TXFORMAT_I8; break; case MESA_FORMAT_AL88: txformat |= RADEON_TXFORMAT_AI88 | RADEON_TXFORMAT_ALPHA_IN_MAP; break; default: break; } if (bo->flags & RADEON_BO_FLAGS_MACRO_TILE) offset |= RADEON_TXO_MACRO_TILE; if (bo->flags & RADEON_BO_FLAGS_MICRO_TILE) offset |= RADEON_TXO_MICRO_TILE_X2; BEGIN_BATCH(18); OUT_BATCH_REGVAL(RADEON_PP_CNTL, RADEON_TEX_0_ENABLE | RADEON_TEX_BLEND_0_ENABLE); OUT_BATCH_REGVAL(RADEON_PP_TXCBLEND_0, (RADEON_COLOR_ARG_A_ZERO | RADEON_COLOR_ARG_B_ZERO | RADEON_COLOR_ARG_C_T0_COLOR | RADEON_BLEND_CTL_ADD | RADEON_CLAMP_TX)); OUT_BATCH_REGVAL(RADEON_PP_TXABLEND_0, (RADEON_ALPHA_ARG_A_ZERO | RADEON_ALPHA_ARG_B_ZERO | RADEON_ALPHA_ARG_C_T0_ALPHA | RADEON_BLEND_CTL_ADD | RADEON_CLAMP_TX)); OUT_BATCH_REGVAL(RADEON_PP_TXFILTER_0, (RADEON_CLAMP_S_CLAMP_LAST | RADEON_CLAMP_T_CLAMP_LAST | RADEON_MAG_FILTER_NEAREST | RADEON_MIN_FILTER_NEAREST)); OUT_BATCH_REGVAL(RADEON_PP_TXFORMAT_0, txformat); OUT_BATCH_REGVAL(RADEON_PP_TEX_SIZE_0, ((width - 1) | ((height - 1) << RADEON_TEX_VSIZE_SHIFT))); OUT_BATCH_REGVAL(RADEON_PP_TEX_PITCH_0, pitch * _mesa_get_format_bytes(mesa_format) - 32); OUT_BATCH_REGSEQ(RADEON_PP_TXOFFSET_0, 1); OUT_BATCH_RELOC(offset, bo, offset, RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, 0); END_BATCH(); }
static void ctx_emit(GLcontext *ctx, struct radeon_state_atom *atom) { r100ContextPtr r100 = R100_CONTEXT(ctx); BATCH_LOCALS(&r100->radeon); struct radeon_renderbuffer *rrb; uint32_t cbpitch; uint32_t zbpitch, depth_fmt; uint32_t dwords = atom->check(ctx, atom); /* output the first 7 bytes of context */ BEGIN_BATCH_NO_AUTOSTATE(dwords); OUT_BATCH_TABLE(atom->cmd, 5); rrb = radeon_get_depthbuffer(&r100->radeon); if (!rrb) { OUT_BATCH(0); OUT_BATCH(0); } else { zbpitch = (rrb->pitch / rrb->cpp); if (r100->using_hyperz) zbpitch |= RADEON_DEPTH_HYPERZ; OUT_BATCH_RELOC(0, rrb->bo, 0, 0, RADEON_GEM_DOMAIN_VRAM, 0); OUT_BATCH(zbpitch); if (rrb->cpp == 4) depth_fmt = RADEON_DEPTH_FORMAT_24BIT_INT_Z; else depth_fmt = RADEON_DEPTH_FORMAT_16BIT_INT_Z; atom->cmd[CTX_RB3D_ZSTENCILCNTL] &= ~RADEON_DEPTH_FORMAT_MASK; atom->cmd[CTX_RB3D_ZSTENCILCNTL] |= depth_fmt; } OUT_BATCH(atom->cmd[CTX_RB3D_ZSTENCILCNTL]); OUT_BATCH(atom->cmd[CTX_CMD_1]); OUT_BATCH(atom->cmd[CTX_PP_CNTL]); rrb = radeon_get_colorbuffer(&r100->radeon); if (!rrb || !rrb->bo) { OUT_BATCH(atom->cmd[CTX_RB3D_CNTL]); OUT_BATCH(atom->cmd[CTX_RB3D_COLOROFFSET]); } else { atom->cmd[CTX_RB3D_CNTL] &= ~(0xf << 10); if (rrb->cpp == 4) atom->cmd[CTX_RB3D_CNTL] |= RADEON_COLOR_FORMAT_ARGB8888; else atom->cmd[CTX_RB3D_CNTL] |= RADEON_COLOR_FORMAT_RGB565; OUT_BATCH(atom->cmd[CTX_RB3D_CNTL]); OUT_BATCH_RELOC(0, rrb->bo, 0, 0, RADEON_GEM_DOMAIN_VRAM, 0); } OUT_BATCH(atom->cmd[CTX_CMD_2]); if (!rrb || !rrb->bo) { OUT_BATCH(atom->cmd[CTX_RB3D_COLORPITCH]); } else { cbpitch = (rrb->pitch / rrb->cpp); if (rrb->bo->flags & RADEON_BO_FLAGS_MACRO_TILE) cbpitch |= RADEON_COLOR_TILE_ENABLE; OUT_BATCH(cbpitch); } END_BATCH(); }
void r200EmitAOS(r200ContextPtr rmesa, GLuint nr, GLuint offset) { BATCH_LOCALS(&rmesa->radeon); uint32_t voffset; int sz = 1 + (nr >> 1) * 3 + (nr & 1) * 2; int i; radeon_print(RADEON_RENDER, RADEON_VERBOSE, "%s: nr=%d, ofs=0x%08x\n", __FUNCTION__, nr, offset); BEGIN_BATCH(sz+2+ (nr*2)); OUT_BATCH_PACKET3(R200_CP_CMD_3D_LOAD_VBPNTR, sz - 1); OUT_BATCH(nr); if (!rmesa->radeon.radeonScreen->kernel_mm) { for (i = 0; i + 1 < nr; i += 2) { OUT_BATCH((rmesa->radeon.tcl.aos[i].components << 0) | (rmesa->radeon.tcl.aos[i].stride << 8) | (rmesa->radeon.tcl.aos[i + 1].components << 16) | (rmesa->radeon.tcl.aos[i + 1].stride << 24)); voffset = rmesa->radeon.tcl.aos[i + 0].offset + offset * 4 * rmesa->radeon.tcl.aos[i + 0].stride; OUT_BATCH_RELOC(voffset, rmesa->radeon.tcl.aos[i].bo, voffset, RADEON_GEM_DOMAIN_GTT, 0, 0); voffset = rmesa->radeon.tcl.aos[i + 1].offset + offset * 4 * rmesa->radeon.tcl.aos[i + 1].stride; OUT_BATCH_RELOC(voffset, rmesa->radeon.tcl.aos[i+1].bo, voffset, RADEON_GEM_DOMAIN_GTT, 0, 0); } if (nr & 1) { OUT_BATCH((rmesa->radeon.tcl.aos[nr - 1].components << 0) | (rmesa->radeon.tcl.aos[nr - 1].stride << 8)); voffset = rmesa->radeon.tcl.aos[nr - 1].offset + offset * 4 * rmesa->radeon.tcl.aos[nr - 1].stride; OUT_BATCH_RELOC(voffset, rmesa->radeon.tcl.aos[nr - 1].bo, voffset, RADEON_GEM_DOMAIN_GTT, 0, 0); } } else { for (i = 0; i + 1 < nr; i += 2) { OUT_BATCH((rmesa->radeon.tcl.aos[i].components << 0) | (rmesa->radeon.tcl.aos[i].stride << 8) | (rmesa->radeon.tcl.aos[i + 1].components << 16) | (rmesa->radeon.tcl.aos[i + 1].stride << 24)); voffset = rmesa->radeon.tcl.aos[i + 0].offset + offset * 4 * rmesa->radeon.tcl.aos[i + 0].stride; OUT_BATCH(voffset); voffset = rmesa->radeon.tcl.aos[i + 1].offset + offset * 4 * rmesa->radeon.tcl.aos[i + 1].stride; OUT_BATCH(voffset); } if (nr & 1) { OUT_BATCH((rmesa->radeon.tcl.aos[nr - 1].components << 0) | (rmesa->radeon.tcl.aos[nr - 1].stride << 8)); voffset = rmesa->radeon.tcl.aos[nr - 1].offset + offset * 4 * rmesa->radeon.tcl.aos[nr - 1].stride; OUT_BATCH(voffset); } for (i = 0; i + 1 < nr; i += 2) { voffset = rmesa->radeon.tcl.aos[i + 0].offset + offset * 4 * rmesa->radeon.tcl.aos[i + 0].stride; radeon_cs_write_reloc(rmesa->radeon.cmdbuf.cs, rmesa->radeon.tcl.aos[i+0].bo, RADEON_GEM_DOMAIN_GTT, 0, 0); voffset = rmesa->radeon.tcl.aos[i + 1].offset + offset * 4 * rmesa->radeon.tcl.aos[i + 1].stride; radeon_cs_write_reloc(rmesa->radeon.cmdbuf.cs, rmesa->radeon.tcl.aos[i+1].bo, RADEON_GEM_DOMAIN_GTT, 0, 0); } if (nr & 1) { voffset = rmesa->radeon.tcl.aos[nr - 1].offset + offset * 4 * rmesa->radeon.tcl.aos[nr - 1].stride; radeon_cs_write_reloc(rmesa->radeon.cmdbuf.cs, rmesa->radeon.tcl.aos[nr-1].bo, RADEON_GEM_DOMAIN_GTT, 0, 0); } } END_BATCH(); }
static void inline emit_tx_setup(struct r200_context *r200, gl_format mesa_format, struct radeon_bo *bo, intptr_t offset, unsigned width, unsigned height, unsigned pitch) { uint32_t txformat = R200_TXFORMAT_NON_POWER2; BATCH_LOCALS(&r200->radeon); assert(width <= 2047); assert(height <= 2047); assert(offset % 32 == 0); /* XXX others? BE/LE? */ switch (mesa_format) { case MESA_FORMAT_ARGB8888: txformat |= R200_TXFORMAT_ARGB8888 | R200_TXFORMAT_ALPHA_IN_MAP; break; case MESA_FORMAT_XRGB8888: txformat |= R200_TXFORMAT_ARGB8888; break; case MESA_FORMAT_RGB565: txformat |= R200_TXFORMAT_RGB565; break; case MESA_FORMAT_ARGB4444: txformat |= R200_TXFORMAT_ARGB4444 | R200_TXFORMAT_ALPHA_IN_MAP; break; case MESA_FORMAT_ARGB1555: txformat |= R200_TXFORMAT_ARGB1555 | R200_TXFORMAT_ALPHA_IN_MAP; break; case MESA_FORMAT_A8: txformat |= R200_TXFORMAT_I8 | R200_TXFORMAT_ALPHA_IN_MAP; break; default: break; } BEGIN_BATCH(28); OUT_BATCH_REGVAL(RADEON_PP_CNTL, RADEON_TEX_0_ENABLE | RADEON_TEX_BLEND_0_ENABLE); OUT_BATCH_REGVAL(R200_PP_CNTL_X, 0); OUT_BATCH_REGVAL(R200_PP_TXMULTI_CTL_0, 0); OUT_BATCH_REGVAL(R200_PP_TXCBLEND_0, (R200_TXC_ARG_A_ZERO | R200_TXC_ARG_B_ZERO | R200_TXC_ARG_C_R0_COLOR | R200_TXC_OP_MADD)); OUT_BATCH_REGVAL(R200_PP_TXCBLEND2_0, R200_TXC_CLAMP_0_1 | R200_TXC_OUTPUT_REG_R0); OUT_BATCH_REGVAL(R200_PP_TXABLEND_0, (R200_TXA_ARG_A_ZERO | R200_TXA_ARG_B_ZERO | R200_TXA_ARG_C_R0_ALPHA | R200_TXA_OP_MADD)); OUT_BATCH_REGVAL(R200_PP_TXABLEND2_0, R200_TXA_CLAMP_0_1 | R200_TXA_OUTPUT_REG_R0); OUT_BATCH_REGVAL(R200_PP_TXFILTER_0, (R200_CLAMP_S_CLAMP_LAST | R200_CLAMP_T_CLAMP_LAST | R200_MAG_FILTER_NEAREST | R200_MIN_FILTER_NEAREST)); OUT_BATCH_REGVAL(R200_PP_TXFORMAT_0, txformat); OUT_BATCH_REGVAL(R200_PP_TXFORMAT_X_0, 0); OUT_BATCH_REGVAL(R200_PP_TXSIZE_0, ((width - 1) | ((height - 1) << RADEON_TEX_VSIZE_SHIFT))); OUT_BATCH_REGVAL(R200_PP_TXPITCH_0, pitch * _mesa_get_format_bytes(mesa_format) - 32); OUT_BATCH_REGSEQ(R200_PP_TXOFFSET_0, 1); OUT_BATCH_RELOC(0, bo, 0, RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, 0); END_BATCH(); }
static void ctx_emit_cs(struct gl_context *ctx, struct radeon_state_atom *atom) { r100ContextPtr r100 = R100_CONTEXT(ctx); BATCH_LOCALS(&r100->radeon); struct radeon_renderbuffer *rrb, *drb; uint32_t cbpitch = 0; uint32_t zbpitch = 0; uint32_t dwords = atom->check(ctx, atom); uint32_t depth_fmt; rrb = radeon_get_colorbuffer(&r100->radeon); if (!rrb || !rrb->bo) { fprintf(stderr, "no rrb\n"); return; } atom->cmd[CTX_RB3D_CNTL] &= ~(0xf << 10); if (rrb->cpp == 4) atom->cmd[CTX_RB3D_CNTL] |= RADEON_COLOR_FORMAT_ARGB8888; else switch (rrb->base.Base.Format) { case MESA_FORMAT_RGB565: atom->cmd[CTX_RB3D_CNTL] |= RADEON_COLOR_FORMAT_RGB565; break; case MESA_FORMAT_ARGB4444: atom->cmd[CTX_RB3D_CNTL] |= RADEON_COLOR_FORMAT_ARGB4444; break; case MESA_FORMAT_ARGB1555: atom->cmd[CTX_RB3D_CNTL] |= RADEON_COLOR_FORMAT_ARGB1555; break; default: _mesa_problem(ctx, "unexpected format in ctx_emit_cs()"); } cbpitch = (rrb->pitch / rrb->cpp); if (rrb->bo->flags & RADEON_BO_FLAGS_MACRO_TILE) cbpitch |= R200_COLOR_TILE_ENABLE; if (rrb->bo->flags & RADEON_BO_FLAGS_MICRO_TILE) cbpitch |= RADEON_COLOR_MICROTILE_ENABLE; drb = radeon_get_depthbuffer(&r100->radeon); if (drb) { zbpitch = (drb->pitch / drb->cpp); if (drb->cpp == 4) depth_fmt = RADEON_DEPTH_FORMAT_24BIT_INT_Z; else depth_fmt = RADEON_DEPTH_FORMAT_16BIT_INT_Z; atom->cmd[CTX_RB3D_ZSTENCILCNTL] &= ~RADEON_DEPTH_FORMAT_MASK; atom->cmd[CTX_RB3D_ZSTENCILCNTL] |= depth_fmt; } BEGIN_BATCH_NO_AUTOSTATE(dwords); /* In the CS case we need to split this up */ OUT_BATCH(CP_PACKET0(packet[0].start, 3)); OUT_BATCH_TABLE((atom->cmd + 1), 4); if (drb) { OUT_BATCH(CP_PACKET0(RADEON_RB3D_DEPTHOFFSET, 0)); OUT_BATCH_RELOC(0, drb->bo, 0, 0, RADEON_GEM_DOMAIN_VRAM, 0); OUT_BATCH(CP_PACKET0(RADEON_RB3D_DEPTHPITCH, 0)); OUT_BATCH(zbpitch); } OUT_BATCH(CP_PACKET0(RADEON_RB3D_ZSTENCILCNTL, 0)); OUT_BATCH(atom->cmd[CTX_RB3D_ZSTENCILCNTL]); OUT_BATCH(CP_PACKET0(RADEON_PP_CNTL, 1)); OUT_BATCH(atom->cmd[CTX_PP_CNTL]); OUT_BATCH(atom->cmd[CTX_RB3D_CNTL]); if (rrb) { OUT_BATCH(CP_PACKET0(RADEON_RB3D_COLOROFFSET, 0)); OUT_BATCH_RELOC(rrb->draw_offset, rrb->bo, rrb->draw_offset, 0, RADEON_GEM_DOMAIN_VRAM, 0); OUT_BATCH(CP_PACKET0(RADEON_RB3D_COLORPITCH, 0)); OUT_BATCH_RELOC(cbpitch, rrb->bo, cbpitch, 0, RADEON_GEM_DOMAIN_VRAM, 0); } // if (atom->cmd_size == CTX_STATE_SIZE_NEWDRM) { // OUT_BATCH_TABLE((atom->cmd + 14), 4); // } END_BATCH(); BEGIN_BATCH_NO_AUTOSTATE(4); OUT_BATCH(CP_PACKET0(RADEON_RE_TOP_LEFT, 0)); OUT_BATCH(0); OUT_BATCH(CP_PACKET0(RADEON_RE_WIDTH_HEIGHT, 0)); if (rrb) { OUT_BATCH(((rrb->base.Base.Width - 1) << RADEON_RE_WIDTH_SHIFT) | ((rrb->base.Base.Height - 1) << RADEON_RE_HEIGHT_SHIFT)); } else { OUT_BATCH(0); } END_BATCH(); }