int pci_init_board (void)
{
#ifdef CONFIG_ATH_EMULATION
printf("--- Skipping %s for emulation\n", __func__);
#else
uint32_t cmd;
// common for rc1 and rc2
ath_reg_wr_nf(PCIE_PLL_DITHER_DIV_MAX_ADDRESS,
PCIE_PLL_DITHER_DIV_MAX_EN_DITHER_SET(1) |
PCIE_PLL_DITHER_DIV_MAX_USE_MAX_SET(1) |
PCIE_PLL_DITHER_DIV_MAX_DIV_MAX_INT_SET(0x14) |
PCIE_PLL_DITHER_DIV_MAX_DIV_MAX_FRAC_SET(0x3ff));
ath_reg_wr_nf(PCIE_PLL_DITHER_DIV_MIN_ADDRESS,
PCIE_PLL_DITHER_DIV_MIN_DIV_MIN_INT_SET(0x14));
ath_reg_wr_nf(PCIE_PLL_CONFIG_ADDRESS,
PCIE_PLL_CONFIG_REFDIV_SET(1) |
PCIE_PLL_CONFIG_BYPASS_SET(1) |
PCIE_PLL_CONFIG_PLLPWD_SET(1));
udelay(10000);
ath_reg_rmw_clear(PCIE_PLL_CONFIG_ADDRESS, PCIE_PLL_CONFIG_PLLPWD_SET(1));
udelay(1000);
ath_reg_rmw_clear(PCIE_PLL_CONFIG_ADDRESS, PCIE_PLL_CONFIG_BYPASS_SET(1));
udelay(1000);
if (!(ath_reg_rd(RST_BOOTSTRAP_ADDRESS) & RST_BOOTSTRAP_PCIE_RC_EP_SELECT_MASK)) {
pci_rc2_init_board();
return 0;
}
ath_reg_rmw_set(RST_RESET_ADDRESS, RST_RESET_PCIE_PHY_RESET_SET(1));
udelay(10000);
ath_reg_rmw_set(RST_RESET_ADDRESS, RST_RESET_PCIE_RESET_SET(1));
udelay(10000);
ath_reg_rmw_clear(RST_MISC2_ADDRESS, RST_MISC2_PERSTN_RCPHY_SET(1));
udelay(10000);
ath_reg_wr_nf(PCIE_RESET_ADDRESS, 0); // Put endpoint in reset
udelay(100000);
ath_reg_rmw_set(RST_MISC2_ADDRESS, RST_MISC2_PERSTN_RCPHY_SET(1));
udelay(10000);
ath_reg_rmw_clear(RST_RESET_ADDRESS, RST_RESET_PCIE_PHY_RESET_SET(1));
udelay(10000);
ath_reg_rmw_clear(RST_RESET_ADDRESS, RST_RESET_PCIE_RESET_SET(1));
udelay(10000);
ath_reg_wr_nf(PCIE_APP_ADDRESS, PCIE_APP_PCIE_BAR_MSN_SET(1) |
PCIE_APP_CFG_BE_SET(0xf) |
PCIE_APP_SLV_RESP_ERR_MAP_SET(0x3f) |
PCIE_APP_LTSSM_ENABLE_SET(1));
cmd = PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | PCI_COMMAND_INVALIDATE |
PCI_COMMAND_PARITY | PCI_COMMAND_SERR | PCI_COMMAND_FAST_BACK;
ath_local_write_config(PCI_COMMAND, 4, cmd);
ath_local_write_config(0x20, 4, 0x1ff01000);
ath_local_write_config(0x24, 4, 0x1ff01000);
ath_reg_wr_nf(PCIE_RESET_ADDRESS, 4); // Pull endpoint out of reset
udelay(100000);
/* training reset */
ath_reg_rmw_set(PCIE_APP_ADDRESS, PCIE_APP_INIT_RST_SET(1));
udelay(1000);
/*
* Check if the WLAN PCI-E H/W is present, If the
* WLAN H/W is not present, skip the PCI platform
* initialization code and return
*/
if (((ath_reg_rd(PCIE_RESET_ADDRESS)) & 0x1) == 0x0) {
printf("*** Warning *** : PCIe WLAN Module not found !!!\n");
}
pci_rc2_init_board();
#endif /* CONFIG_ATH_EMULATION */
return 0;
}
PCI_INIT_RET_TYPE
pci_init_board (void)
{
#ifdef CONFIG_ATH_EMULATION
prmsg("--- Skipping %s for emulation\n", __func__);
#else
uint32_t cmd;
if (is_drqfn() && !is_qca953x()) {
/*
* Dont enable PCIe in DRQFN package as it has some issues
* related to PCIe
*/
PCI_INIT_RETURN;
}
#if defined(CONFIG_MACH_QCA953x)
if (ath_reg_rd(RST_BOOTSTRAP_ADDRESS) & RST_BOOTSTRAP_TESTROM_ENABLE_MASK) {
ath_reg_rmw_clear(RST_MISC2_ADDRESS, RST_MISC2_PERSTN_RCPHY_SET(1));
ath_reg_wr(PCIE_PHY_REG_1_ADDRESS, PCIE_PHY_REG_1_RESET_1);
ath_reg_wr(PCIE_PHY_REG_3_ADDRESS, PCIE_PHY_REG_3_RESET_1);
ath_reg_rmw_set(PCIE_PWR_MGMT_ADDRESS, PCIE_PWR_MGMT_ASSERT_CLKREQN_SET(1));
ath_reg_rmw_set(PCIE_PLL_CONFIG_ADDRESS, PCIE_PLL_CONFIG_PLLPWD_SET(1));
ath_reg_rmw_set(RST_RESET_ADDRESS, RST_RESET_PCIE_RESET_SET(1));
ath_reg_rmw_set(RST_RESET_ADDRESS, RST_RESET_PCIE_PHY_RESET_SET(1));
ath_reg_rmw_clear(RST_CLKGAT_EN_ADDRESS, RST_CLKGAT_EN_PCIE_RC_SET(1));
PCI_INIT_RETURN;
} else {
/* Honeybee -The PCIe reference clock frequency is being changed
to vary from 99.968MHz to 99.999MHz using SS modulation */
ath_reg_wr_nf(PCIE_PLL_DITHER_DIV_MAX_ADDRESS,
PCIE_PLL_DITHER_DIV_MAX_EN_DITHER_SET(0x1) |
PCIE_PLL_DITHER_DIV_MAX_USE_MAX_SET(0x1) |
PCIE_PLL_DITHER_DIV_MAX_DIV_MAX_INT_SET(0x17) |
PCIE_PLL_DITHER_DIV_MAX_DIV_MAX_FRAC_SET(0x3fff));
ath_reg_wr_nf(PCIE_PLL_DITHER_DIV_MIN_ADDRESS,
PCIE_PLL_DITHER_DIV_MIN_DIV_MIN_FRAC_SET(0x3f84)|
PCIE_PLL_DITHER_DIV_MIN_DIV_MIN_INT_SET(0x17));
}
#else
#if defined(CONFIG_MACH_QCA956x)
ath_reg_rmw_set(PCIE_PHY_REG_1_ADDRESS, PCIE_PHY_REG_1_S_SET(PCIE_PHY_REG_1_S_RESET));
ath_reg_wr_nf(PCIE_PLL_DITHER_DIV_MAX_ADDRESS,
PCIE_PLL_DITHER_DIV_MAX_USE_MAX_SET(0x1) |
PCIE_PLL_DITHER_DIV_MAX_DIV_MAX_INT_SET(0x17) |
PCIE_PLL_DITHER_DIV_MAX_DIV_MAX_FRAC_SET(0x3fff));
ath_reg_wr_nf(PCIE_PLL_DITHER_DIV_MIN_ADDRESS,
PCIE_PLL_DITHER_DIV_MIN_DIV_MIN_FRAC_SET(0x3f84) |
PCIE_PLL_DITHER_DIV_MIN_DIV_MIN_INT_SET(0x17));
#else
// common for rc1 and rc2
ath_reg_wr_nf(PCIE_PLL_DITHER_DIV_MAX_ADDRESS,
PCIE_PLL_DITHER_DIV_MAX_EN_DITHER_SET(0x1) |
PCIE_PLL_DITHER_DIV_MAX_USE_MAX_SET(0x1) |
PCIE_PLL_DITHER_DIV_MAX_DIV_MAX_INT_SET(0x14) |
PCIE_PLL_DITHER_DIV_MAX_DIV_MAX_FRAC_SET(0x3ff));
ath_reg_wr_nf(PCIE_PLL_DITHER_DIV_MIN_ADDRESS,
PCIE_PLL_DITHER_DIV_MIN_DIV_MIN_INT_SET(0x14));
#endif
#endif
ath_reg_wr_nf(PCIE_PLL_CONFIG_ADDRESS,
PCIE_PLL_CONFIG_REFDIV_SET(1) |
PCIE_PLL_CONFIG_BYPASS_SET(1) |
PCIE_PLL_CONFIG_PLLPWD_SET(1));
udelay(10000);
ath_reg_rmw_clear(PCIE_PLL_CONFIG_ADDRESS, PCIE_PLL_CONFIG_PLLPWD_SET(1));
udelay(1000);
ath_reg_rmw_clear(PCIE_PLL_CONFIG_ADDRESS, PCIE_PLL_CONFIG_BYPASS_SET(1));
udelay(1000);
#if !defined(CONFIG_MACH_QCA956x)
#ifdef PCIE2_APP_ADDRESS
if (!(ath_reg_rd(RST_BOOTSTRAP_ADDRESS) & RST_BOOTSTRAP_PCIE_RC_EP_SELECT_MASK)) {
pci_rc2_init_board();
return;
}
#endif
ath_reg_rmw_set(RST_RESET_ADDRESS, RST_RESET_PCIE_PHY_RESET_SET(1));
udelay(10000);
ath_reg_rmw_set(RST_RESET_ADDRESS, RST_RESET_PCIE_RESET_SET(1));
udelay(10000);
#ifdef PCIE2_APP_ADDRESS
ath_reg_rmw_clear(RST_MISC2_ADDRESS, RST_MISC2_PERSTN_RCPHY_SET(1));
udelay(10000);
#endif
ath_reg_wr_nf(PCIE_RESET_ADDRESS, 0); // Put endpoint in reset
udelay(100000);
#ifdef PCIE2_APP_ADDRESS
ath_reg_rmw_set(RST_MISC2_ADDRESS, RST_MISC2_PERSTN_RCPHY_SET(1));
udelay(10000);
#endif
ath_reg_rmw_clear(RST_RESET_ADDRESS, RST_RESET_PCIE_PHY_RESET_SET(1));
udelay(10000);
ath_reg_rmw_clear(RST_RESET_ADDRESS, RST_RESET_PCIE_RESET_SET(1));
udelay(10000);
ath_reg_wr_nf(PCIE_APP_ADDRESS, PCIE_APP_PCIE_BAR_MSN_SET(1) |
PCIE_APP_CFG_BE_SET(0xf) |
PCIE_APP_SLV_RESP_ERR_MAP_SET(0x3f) |
PCIE_APP_LTSSM_ENABLE_SET(1));
cmd = PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | PCI_COMMAND_INVALIDATE |
PCI_COMMAND_PARITY | PCI_COMMAND_SERR | PCI_COMMAND_FAST_BACK;
ath_local_write_config(PCI_COMMAND, 4, cmd);
ath_local_write_config(0x20, 4, 0x1ff01000);
ath_local_write_config(0x24, 4, 0x1ff01000);
ath_reg_wr_nf(PCIE_RESET_ADDRESS, 4); // Pull endpoint out of reset
udelay(100000);
/*
* Check if the WLAN PCI-E H/W is present, If the
* WLAN H/W is not present, skip the PCI platform
* initialization code and return
*/
if (((ath_reg_rd(PCIE_RESET_ADDRESS)) & 0x1) == 0x0) {
prmsg("*** Warning *** : PCIe WLAN Module not found !!!\n");
}
#endif
#ifdef PCIE2_APP_ADDRESS
pci_rc2_init_board();
#endif
#ifndef COMPRESSED_UBOOT
/*
* Now, configure for u-boot tools
*/
hose.first_busno = 0;
hose.last_busno = 0xff;
/* System space */
pci_set_region( &hose.regions[0],
0x80000000,
0x00000000,
32 * 1024 * 1024,
PCI_REGION_MEM | PCI_REGION_MEMORY);
/* PCI memory space */
pci_set_region( &hose.regions[1],
0x10000000,
0x10000000,
128 * 1024 * 1024,
PCI_REGION_MEM);
hose.region_count = 2;
pci_register_hose(&hose);
pci_set_ops( &hose,
pci_hose_read_config_byte_via_dword,
pci_hose_read_config_word_via_dword,
ath_pci_read_config,
pci_hose_write_config_byte_via_dword,
pci_hose_write_config_word_via_dword,
ath_pci_write_config);
#endif
plat_dev_init();
#endif /* CONFIG_ATH_EMULATION */
PCI_INIT_RETURN;
}
void pci_init_board (void)
#endif /* #ifdef COMPRESSED_UBOOT */
{
#ifdef CONFIG_AP123
return;
#else
uint32_t cmd = 0, reg_val;
//printf("%s: PCIe PLL 0x%x\n", __func__, mips3_cp0_count_read());
//printf("%s: PCIe PLL 0x%x 0xb8000008 = 0x%08x\n", __func__, mips3_cp0_count_read(), ar7240_reg_rd(0xb8040008));
pci_udelay(100000);
//count ++;
if ((ar7240_reg_rd(WASP_BOOTSTRAP_REG) & WASP_REF_CLK_25) == 0) {
ar7240_reg_wr_nf(AR934X_PCIE_PLL_DITHER_DIV_MAX,
PCIE_PLL_DITHER_DIV_MAX_EN_DITHER_SET(0) |
PCIE_PLL_DITHER_DIV_MAX_USE_MAX_SET(1) |
PCIE_PLL_DITHER_DIV_MAX_DIV_MAX_INT_SET(0x20) |
PCIE_PLL_DITHER_DIV_MAX_DIV_MAX_FRAC_SET(0));
} else {
#ifndef COMPRESSED_UBOOT
printf("%s: PCIe PLL not set for 40MHz refclk\n", __func__);
#endif
}
ar7240_reg_rmw_set(AR7240_RESET, AR7240_RESET_PCIE); // core in reset
pci_udelay(10000);
ar7240_reg_rmw_set(AR7240_RESET, AR7240_RESET_PCIE_PHY);// phy in reset
pci_udelay(10000);
ar7240_reg_rmw_clear(RST_MISC2_ADDRESS, RST_MISC2_PERSTN_RCPHY_SET(1)); // pci phy analog in reset
pci_udelay(10000);
ar7240_reg_wr(0x180f0000, 0x1ffc0); // ltssm is disabled
pci_udelay(100);
ar7240_reg_wr_nf(AR7240_PCI_LCL_RESET, 0); // End point in reset
pci_udelay(100000);
//ar7240_reg_rmw_clear(AR7240_RESET, AR7240_RESET_PCIE_PHY);
if ((ar7240_reg_rd(AR7240_REV_ID) & 0xf) == 0) {
ar7240_reg_wr_nf(AR934X_PCIE_PLL_CONFIG,
PCIE_PLL_CONFIG_REFDIV_SET(1) |
PCIE_PLL_CONFIG_BYPASS_SET(1) |
PCIE_PLL_CONFIG_PLLPWD_SET(1));
pci_udelay(10000);
ar7240_reg_wr_nf(AR934X_PCIE_PLL_CONFIG,
PCIE_PLL_CONFIG_REFDIV_SET(1) |
PCIE_PLL_CONFIG_BYPASS_SET(1) |
PCIE_PLL_CONFIG_PLLPWD_SET(0));
pci_udelay(1000);
ar7240_reg_wr_nf(AR934X_PCIE_PLL_CONFIG,
ar7240_reg_rd(AR934X_PCIE_PLL_CONFIG) &
(~PCIE_PLL_CONFIG_BYPASS_SET(1)));
pci_udelay(1000);
} else {
ar7240_reg_wr_nf(AR934X_PCIE_PLL_CONFIG,
PCIE_PLL_CONFIG_REFDIV_SET(2) |
PCIE_PLL_CONFIG_BYPASS_SET(1) |
PCIE_PLL_CONFIG_PLLPWD_SET(1));
pci_udelay(10000);
if ((ar7240_reg_rd(WASP_BOOTSTRAP_REG) & WASP_REF_CLK_25) == 0) {
ar7240_reg_wr_nf(0xb8116c00, (0x5 << 27) | (160 << 18) | 0);
} else {
ar7240_reg_wr_nf(0xb8116c00, (0x2 << 27) | (0x28 << 18) | 0);
}
do {
ar7240_reg_wr_nf(0xb8116c04, (0x1 << 30) | (0x4 << 26) | (0x32 << 19) | (1 << 16) | (3 << 13) | (0x1e << 7));
ar7240_reg_wr_nf(0xb8116c08, (6 << 23));
pci_udelay(10000);
ar7240_reg_wr_nf(0xb8116c04, (0x1 << 30) | (0x4 << 26) | (0x32 << 19) | (3 << 13) | (0x1e << 7));
ar7240_reg_rmw_clear(KSEG1ADDR(PCIe_DPLL3_ADDRESS), PCIe_DPLL3_DO_MEAS_SET(1));
ar7240_reg_rmw_set(KSEG1ADDR(PCIe_DPLL3_ADDRESS), PCIe_DPLL3_DO_MEAS_SET(1));
ar7240_reg_wr(0xb804000c, 1 << 2);
pci_udelay(1000);
while (((cmd = ar7240_reg_rd(PCIe_DPLL4_ADDRESS)) & PCIe_DPLL4_MEAS_DONE_SET(1)) == 0) {
printf("0x%x 0x%x 0x%x\n", KSEG1ADDR(PCIe_DPLL4_ADDRESS), cmd);
pci_udelay(10);
}
{ int i; for (i = 0; i < 100; i++) udelay(10); }
#if 0
msdvc = PCIe_DPLL4_MEAN_DVC_GET(cmd);
cmd = PCIe_DPLL3_SQSUM_DVC_GET(ar7240_reg_rd(PCIe_DPLL3_ADDRESS));
if (msdvc & 0x400) msdvc = ((~msdvc & 0x7FF) + 1); /* 11 bit signed number , but not intentioanlly multiply by (-1), ASK VIPUL*/
msdvc = cmd - (msdvc *msdvc);
msdvc_sq = msdvc * msdvc;
if (cmd >= 0x40000) {
err_count++;
if (sqsum_min_fail == 0)
sqsum_min_fail = cmd;
if (cmd > sqsum_max_fail)
sqsum_max_fail = cmd;
if (cmd < sqsum_min_fail)
sqsum_min_fail = cmd;
sqsum_avg_fail = (sqsum_avg_fail - (sqsum_avg_fail / err_count)) + (cmd / err_count);
if (num_pll_loops == 0)
err_pll1++;
if (num_pll_loops == 1)
err_pll2++;
if (num_pll_loops == 2)
err_pll3++;
if (num_pll_loops == 3)
err_pll4++;
if (num_pll_loops == 4) {
err_pll5++;
break;
}
} else {
if (sqsum_min == 0)
sqsum_min = cmd;
if (cmd < sqsum_min)
sqsum_min = cmd;
if (cmd > sqsum_max)
sqsum_max = cmd;
//sqsum_avg = (sqsum_avg - (sqsum_avg / count)) + (cmd / count);
sqsum_avg += cmd;
/*msdvc calc*/
if (msdvc_min == 0) msdvc_min = msdvc;
if (msdvc < msdvc_min) msdvc_min =msdvc;
if (msdvc > msdvc_max) msdvc_max =msdvc;
msdvc_avg += msdvc;
msdvc_sq_avg += msdvc_sq;
}
num_pll_loops++;
#endif
} while ((cmd = PCIe_DPLL3_SQSUM_DVC_GET(ar7240_reg_rd(PCIe_DPLL3_ADDRESS))) >= 0x40000);
ar7240_reg_rmw_clear(AR934X_PCIE_PLL_CONFIG, PCIE_PLL_CONFIG_PLLPWD_SET(1));
pci_udelay(10000);
ar7240_reg_rmw_clear(AR934X_PCIE_PLL_CONFIG, PCIE_PLL_CONFIG_BYPASS_SET(1));
pci_udelay(10000);
/*
* PCIe Dithering configuration
*/
if (is_ar934x_12_or_later()) {
ar7240_reg_wr_nf(PCIe_DPLL2_ADDRESS,
PCIe_DPLL2_LOCAL_PLL_SET(0) |
PCIe_DPLL2_KI_SET(0x4)|
PCIe_DPLL2_KD_SET(0x40));
ar7240_reg_wr_nf(AR934X_PCIE_PLL_CONFIG, 0x40010800);
ar7240_reg_wr_nf(AR934X_PCIE_PLL_DITHER_DIV_MAX, 0xc013fffe);
ar7240_reg_wr_nf(AR934X_PCIE_PLL_DITHER_DIV_MIN, 0x0013e666);
ar7240_reg_wr_nf(AR934X_PCIE_PLL_CONFIG, 0x00010800);
ar7240_reg_wr_nf(AR934X_PCIE_PLL_CONFIG, 0x00000800);
}
//run_command("md 0xb8116c00 4", 0);
}
ar7240_reg_rmw_set(RST_MISC2_ADDRESS, RST_MISC2_PERSTN_RCPHY_SET(1)); // pci phy analog out of reset
pci_udelay(10000);
ar7240_reg_rmw_clear(AR7240_RESET, AR7240_RESET_PCIE_PHY); // phy out of reset
pci_udelay(10000);
ar7240_reg_rmw_clear(AR7240_RESET, AR7240_RESET_PCIE); // core out of reset
pci_udelay(1000);
cmd = PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | PCI_COMMAND_INVALIDATE |
PCI_COMMAND_PARITY|PCI_COMMAND_SERR|PCI_COMMAND_FAST_BACK;
ar7240_local_write_config(PCI_COMMAND, 4, cmd); // pci cmd reg init
ar7240_local_write_config(0x20, 4, 0x1ff01000); // membase setting
ar7240_local_write_config(0x24, 4, 0x1ff01000); // prefetch membase setting
if ((is_ar7241() || is_ar7242() || is_wasp())) {
ar7240_reg_wr(0x180f0000, 0x1ffc1); // ltssm enable
} else {
ar7240_reg_wr(0x180f0000, 0x1);
}
pci_udelay(100000);
ar7240_reg_wr_nf(AR7240_PCI_LCL_RESET, 4); // EP out of reset
pci_udelay(100000);
#ifdef COMPRESSED_UBOOT
pci_udelay(100);
#else
/*
* Delay increased from 100 to 1000, so as to
* get the correct status from PCI LCL RESET register
*/
pci_udelay(100000);
/*
* Check if the WLAN PCI-E H/W is present, If the
* WLAN H/W is not present, skip the PCI platform
* initialization code and return
*/
if (((ar7240_reg_rd(AR7240_PCI_LCL_RESET)) & 0x1) == 0x0) {
printf("*** Warning *** : PCIe WLAN Module not found !!!\n");
return;
}
#endif
#ifndef COMPRESSED_UBOOT
/*
* Now, configure for u-boot tools
*/
hose.first_busno = 0;
hose.last_busno = 0xff;
/* System space */
pci_set_region( &hose.regions[0],
0x80000000,
0x00000000,
32 * 1024 * 1024,
PCI_REGION_MEM | PCI_REGION_MEMORY);
/* PCI memory space */
pci_set_region( &hose.regions[1],
0x10000000,
0x10000000,
128 * 1024 * 1024,
PCI_REGION_MEM);
hose.region_count = 2;
pci_register_hose(&hose);
pci_set_ops( &hose,
pci_hose_read_config_byte_via_dword,
pci_hose_read_config_word_via_dword,
ar7240_pci_read_config,
pci_hose_write_config_byte_via_dword,
pci_hose_write_config_word_via_dword,
ar7240_pci_write_config);
#endif
plat_dev_init();
#endif // CONFIG_AP123
#ifdef COMPRESSED_UBOOT
return 0;
#endif
}