/**
* @brief CRC_DMA_Mode_Test, CRC DMA mode test sample code.
* @param None.
* @retval None.
*/
void CRC_DMA_Mode_Test(void)
{
volatile uint32_t i;
uint8_t *p8BufAddr;
volatile uint32_t uFinalCRC;
/* PDMA Init */
PDMA_Init();
printf(" This sample code will do CRC DMA Mode Test. \n");
p8BufAddr = (uint8_t *)"123456789";
g_uTotalByteCnt = strlen("123456789");
/* CRC Setting */
PDMAGCR->CSR |= PDMAGCR_CSR_CRCCLK; /* Enable CRC Clock */
/* Reset CRC, CPU Write data length-> none */
PDMACRC->CTL = (uint32_t)(PDMACRC_CTL_CEN|PDMACRC_CTL_RST|PDMACRC_CTL_CPU_WDLEN_MASK);
PDMACRC->DMASAR = (uint32_t)p8BufAddr; /* Set Source Address */
PDMACRC->DMABCR = g_uTotalByteCnt; /* Set Byte Count Register */
/*Set SEED-> 0xFFFF */
PDMACRC->SEED = 0xFFFF;
/* Trigger CRC DMA */
PDMACRC->CTL |= PDMACRC_CTL_TRIG_EN;
while (1)
{
if (PDMACRC->DMAISR & PDMACRC_DMAISR_TABORT)
{
PDMACRC->DMAISR |= PDMACRC_DMAISR_TABORT;
printf(" CRC target abort !!! \n");
return ;
}
if (PDMACRC->DMAISR & PDMACRC_DMAISR_TD)
{
PDMACRC->DMAISR |= PDMACRC_DMAISR_TD;
// Read the CRC checksum result ......
uFinalCRC = PDMACRC->CHECKSUM & PDMACRC->SEED;
break;
}
}
if (uFinalCRC == 0x29B1)
printf("CRC DMA mode test pass\n");
else
printf("CRC DMA mode test fail\n");
/* Close PDMA CRC Channel */
PDMAGCR->CSR = 0;
/* PDMA DeInit */
PDMA_DeInit();
return;
}
// Enable I2S TX with PDMA function
void StartPlay(void)
{
printf("Start playing ...\n");
PDMA_Init();
I2S_ENABLE_TXDMA(I2S1);
I2S_ENABLE_TX(I2S1);
// enable sound output
//PI3 = 0;
audioInfo.mp3Playing = 1;
}
/*---------------------------------------------------------------------------------------------------------*/
void UART_PDMATest()
{
uint32_t i;
printf("+-----------------------------------------------------------+\n");
printf("| UART PDMA Test |\n");
printf("+-----------------------------------------------------------+\n");
printf("| Description : |\n");
printf("| The sample code will demo UART1 PDMA function. |\n");
printf("| Please connect UART1_TX and UART1_RX pin. |\n");
printf("+-----------------------------------------------------------+\n");
printf("Please press any key to start test. \n\n");
GetChar();
/*
Using UAR1 external loop back.
This code will send data from UART1_TX and receive data from UART1_RX.
*/
for (i=0; i<PDMA_TEST_LENGTH; i++) {
g_u8Tx_Buffer[i] = i;
g_u8Rx_Buffer[i] = 0xff;
}
PDMA_Init();
UART1->INTEN |= UART_INTEN_TXPDMAEN_Msk | UART_INTEN_RXPDMAEN_Msk;
#ifdef ENABLE_PDMA_INTERRUPT
while(u32IsTestOver == 0);
if (u32IsTestOver == 1)
printf("test done...\n");
else if (u32IsTestOver == 2)
printf("target abort...\n");
else if (u32IsTestOver == 3)
printf("timeout...\n");
#else
while( (!(PDMA_GET_TD_STS() & (1 << 0))) || (!(PDMA_GET_TD_STS() & (1 << 1))) );
PDMA_CLR_TD_FLAG(PDMA_TDF_TD_F_Msk);
#endif
for (i=0; i<PDMA_TEST_LENGTH; i++) {
if(g_u8Rx_Buffer[i] != i) {
printf("\n Receive Data Compare Error !!");
while(1);
}
}
printf("\nUART PDMA test Pass.\n");
}
/**
* @brief CRC_CPU_Mode_Test, CRC CPU mode test sample code.
* @param None.
* @retval None.
*/
void CRC_CPU_Mode_Test(void)
{
volatile uint32_t i;
uint8_t *p8BufAddr, u8WriteLength;
uint32_t SrcData;
uint32_t uInteger, uRemainder;
volatile uint32_t uFinalCRC;
/* PDMA Init */
PDMA_Init();
printf(" This sample code will do CRC CPU Mode Test. \n");
p8BufAddr = (uint8_t *)"123456789";
g_uTotalByteCnt = strlen("123456789");
/* CRC Setting */
PDMAGCR->CSR |= PDMAGCR_CSR_CRCCLK; /* Enable CRC Clock */
/* Reset CRC, CPU Write data length-> 32-bit */
PDMACRC->CTL = (uint32_t)(PDMACRC_CTL_CEN|PDMACRC_CTL_RST|PDMACRC_CTL_CPU_WDLEN_32BIT);
/*Set SEED-> 0xFFFF */
PDMACRC->SEED = 0xFFFF;
uInteger = g_uTotalByteCnt / 4;
uRemainder = g_uTotalByteCnt % 4;
u8WriteLength = 4;
for (i=0; i<uInteger; i++)
{
memcpy(&SrcData, p8BufAddr, u8WriteLength);
PDMACRC->WDATA = SrcData;
p8BufAddr += u8WriteLength;
}
if (uRemainder != 0)
{
if (uRemainder == 3)
{
PDMACRC->CTL = (PDMACRC->CTL & ~PDMACRC_CTL_CPU_WDLEN_MASK|PDMACRC_CTL_CPU_WDLEN_16BIT);
memcpy(&SrcData, p8BufAddr, 2);
SrcData &= 0xFFFF;
PDMACRC->WDATA = SrcData;
p8BufAddr = p8BufAddr + 2;
PDMACRC->CTL = (PDMACRC->CTL & ~PDMACRC_CTL_CPU_WDLEN_MASK|PDMACRC_CTL_CPU_WDLEN_8BIT);
SrcData &= 0xFF;
memcpy(&SrcData, p8BufAddr, 1);
PDMACRC->WDATA = SrcData;
}
else if (uRemainder == 2)
{
PDMACRC->CTL = (PDMACRC->CTL & ~PDMACRC_CTL_CPU_WDLEN_MASK|PDMACRC_CTL_CPU_WDLEN_16BIT);
memcpy(&SrcData, p8BufAddr, 2);
SrcData &= 0xFFFF;
PDMACRC->WDATA = SrcData;
}
else if (uRemainder == 1)
{
PDMACRC->CTL = (PDMACRC->CTL & ~PDMACRC_CTL_CPU_WDLEN_MASK|PDMACRC_CTL_CPU_WDLEN_8BIT);
SrcData &= 0xFF;
memcpy(&SrcData, p8BufAddr, 1);
PDMACRC->WDATA = SrcData;
}
}
uFinalCRC = PDMACRC->CHECKSUM & PDMACRC->SEED;
if (uFinalCRC == 0x29B1)
printf("CRC CPU mode test pass\n");
else
printf("CRC CPU mode test fail\n");
/* Close PDMA CRC Channel */
PDMAGCR->CSR = 0;
/* PDMA DeInit */
PDMA_DeInit();
return;
}