static void temp_smbus_init(int chan)
{
uintptr_t reg;
reg = PHYS_TO_K1(A_SMB_REGISTER(chan,R_SMB_FREQ));
SBWRITECSR(reg,K_SMB_FREQ_100KHZ); /* 400Khz clock */
reg = PHYS_TO_K1(A_SMB_REGISTER(chan,R_SMB_CONTROL));
SBWRITECSR(reg,0); /* not in direct mode, no interrupts, will poll */
}
static int bcm6348_ether_read( cfe_devctx_t * ctx, iocb_buffer_t * buffer )
{
unsigned char * dstptr;
unsigned char * srcptr;
volatile DmaDesc * CurrentBdPtr;
bcmenet_softc * softc = (bcmenet_softc *) ctx->dev_softc;
uint16 dmaFlag;
if( ctx == NULL ) {
xprintf( "No context\n" );
return -1;
}
if( buffer == NULL ) {
xprintf( "No dst buffer\n" );
return -1;
}
if( buffer->buf_length > ENET_MAX_MTU_SIZE ) {
xprintf( "dst buffer too small.\n" );
xprintf( "actual size is %d\n", buffer->buf_length );
return -1;
}
if( softc == NULL ) {
xprintf( "softc has not been initialized.\n" );
return -1;
}
dmaFlag = (uint16) softc->rxBdReadPtr->status;
if (!(dmaFlag & DMA_EOP))
{
xprintf("dmaFlag (return -1)[%04x]\n", dmaFlag);
return -1;
}
dstptr = buffer->buf_ptr;
CurrentBdPtr = softc->rxBdReadPtr;
srcptr = (unsigned char *)( PHYS_TO_K1(CurrentBdPtr->address) );
buffer->buf_retlen = CurrentBdPtr->length;
memcpy( dstptr, srcptr, buffer->buf_retlen );
CurrentBdPtr->length = ENET_BUF_SIZE;
CurrentBdPtr->status &= DMA_WRAP;
CurrentBdPtr->status |= DMA_OWN;
IncRxBdPtr( CurrentBdPtr, softc );
softc->rxBdReadPtr = CurrentBdPtr;
softc->dmaCtrl->flowctl_ch1_alloc = 1;
// enable rx dma
softc->rxDma->cfg = DMA_ENABLE;
return 0;
}
/*******************************************************************************
*
* bcm1250TimerBase - return a pointer to the SCD base address register of
* the specified timer
*
* RETURNS: address of a timer's base register, NULL if a bogus timer is requested
*
*/
LOCAL char * bcm1250TimerBase
(
int unit
)
{
switch (unit)
{
case BCM1250_TIMER_0:
return (char *)PHYS_TO_K1(A_SCD_TIMER_BASE(0));
case BCM1250_TIMER_1:
return (char *)PHYS_TO_K1(A_SCD_TIMER_BASE(1));
case BCM1250_TIMER_2:
return (char *)PHYS_TO_K1(A_SCD_TIMER_BASE(2));
case BCM1250_TIMER_3:
return (char *)PHYS_TO_K1(A_SCD_TIMER_BASE(3));
}
return NULL;
}
static int temp_smbus_write(int chan,int slaveaddr,int devaddr,int data)
{
uintptr_t reg;
int err;
/*
* Make sure the bus is idle (probably should
* ignore error here)
*/
if (temp_smbus_waitready(chan) < 0) return -1;
/*
* Write the device address to the controller. There are two
* parts, the high part goes in the "CMD" field, and the
* low part is the data field.
*/
reg = PHYS_TO_K1(A_SMB_REGISTER(chan,R_SMB_CMD));
SBWRITECSR(reg,devaddr);
/*
* Write the data byte
*/
reg = PHYS_TO_K1(A_SMB_REGISTER(chan,R_SMB_DATA));
SBWRITECSR(reg,data);
/*
* Do the write command.
*/
reg = PHYS_TO_K1(A_SMB_REGISTER(chan,R_SMB_START));
SBWRITECSR(reg,V_SMB_TT(K_SMB_TT_WR2BYTE) | slaveaddr);
err = temp_smbus_waitready(chan);
return err;
}
/*
* Standard eCos initialization routine. Call the upper-level ethernet
* driver and let it know our MAC address.
*/
static int
ae531x_init(struct eth_device *dev, bd_t *bis)
{
unsigned char enaddr[ETHER_ADDR_LEN];
char *mac_addr;
ae531x_priv_data_t *ae531x_priv;
ae531x_MAC_t *MACInfo;
int unit;
ae531x_priv = (ae531x_priv_data_t *)dev->priv;
unit = ae531x_priv->enetUnit;
/* Get ethernet's MAC address from board configuration data */
memcpy(enaddr, DEFAULT_MAC_ADDRESS, ETHER_ADDR_LEN);
MACInfo = &ae531x_priv->MACInfo;
/* Initialize MACInfo */
MACInfo->OSinfo = (void *)ae531x_priv;
MACInfo->unit = unit;
if (unit == 0) {
MACInfo->macBase = (UINT32)(PHYS_TO_K1(AR531X_ENET0)+AE531X_MAC_OFFSET);
MACInfo->dmaBase = (UINT32)(PHYS_TO_K1(AR531X_ENET0)+AE531X_DMA_OFFSET);
MACInfo->phyBase = (UINT32)(PHYS_TO_K1(AR531X_ENET0)+AE531X_PHY_OFFSET);
}
/* Bring MAC and PHY out of reset */
ae531x_reset(MACInfo);
/* Initialize PHY */
phySetup(MACInfo->unit, MACInfo->phyBase);
return 1;
}
void bcm1250DuartDevInit
(
BCM1250_DUART_CHAN * pChan
)
{
int oldlevel;
pChan->intEnable = FALSE;
if((pChan->channel != BCM1250_DUART_CHANNEL_A ) &&
(pChan->channel != BCM1250_DUART_CHANNEL_B))
return;
pChan->duartBase = (void *)PHYS_TO_K1(A_DUART);
pChan->chanBase = pChan->duartBase + R_DUART_CHANREG(pChan->channel, 0);
pChan->chanIMR = (unsigned long long *)
(pChan->duartBase + R_DUART_IMRREG(pChan->channel));
pChan->chanISR = (unsigned long long *)
(pChan->duartBase + R_DUART_ISRREG(pChan->channel));
pChan->intSource = (pChan->channel == BCM1250_DUART_CHANNEL_A) ?
K_INT_UART_0 : K_INT_UART_1;
/* clear delta interrupts */
bcm1250DuartAcrSet (pChan, 0);
/* don't relay TX clock on output in */
bcm1250DuartTxCoutRelay (pChan, FALSE );
/* assert RTS (request to send ) */
bcm1250DuartRts (pChan, TRUE);
/* init callbacks and set default options */
bcm1250DuartInitStruct (pChan);
oldlevel = intLock ();
/* Clear the interrupt mask register */
MIPS3_SD(pChan->chanIMR, 0);
bcm1250DuartInitChannel (pChan);
intUnlock (oldlevel);
}
static void idedrv_ins(idecommon_dispatch_t *disp,uint32_t reg,uint8_t *buf,int len)
{
uint16_t data;
while (len > 0) {
data = *((volatile uint16_t *) PHYS_TO_K1(reg+disp->baseaddr));
#ifdef _BYTESWAP_
*buf++ = (data >> 8) & 0xFF;
*buf++ = (data & 0xFF);
#else
*buf++ = (data & 0xFF);
*buf++ = (data >> 8) & 0xFF;
#endif
len--;
len--;
}
}
/* *********************************************************************
* temp_smbus_waitready(chan)
*
* Wait until the SMBus channel is ready. We simply poll
* the busy bit until it clears.
*
* Input parameters:
* chan - channel (0 or 1)
*
* Return value:
* nothing
********************************************************************* */
static int temp_smbus_waitready(int chan)
{
uintptr_t reg;
uint64_t status;
reg = PHYS_TO_K1(A_SMB_REGISTER(chan,R_SMB_STATUS));
for (;;) {
status = SBREADCSR(reg);
if (status & M_SMB_BUSY) continue;
break;
}
if (status & M_SMB_ERROR) {
SBWRITECSR(reg,(status & M_SMB_ERROR));
return -1;
}
return 0;
}
static void idedrv_outs(idecommon_dispatch_t *disp,uint32_t reg,uint8_t *buf,int len)
{
uint16_t data;
while (len > 0) {
#ifdef _BYTESWAP_
data = (uint16_t) buf[1] + ((uint16_t) buf[0] << 8);
#else
data = (uint16_t) buf[0] + ((uint16_t) buf[1] << 8);
#endif
*((volatile uint16_t *) PHYS_TO_K1(reg+disp->baseaddr)) = data;
_wbflush();
buf++;
buf++;
len--;
len--;
}
}
/* --------------------------------------------------------------------------
Name: bcm6352_enet_read
Purpose: Returns a recevied data buffer.
-------------------------------------------------------------------------- */
static int bcm6352_enet_read( cfe_devctx_t *ctx, iocb_buffer_t *buffer )
{
uint32_t rxEvents;
unsigned char *dstptr;
unsigned char *srcptr;
volatile DmaDesc *CurrentBdPtr;
bcm6352enet_softc *softc = (bcm6352enet_softc *) ctx->dev_softc;
/* ============================= ASSERTIONS ============================= */
if( ctx == NULL ) {
xprintf( "No context\n" );
return -1;
}
if( buffer == NULL ) {
xprintf( "No dst buffer\n" );
return -1;
}
if( buffer->buf_length != ENET_MAX_BUF_SIZE ) {
xprintf( "dst buffer too small.\n" );
xprintf( "actual size is %d\n", buffer->buf_length );
return -1;
}
if( softc == NULL ) {
xprintf( "softc has not been initialized.\n" );
return -1;
}
/* ====================================================================== */
dstptr = buffer->buf_ptr;
CurrentBdPtr = softc->rxBdReadPtr;
if( (CurrentBdPtr->status & DMA_OWN) == 1 )
return -1;
srcptr = (unsigned char *)( PHYS_TO_K1(CurrentBdPtr->address) );
memcpy( dstptr, srcptr, ETH_ALEN * 2 );
dstptr += ETH_ALEN * 2;
memcpy( dstptr, srcptr + HEDR_LEN, CurrentBdPtr->length - HEDR_LEN - 8 );
/* length - header difference - 2 CRCs */
buffer->buf_retlen = CurrentBdPtr->length - 6 - 8;
CurrentBdPtr->length = ENET_MAX_MTU_SIZE;
CurrentBdPtr->status &= DMA_WRAP;
CurrentBdPtr->status |= DMA_OWN;
IncRxBDptr(CurrentBdPtr, softc);
softc->rxBdReadPtr = CurrentBdPtr;
rxEvents = softc->rxDma->intStat;
softc->rxDma->intStat = rxEvents;
softc->rxDma->cfg = DMA_ENABLE | DMA_CHAINING | DMA_WRAP_EN;
return 0;
}
static void idedrv_outw(idecommon_dispatch_t *disp,uint32_t reg,uint16_t val)
{
*((volatile uint16_t *) PHYS_TO_K1(reg+disp->baseaddr)) = val;
_wbflush();
}
static uint16_t idedrv_inw(idecommon_dispatch_t *disp,uint32_t reg)
{
return *((volatile uint16_t *) PHYS_TO_K1((reg+disp->baseaddr)));
}
{ "bdSize", HCF_RES_INT, { (void *)(0) } },
{ "rxBdCount", HCF_RES_INT, { (void *)(0) } },
{ "txBdCount", HCF_RES_INT, { (void *)(0) } },
{ "phyAddr", HCF_RES_INT, {(void *)0x0 }},
{ "miiIfName", HCF_RES_STRING, { (void *)"atse" } },
{ "miiIfUnit", HCF_RES_INT, { (void *)0 } }
};
#define atsemac0Num NELEMENTS(atsemac0Resources)
#endif
#define LS3A_FREQ 500000000 //mxl: 495000000
#ifdef INCLUDE_SBE0
LOCAL const struct hcfResource sbeVxbEnd0Resources[] = {
{ "regBase", HCF_RES_INT, { (void *)(PHYS_TO_K1(A_MAC_BASE_0)) } },
};
#define sbeVxbEnd0Num NELEMENTS(sbeVxbEnd0Resources)
#endif
#ifdef INCLUDE_SBE1
LOCAL const struct hcfResource sbeVxbEnd1Resources[] = {
{ "regBase", HCF_RES_INT, { (void *)(PHYS_TO_K1(A_MAC_BASE_1)) } },
};
#define sbeVxbEnd1Num NELEMENTS(sbeVxbEnd1Resources)
#endif
#if 1
/* Added for ns16550 serial resources! 20091211 */
#ifdef DRV_SIO_NS16550
struct hcfResource ns16550Dev0Resources[] = {
ipPhyInfo_t ipPhyInfo[] = {
/*
* On AP30/AR5312, all PHYs are associated with MAC0.
* AP30/AR5312's MAC1 isn't used for anything.
* CONFIG_VENETDEV==1 (router) configuration:
* Ports 0,1,2, and 3 are "LAN ports"
* Port 4 is a WAN port
* Port 5 connects to MAC0 in the AR5312
* CONFIG_VENETDEV==0 (bridge) configuration:
* Ports 0,1,2,3,4 are "LAN ports"
* Port 5 connects to the MAC0 in the AR5312
*/
{TRUE, /* phy port 0 -- LAN port 0 */
FALSE,
ENET_UNIT_DEFAULT,
(UINT32) (PHYS_TO_K1(AR531XPLUS_ENET0)+AE531X_PHY_OFFSET),
IP_PHY0_ADDR,
IP_LAN_PORT_VLAN
},
{TRUE, /* phy port 1 -- LAN port 1 */
FALSE,
ENET_UNIT_DEFAULT,
(UINT32) (PHYS_TO_K1(AR531XPLUS_ENET0)+AE531X_PHY_OFFSET),
IP_PHY1_ADDR,
IP_LAN_PORT_VLAN
},
{TRUE, /* phy port 2 -- LAN port 2 */
FALSE,
ENET_UNIT_DEFAULT,
static int bcm6348_ether_write(cfe_devctx_t *ctx,iocb_buffer_t *buffer)
{
uint32_t status;
unsigned char * dstptr;
bcmenet_softc * softc;
volatile DmaDesc * CurrentBdPtr;
volatile uint32 txEvents = 0;
/* ============================= ASSERTIONS ============================= */
if( ctx == NULL ) {
xprintf( "No context\n" );
return -1;
}
if( buffer == NULL ) {
xprintf( "No dst buffer\n" );
return -1;
}
if( buffer->buf_length > ENET_MAX_MTU_SIZE ) {
xprintf( "src buffer too large.\n" );
xprintf( "size is %d\n", buffer->buf_length );
return -1;
}
softc = (bcmenet_softc *) ctx->dev_softc;
if( softc == NULL ) {
xprintf( "softc has not been initialized.\n" );
return -1;
}
/* ====================================================================== */
CurrentBdPtr = softc->txNextBdPtr;
/* Find out if the next BD is available. */
if( CurrentBdPtr->status & DMA_OWN ) {
xprintf( "No tx BD available ?!\n" );
return -1;
}
dstptr = (unsigned char *)PHYS_TO_K1( CurrentBdPtr->address );
memcpy( dstptr, buffer->buf_ptr, buffer->buf_length );
/* Set status of DMA BD to be transmitted. */
status = DMA_SOP | DMA_EOP | DMA_APPEND_CRC | DMA_OWN;
if( CurrentBdPtr == softc->txLastBdPtr ) {
status |= DMA_WRAP;
}
CurrentBdPtr->length = buffer->buf_length;
CurrentBdPtr->status = status;
// Enable DMA for this channel
softc->txDma->cfg |= DMA_ENABLE;
// poll the dma status until done
do
{
txEvents = CurrentBdPtr->status;
} while (txEvents & DMA_OWN);
//Advance BD pointer to next in the chain.
InctxBdPtr( CurrentBdPtr, softc );
softc->txNextBdPtr = CurrentBdPtr;
return 0;
}
