void C6821::mc6821_write_ddrb(BYTE byte, unsigned int dnr)
{
if (mc6821[dnr].ddrb == byte) // AppleWin:TC
return;
mc6821[dnr].ddrb = byte;
if (mc6821[dnr].ddrb) // AppleWin:TC
PIA_W_CALLBACK( m_stOutB, mc6821[dnr].prb & mc6821[dnr].ddrb );
}
void C6821::mc6821_write_pra(BYTE byte, unsigned int dnr)
{
//if (mc6821[dnr].drive->parallel_cable == DRIVE_PC_DD3)
// parallel_cable_drive_write(byte, PARALLEL_WRITE, dnr);
mc6821[dnr].pra = byte;
if (mc6821[dnr].ddra) // AppleWin:TC
PIA_W_CALLBACK( m_stOutA, mc6821[dnr].pra & mc6821[dnr].ddra );
}
void C6821::mc6821_write_ddra(BYTE byte, unsigned int dnr)
{
//parallel_cable_drive_write((BYTE)((~byte) | mc6821[dnr].pra), PARALLEL_WRITE, dnr);
if (mc6821[dnr].ddra == byte) // AppleWin:TC
return;
mc6821[dnr].ddra = byte;
if (mc6821[dnr].ddra) // AppleWin:TC
PIA_W_CALLBACK( m_stOutA, mc6821[dnr].pra & mc6821[dnr].ddra );
}
void C6821::SetCB1(BYTE byData)
{
byData = byData ? 1 : 0;
// the new state has caused a transition
if ( m_byCB1 ^ byData )
{
// handle the active transition
if ( ( byData && C1_LOW_TO_HIGH( m_byCTLB ) ) ||
( !byData && C1_HIGH_TO_LOW( m_byCTLB ) ) )
{
// mark the IRQ
SET_IRQ1( m_byCTLB );
// update externals
UpdateInterrupts();
// CB2 is configured as output and in read strobe mode and cleared by a CA1 transition
if ( C2_OUTPUT( m_byCTLB ) && C2_STROBE_MODE( m_byCTLB ) && STROBE_C1_RESET( m_byCTLB ) )
{
// the IRQ1 flag must have also been cleared
if ( !IRQ1( m_byCTLB ) )
{
// call the CB2 output function
if ( !m_byOCB2 )
PIA_W_CALLBACK( m_stOutCB2, 1 );
// clear CB2
m_byOCB2 = 1;
}
}
}
}
// set the new value for CA1
m_byCB1 = byData;
}
void C6821::Write(BYTE byRS, BYTE byData)
{
byRS &= 3;
switch( byRS )
{
/******************* port A output/DDR write *******************/
case PIA_DDRA:
// write output register
if ( OUTPUT_SELECTED( m_byCTLA ) )
{
// update the output value
m_byOA = byData;
// send it to the output function
if ( m_byDDRA )
PIA_W_CALLBACK( m_stOutA, m_byOA & m_byDDRA );
}
// write DDR register
else
{
if ( m_byDDRA != byData )
{
m_byDDRA = byData;
// send it to the output function
if ( m_byDDRA )
PIA_W_CALLBACK( m_stOutA, m_byOA & m_byDDRA );
}
}
break;
/******************* port B output/DDR write *******************/
case PIA_DDRB:
// write output register
if ( OUTPUT_SELECTED( m_byCTLB ) )
{
// update the output value
m_byOB = byData;
// send it to the output function
if ( m_byDDRB )
PIA_W_CALLBACK( m_stOutB, m_byOB & m_byDDRB );
// CB2 is configured as output and in write strobe mode
if ( C2_OUTPUT( m_byCTLB ) && C2_STROBE_MODE( m_byCTLB ) )
{
// this will cause a transition low; call the output function if we're currently high
if ( m_byOCB2 )
PIA_W_CALLBACK( m_stOutCB2, 0 );
m_byOCB2 = 0;
// if the CB2 strobe is cleared by the E, reset it right away
if ( STROBE_E_RESET( m_byCTLB ) )
{
PIA_W_CALLBACK( m_stOutCB2, 1 );
m_byOCB2 = 1;
}
}
}
// write DDR register
else
{
if ( m_byDDRB != byData )
{
m_byDDRB = byData;
// send it to the output function
if ( m_byDDRB )
PIA_W_CALLBACK( m_stOutB, m_byOB & m_byDDRB );
}
}
break;
/******************* port A control write *******************/
case PIA_CTLA:
// Bit 7 and 6 read only
byData &= 0x3f;
// CA2 is configured as output and in set/reset mode
if ( C2_OUTPUT( byData ) )
{
// determine the new value
int temp = SET_C2( byData ) ? 1 : 0;
// if this creates a transition, call the CA2 output function
if ( m_byOCA2 ^ temp)
PIA_W_CALLBACK( m_stOutCA2, temp );
// set the new value
m_byOCA2 = temp;
}
// update the control register
m_byCTLA = ( m_byCTLA & ~0x3F ) | byData;
// update externals
UpdateInterrupts();
break;
/******************* port B control write *******************/
case PIA_CTLB:
/* Bit 7 and 6 read only - PD 16/01/00 */
byData &= 0x3f;
// CB2 is configured as output and in set/reset mode
if ( C2_OUTPUT( byData ) )
{
// determine the new value
int temp = SET_C2( byData ) ? 1 : 0;
// if this creates a transition, call the CA2 output function
if ( m_byOCB2 ^ temp)
PIA_W_CALLBACK( m_stOutCB2, temp );
// set the new value
m_byOCB2 = temp;
}
// update the control register
m_byCTLB = ( m_byCTLB & ~0x3F ) | byData;
// update externals
UpdateInterrupts();
break;
}
}
BYTE C6821::Read(BYTE byRS)
{
BYTE retval = 0;
byRS &= 3;
switch ( byRS )
{
/******************* port A output/DDR read *******************/
case PIA_DDRA:
// read output register
if ( OUTPUT_SELECTED(m_byCTLA) )
{
// combine input and output values
retval = ( m_byOA & m_byDDRA ) | ( m_byIA & ~m_byDDRA );
// IRQ flags implicitly cleared by a read
CLEAR_IRQ1( m_byCTLA );
CLEAR_IRQ1( m_byCTLB );
UpdateInterrupts();
// CA2 is configured as output and in read strobe mode
if ( C2_OUTPUT(m_byCTLA) && C2_STROBE_MODE(m_byCTLA) )
{
// this will cause a transition low; call the output function if we're currently high
if ( m_byOCA2 )
PIA_W_CALLBACK( m_stOutCA2, 0 );
m_byOCA2 = 0;
// if the CA2 strobe is cleared by the E, reset it right away
if ( STROBE_E_RESET( m_byCTLA ) )
{
PIA_W_CALLBACK( m_stOutCA2, 1 );
m_byOCA2 = 1;
}
}
}
// read DDR register
else
{
retval = m_byDDRA;
}
break;
/******************* port B output/DDR read *******************/
case PIA_DDRB:
// read output register
if ( OUTPUT_SELECTED( m_byCTLB ) )
{
// combine input and output values
retval = ( m_byOB & m_byDDRB ) + ( m_byIB & ~m_byDDRB );
// IRQ flags implicitly cleared by a read
CLEAR_IRQ2( m_byCTLA );
CLEAR_IRQ2( m_byCTLB );
UpdateInterrupts();
}
/* read DDR register */
else
{
retval = m_byDDRB;
}
break;
/******************* port A control read *******************/
case PIA_CTLA:
// read control register
retval = m_byCTLA;
// when CA2 is an output, IRQA2 = 0, and is not affected by CA2 transitions.
if ( C2_OUTPUT( m_byCTLA ) )
retval &= ~PIA_IRQ2;
break;
/******************* port B control read *******************/
case PIA_CTLB:
retval = m_byCTLB;
// when CB2 is an output, IRQB2 = 0, and is not affected by CB2 transitions.
if ( C2_OUTPUT( m_byCTLB ) )
retval &= ~PIA_IRQ2;
break;
}
return retval;
}