VOID
PciePifPllConfigureML (
IN PCIe_WRAPPER_CONFIG *Wrapper,
IN PCIe_PLATFORM_CONFIG *Pcie
)
{
D0F0xE4_PIF_0012_STRUCT D0F0xE4_PIF_0012;
IDS_HDT_CONSOLE (GNB_TRACE, "PciePifPllConfigureML Enter\n");
D0F0xE4_PIF_0012.Value = PcieRegisterRead (
Wrapper,
PIF_SPACE (Wrapper->WrapId, 0, D0F0xE4_PIF_0012_ADDRESS),
Pcie
);
D0F0xE4_PIF_0012.Field.PllRampUpTime = 0x0;
if (Wrapper->Features.PowerOffUnusedPlls != 0) {
D0F0xE4_PIF_0012.Field.PllPowerStateInOff = PifPowerStateOff;
D0F0xE4_PIF_0012.Field.PllPowerStateInTxs2 = PifPowerStateOff;
} else {
D0F0xE4_PIF_0012.Field.PllPowerStateInOff = PifPowerStateL0;
D0F0xE4_PIF_0012.Field.PllPowerStateInTxs2 = PifPowerStateL0;
}
if (Wrapper->Features.PllOffInL1 != 0) {
D0F0xE4_PIF_0012.Field.TxPowerStateInTxs2 = PifPowerStateLS2;
D0F0xE4_PIF_0012.Field.RxPowerStateInRxs2 = PifPowerStateLS2;
} else {
D0F0xE4_PIF_0012.Field.TxPowerStateInTxs2 = PifPowerStateL0;
D0F0xE4_PIF_0012.Field.RxPowerStateInRxs2 = PifPowerStateL0;
}
PcieRegisterWrite (
Wrapper,
PIF_SPACE (Wrapper->WrapId, 0, D0F0xE4_PIF_0012_ADDRESS),
D0F0xE4_PIF_0012.Value,
TRUE,
Pcie
);
PcieRegisterWrite (
Wrapper,
PIF_SPACE (Wrapper->WrapId, 0, D0F0xE4_PIF_0012_ADDRESS + 1),
D0F0xE4_PIF_0012.Value,
TRUE,
Pcie
);
IDS_HDT_CONSOLE (GNB_TRACE, "PciePifPllConfigureML Exit\n");
}
VOID
PciePwrAutoPowerDownElectricalIdleDetector (
IN PCIe_WRAPPER_CONFIG *Wrapper,
IN PCIe_PLATFORM_CONFIG *Pcie
)
{
UINT8 Pif;
IDS_HDT_CONSOLE (GNB_TRACE, "PciePwrAutoPowerDownElectricalIdleDetector Enter\n");
for (Pif = 0; Pif < Wrapper->NumberOfPIFs; Pif++) {
PcieRegisterWriteField (
Wrapper,
PIF_SPACE (Wrapper->WrapId, Pif, D0F0xE4_PIF_0010_ADDRESS),
D0F0xE4_PIF_0010_EiDetCycleMode_OFFSET,
D0F0xE4_PIF_0010_EiDetCycleMode_WIDTH,
0x0,
TRUE,
Pcie
);
PcieRegisterWriteField (
Wrapper,
PIF_SPACE (Wrapper->WrapId, Pif, D0F0xE4_PIF_0010_ADDRESS),
D0F0xE4_PIF_0010_EiCycleOffTime_OFFSET,
D0F0xE4_PIF_0010_EiCycleOffTime_WIDTH,
0x2,
TRUE,
Pcie
);
PcieRegisterWriteField (
Wrapper,
PIF_SPACE (Wrapper->WrapId, Pif, D0F0xE4_PIF_0010_ADDRESS),
D0F0xE4_PIF_0010_EiDetCycleMode_OFFSET,
D0F0xE4_PIF_0010_EiDetCycleMode_WIDTH,
0x1,
TRUE,
Pcie
);
}
IDS_HDT_CONSOLE (GNB_TRACE, "PciePwrAutoPowerDownElectricalIdleDetector Exit\n");
}
VOID
STATIC
PcieMidPortInitCallbackKV (
IN PCIe_ENGINE_CONFIG *Engine,
IN OUT VOID *Buffer,
IN PCIe_PLATFORM_CONFIG *Pcie
)
{
DxFxx68_STRUCT DxFxx68;
D0F0xE4_PIF_0012_STRUCT D0F0xE4_PIF_0012;
PCIe_SUBLINK_INFO *SublinkInfo;
PCIe_WRAPPER_INFO *WrapperInfo;
PCIe_WRAPPER_CONFIG *Wrapper;
CPU_LOGICAL_ID LogicalId;
UINT8 Count;
UINT8 Nibble;
PciePortProgramRegisterTable (PortInitMidTableKV.Table, PortInitMidTableKV.Length, Engine, TRUE, Pcie);
if (PcieConfigCheckPortStatus (Engine, INIT_STATUS_PCIE_TRAINING_SUCCESS) || Engine->Type.Port.PortData.LinkHotplug != HotplugDisabled) {
PcieEnableSlotPowerLimitV5 (Engine, Pcie);
if (GnbFmCheckIommuPresent ((GNB_HANDLE*) PcieConfigGetParentSilicon (Engine), GnbLibGetHeader (Pcie))) {
PcieInitPortForIommuV4 (Engine, Pcie);
}
// After GFX link is trained up and before ASPM is enabled, AGESA needs to check link width,
// if it equals to x16, then apply the following change to GFX port:
// Per port register 0xA1 - PCIE LC TRAINING CONTROL, bit16 - LC_EXTEND_WAIT_FOR_SKP = 1
GnbLibPciRead (
Engine->Type.Port.Address.AddressValue | DxFxx68_ADDRESS,
AccessWidth32,
&DxFxx68,
GnbLibGetHeader (Pcie)
);
if (DxFxx68.Field.NegotiatedLinkWidth == 16) {
PciePortRegisterRMW (
Engine,
DxFxxE4_xA1_ADDRESS,
DxFxxE4_xA1_LcExtendWaitForSkp_MASK,
(1 << DxFxxE4_xA1_LcExtendWaitForSkp_OFFSET),
TRUE,
Pcie
);
}
}
Wrapper = PcieConfigGetParentWrapper (Engine);
SublinkInfo = &(((PCIe_INFO_BUFFER *)Buffer)->SublinkInfo[MIN (Engine->EngineData.StartLane, Engine->EngineData.EndLane) / 4]);
WrapperInfo = &(((PCIe_INFO_BUFFER *)Buffer)->WrapperInfo[Wrapper->WrapId]);
GetLogicalIdOfCurrentCore (&LogicalId, (AMD_CONFIG_PARAMS *)Pcie->StdHeader);
// Check if this CPU is KV A0
// UBTS468566
if ((LogicalId.Revision & AMD_F15_KV_A0) != 0) {
Count = SublinkInfo->GppPortCount;
IDS_HDT_CONSOLE (GNB_TRACE, "x1x2 PortCount = %02x\n", Count);
if (Count == 2) {
// If number of GPP ports under the same sublink is 2, Delay L1 Exit (prolong minimum time spent in L1)
PciePortRegisterRMW (
Engine,
DxFxxE4_xA0_ADDRESS,
DxFxxE4_xA0_LcDelayCount_MASK |
DxFxxE4_xA0_LcDelayL1Exit_MASK,
(0 << DxFxxE4_xA0_LcDelayCount_OFFSET) |
(1 << DxFxxE4_xA0_LcDelayL1Exit_OFFSET),
TRUE,
Pcie
);
} else if (Count > 2) {
// If number of GPP ports > 2
if (SublinkInfo->MaxGenCapability > Gen1) {
// If at least 1 GPP is Gen2 capable, Disable PLL Power down feature
Wrapper = PcieConfigGetParentWrapper (Engine);
Nibble = (UINT8) ((MIN (Engine->EngineData.StartLane, Engine->EngineData.EndLane) % 8) / 4);
// Only PSD and PPD can have x1/x2 links, so we assume that PIF number is always 0
D0F0xE4_PIF_0012.Value = PcieRegisterRead (
Wrapper,
PIF_SPACE (Wrapper->WrapId, 0, D0F0xE4_PIF_0012_ADDRESS + Nibble),
Pcie
);
D0F0xE4_PIF_0012.Field.PllPowerStateInOff = PifPowerStateL0;
D0F0xE4_PIF_0012.Field.PllPowerStateInTxs2 = PifPowerStateL0;
PcieRegisterWrite (
Wrapper,
PIF_SPACE (Wrapper->WrapId, 0, D0F0xE4_PIF_0012_ADDRESS + Nibble),
D0F0xE4_PIF_0012.Value,
TRUE,
Pcie
);
} else {
// All ports are only Gen1
PciePortRegisterRMW (
Engine,
DxFxxE4_xC0_ADDRESS,
DxFxxE4_xC0_StrapMedyTSxCount_MASK,
0x2 << DxFxxE4_xC0_StrapMedyTSxCount_OFFSET,
TRUE,
Pcie
);
}
}
}
PcieRegisterRMW (
Wrapper,
WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_0802_ADDRESS + (0x100 * Engine->Type.Port.PortId)),
D0F0xE4_WRAP_0802_StrapBifL1ExitLatency_MASK,
(WrapperInfo->L1ExitLatencyValue << D0F0xE4_WRAP_0802_StrapBifL1ExitLatency_OFFSET),
TRUE,
Pcie
);
if (WrapperInfo->DisableL1OnWrapper == TRUE) {
Engine->Type.Port.PortData.LinkAspm &= ~(AspmL1);
}
PcieEnableAspm (Engine, Pcie);
}
AGESA_STATUS
STATIC
PcieMidWrapperCharacterizationCallbackKV (
IN PCIe_WRAPPER_CONFIG *Wrapper,
IN VOID *Buffer,
IN PCIe_PLATFORM_CONFIG *Pcie
)
{
PCIe_WRAPPER_INFO *WrapperInfo;
UINT8 Pif;
D0F0xE4_PIF_0012_STRUCT D0F0xE4_PIF_0012;
UINT8 ActualL1Latency;
WrapperInfo = &(((PCIe_INFO_BUFFER *)Buffer)->WrapperInfo[Wrapper->WrapId]);
WrapperInfo->ActualL1Latency = EI_CYCLING_TIME + PLL_RAMP_UP_TIME + LS2_EXIT_TIME + RECOVER_TO_L0_TIME;
if (WrapperInfo->MinAspmL1ExitLatency < WrapperInfo->ActualL1Latency) {
WrapperInfo->ActualL1Latency -= EI_CYCLING_TIME;
for (Pif = 0; Pif < Wrapper->NumberOfPIFs; Pif++) {
PcieRegisterRMW (
Wrapper,
PIF_SPACE (Wrapper->WrapId, Pif, D0F0xE4_PIF_0010_ADDRESS),
D0F0xE4_PIF_0010_EiDetCycleMode_MASK,
(0 << D0F0xE4_PIF_0010_EiDetCycleMode_OFFSET),
TRUE,
Pcie
);
}
}
if (WrapperInfo->MinAspmL1ExitLatency < WrapperInfo->ActualL1Latency) {
WrapperInfo->ActualL1Latency -= PLL_RAMP_UP_TIME;
D0F0xE4_PIF_0012.Value = PcieRegisterRead (
Wrapper,
PIF_SPACE (Wrapper->WrapId, 0, D0F0xE4_PIF_0012_ADDRESS),
Pcie
);
D0F0xE4_PIF_0012.Field.PllPowerStateInOff = PifPowerStateL0;
D0F0xE4_PIF_0012.Field.PllPowerStateInTxs2 = PifPowerStateL0;
for (Pif = 0; Pif < Wrapper->NumberOfPIFs; Pif++) {
PcieRegisterWrite (
Wrapper,
PIF_SPACE (Wrapper->WrapId, Pif, D0F0xE4_PIF_0012_ADDRESS),
D0F0xE4_PIF_0012.Value,
TRUE,
Pcie
);
PcieRegisterWrite (
Wrapper,
PIF_SPACE (Wrapper->WrapId, Pif, D0F0xE4_PIF_0012_ADDRESS + 1),
D0F0xE4_PIF_0012.Value,
TRUE,
Pcie
);
}
WrapperInfo->AnyDevFailPllpdnb = TRUE;
}
if (WrapperInfo->MinAspmL1ExitLatency < WrapperInfo->ActualL1Latency) {
WrapperInfo->DisableL1OnWrapper = TRUE;
}
ActualL1Latency = WrapperInfo->ActualL1Latency >> 1;
WrapperInfo->L1ExitLatencyValue = 1;
while (ActualL1Latency != 0) {
ActualL1Latency = ActualL1Latency >> 1;
WrapperInfo->L1ExitLatencyValue++;
}
return (AGESA_SUCCESS);
}
/**
* Pcie TxPreset loading sequence
*
*
* @param[in] Wrapper Pointer to wrapper configuration descriptor
* @param[in] Pcie Pointer to global PCIe configuration
*/
VOID
STATIC
PcieEarlyWrapperTxPresetLoadingSequenceCZ (
IN PCIe_WRAPPER_CONFIG *Wrapper,
IN PCIe_PLATFORM_CONFIG *Pcie
)
{
UINT8 Pif;
UINT8 CoreId;
IDS_HDT_CONSOLE (GNB_TRACE, "PcieEarlyWrapperTxPresetLoadingSequenceCZ Enter\n");
// Step 1: program TX preset value of PCIE_WRAPPER:PSX80/81_WRP_BIF_LANE_EQUALIZATION_CNTL to 0x7 ( from h/w default 0xF )
PcieRegisterRMW (
Wrapper,
WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_0050_ADDRESS),
D0F0xE4_WRAP_0050_StrapBifPcieLaneEqCntlDsPortTxPreset_MASK | D0F0xE4_WRAP_0050_StrapBifPcieLaneEqCntlUsPortTxPreset_MASK,
(7 << D0F0xE4_WRAP_0050_StrapBifPcieLaneEqCntlDsPortTxPreset_OFFSET) | (7 << D0F0xE4_WRAP_0050_StrapBifPcieLaneEqCntlUsPortTxPreset_OFFSET),
TRUE,
Pcie
);
IDS_OPTION_CALLOUT (IDS_CALLOUT_GNB_BEFORE_TXPRESET_LOADING, Pcie, (AMD_CONFIG_PARAMS *)Pcie->StdHeader);
for (CoreId = Wrapper->StartPcieCoreId; CoreId <= Wrapper->EndPcieCoreId; CoreId++) {
// Step 2: program TOGGLESTRAP bit of PCIE_WRAPPER:PSX80/81_BIF_SWRST_COMMAND_1 to 0x1
PcieRegisterRMW (
Wrapper,
CORE_SPACE (CoreId, D0F0xE4_CORE_0103_ADDRESS),
D0F0xE4_CORE_0103_Togglestrap_MASK,
(1 << D0F0xE4_CORE_0103_Togglestrap_OFFSET),
TRUE,
Pcie
);
// Wait for ~50ns
GnbLibStall (1, (AMD_CONFIG_PARAMS *)Pcie->StdHeader);
// program TOGGLESTRAP bit of PCIE_WRAPPER:PSX80/81_BIF_SWRST_COMMAND_1 to 0x0
PcieRegisterRMW (
Wrapper,
CORE_SPACE (CoreId, D0F0xE4_CORE_0103_ADDRESS),
D0F0xE4_CORE_0103_Togglestrap_MASK,
(0 << D0F0xE4_CORE_0103_Togglestrap_OFFSET),
TRUE,
Pcie
);
}
for (Pif = 0; Pif < Wrapper->NumberOfPIFs; Pif++) {
// Step 3: program TXPWR_IN_INIT bit of PCIE_WRAPPER:PSX80/81_PIF0_TX_CTRL to 0x1 ( from h/w default 0x2 )
// program RXPWR_IN_INIT bit of PCIE_WRAPPER:PSX80/81_PIF0_RX_CTRL to 0x1 ( from h/w default 0x2 )
PcieRegisterRMW (
Wrapper,
PIF_SPACE (Wrapper->WrapId, Pif, D0F0xE4_PIF_0008_ADDRESS),
D0F0xE4_PIF_0008_TxpwrInInit_MASK,
(1 << D0F0xE4_PIF_0008_TxpwrInInit_OFFSET),
TRUE,
Pcie
);
PcieRegisterRMW (
Wrapper,
PIF_SPACE (Wrapper->WrapId, Pif, D0F0xE4_PIF_000A_ADDRESS),
D0F0xE4_PIF_000A_RxpwrInInit_MASK,
(1 << D0F0xE4_PIF_000A_RxpwrInInit_OFFSET),
TRUE,
Pcie
);
// Wait for ~1ns
GnbLibStall (1, (AMD_CONFIG_PARAMS *)Pcie->StdHeader);
//Step 5: program TXPWR_IN_INIT bit of PCIE_WRAPPER:PSX80/81_PIF0_TX_CTRL back to 0x2
// program RXPWR_IN_INIT bit of PCIE_WRAPPER:PSX80/81_PIF0_RX_CTRL back to 0x2
PcieRegisterRMW (
Wrapper,
PIF_SPACE (Wrapper->WrapId, Pif, D0F0xE4_PIF_0008_ADDRESS),
D0F0xE4_PIF_0008_TxpwrInInit_MASK,
(2 << D0F0xE4_PIF_0008_TxpwrInInit_OFFSET),
TRUE,
Pcie
);
PcieRegisterRMW (
Wrapper,
PIF_SPACE (Wrapper->WrapId, Pif, D0F0xE4_PIF_000A_ADDRESS),
D0F0xE4_PIF_000A_RxpwrInInit_MASK,
(2 << D0F0xE4_PIF_000A_RxpwrInInit_OFFSET),
TRUE,
Pcie
);
}
IDS_HDT_CONSOLE (GNB_TRACE, "PcieEarlyWrapperTxPresetLoadingSequenceCZ Exit\n");
}
VOID
STATIC
PcieHwInitPowerGatingCZ (
IN PCIe_WRAPPER_CONFIG *Wrapper,
IN PCIe_PLATFORM_CONFIG *Pcie
)
{
UINT8 Pif;
UINT32 Value;
D0F0xE4_PIF_0004_STRUCT D0F0xE4_PIF_0004;
D0F0xE4_PIF_0008_STRUCT D0F0xE4_PIF_0008;
D0F0xE4_PIF_000A_STRUCT D0F0xE4_PIF_000A;
D0F0xE4_CORE_012A_STRUCT D0F0xE4_CORE_012A;
D0F0xE4_CORE_012C_STRUCT D0F0xE4_CORE_012C;
D0F0xE4_CORE_012D_STRUCT D0F0xE4_CORE_012D;
GNB_BUILD_OPTIONS_CZ *GnbBuildOptionData;
IDS_HDT_CONSOLE (GNB_TRACE, "PcieHwInitPowerGatingCZ Enter\n");
GnbBuildOptionData = GnbLocateHeapBuffer (AMD_GNB_BUILD_OPTIONS_HANDLE, GnbLibGetHeader (Pcie));
ASSERT (GnbBuildOptionData != NULL);
Value = 0x0;
if ((GnbBuildOptionData->CfgPcieHwInitPwerGating & PcieHwInitPwrGatingL1Pg) == PcieHwInitPwrGatingL1Pg) {
Value = 0x1;
}
PcieRegisterWriteField (
Wrapper,
CORE_SPACE (Wrapper->StartPcieCoreId, D0F0xE4_CORE_003D_ADDRESS),
D0F0xE4_CORE_003D_LC_L1_POWER_GATING_EN_OFFSET,
D0F0xE4_CORE_003D_LC_L1_POWER_GATING_EN_WIDTH,
Value,
TRUE,
Pcie
);
for (Pif = 0; Pif < Wrapper->NumberOfPIFs; Pif++) {
D0F0xE4_PIF_0008.Value = PcieRegisterRead (
Wrapper,
PIF_SPACE (Wrapper->WrapId, Pif, D0F0xE4_PIF_0008_ADDRESS),
Pcie
);
D0F0xE4_PIF_000A.Value = PcieRegisterRead (
Wrapper,
PIF_SPACE (Wrapper->WrapId, Pif, D0F0xE4_PIF_000A_ADDRESS),
Pcie
);
D0F0xE4_PIF_0008.Field.TxpwrInOff = GnbBuildOptionData->CfgPcieTxpwrInOff;
D0F0xE4_PIF_000A.Field.RxpwrInOff = GnbBuildOptionData->CfgPcieRxpwrInOff;
D0F0xE4_PIF_000A.Field.RxEiDetInPs2Degrade = 0x0;
D0F0xE4_PIF_0008.Field.TxpwrGatingInL1 = 0x0;
D0F0xE4_PIF_000A.Field.RxpwrGatingInL1 = 0x0;
if ((GnbBuildOptionData->CfgPcieHwInitPwerGating & PcieHwInitPwrGatingL1Pg) == PcieHwInitPwrGatingL1Pg) {
D0F0xE4_PIF_0008.Field.TxpwrGatingInL1 = 0x1;
D0F0xE4_PIF_000A.Field.RxpwrGatingInL1 = 0x1;
}
D0F0xE4_PIF_0008.Field.TxpwrGatingInUnused = 0x0;
D0F0xE4_PIF_000A.Field.RxpwrGatingInUnused = 0x0;
if ((GnbBuildOptionData->CfgPcieHwInitPwerGating & PcieHwInitPwrGatingOffPg) == PcieHwInitPwrGatingOffPg) {
D0F0xE4_PIF_0008.Field.TxpwrGatingInUnused = 0x1;
D0F0xE4_PIF_000A.Field.RxpwrGatingInUnused = 0x1;
}
PcieRegisterWrite (
Wrapper,
PIF_SPACE (Wrapper->WrapId, Pif, D0F0xE4_PIF_0008_ADDRESS),
D0F0xE4_PIF_0008.Value,
TRUE,
Pcie
);
PcieRegisterWrite (
Wrapper,
PIF_SPACE (Wrapper->WrapId, Pif, D0F0xE4_PIF_000A_ADDRESS),
D0F0xE4_PIF_000A.Value,
TRUE,
Pcie
);
D0F0xE4_PIF_0004.Value = PcieRegisterRead (
Wrapper,
PIF_SPACE (Wrapper->WrapId, Pif, D0F0xE4_PIF_0004_ADDRESS),
Pcie
);
D0F0xE4_PIF_0004.Field.PifDegradePwrPllMode = 0x0;
PcieRegisterWrite (
Wrapper,
PIF_SPACE (Wrapper->WrapId, Pif, D0F0xE4_PIF_0004_ADDRESS),
D0F0xE4_PIF_0004.Value,
TRUE,
Pcie
);
}
D0F0xE4_CORE_012A.Value = PcieRegisterRead (
Wrapper,
CORE_SPACE (Wrapper->StartPcieCoreId, D0F0xE4_CORE_012A_ADDRESS),
Pcie
);
D0F0xE4_CORE_012C.Value = PcieRegisterRead (
Wrapper,
CORE_SPACE (Wrapper->StartPcieCoreId, D0F0xE4_CORE_012C_ADDRESS),
Pcie
);
D0F0xE4_CORE_012D.Value = PcieRegisterRead (
Wrapper,
CORE_SPACE (Wrapper->StartPcieCoreId, D0F0xE4_CORE_012D_ADDRESS),
Pcie
);
D0F0xE4_CORE_012A.Field.LMLaneDegrade0 = 1;
D0F0xE4_CORE_012A.Field.LMLaneDegrade1 = 1;
D0F0xE4_CORE_012A.Field.LMLaneDegrade2 = 1;
D0F0xE4_CORE_012A.Field.LMLaneDegrade3 = 1;
D0F0xE4_CORE_012C.Field.LMLaneUnused0 = 1;
D0F0xE4_CORE_012C.Field.LMLaneUnused1 = 1;
D0F0xE4_CORE_012C.Field.LMLaneUnused2 = 1;
D0F0xE4_CORE_012D.Field.LMLaneUnused3 = 1;
PcieRegisterWrite (
Wrapper,
CORE_SPACE (Wrapper->StartPcieCoreId, D0F0xE4_CORE_012A_ADDRESS),
D0F0xE4_CORE_012A.Value,
TRUE,
Pcie
);
PcieRegisterWrite (
Wrapper,
CORE_SPACE (Wrapper->StartPcieCoreId, D0F0xE4_CORE_012C_ADDRESS),
D0F0xE4_CORE_012C.Value,
TRUE,
Pcie
);
PcieRegisterWrite (
Wrapper,
CORE_SPACE (Wrapper->StartPcieCoreId, D0F0xE4_CORE_012D_ADDRESS),
D0F0xE4_CORE_012D.Value,
TRUE,
Pcie
);
IDS_HDT_CONSOLE (GNB_TRACE, "PcieHwInitPowerGatingCZ Exit\n");
}
