static void
mainbus_attach(device_t parent, device_t self, void *aux)
{
struct mainbus_attach_args ma;
const struct mainbusdev *md;
#if defined(PCI_NETBSD_ENABLE_IDE) || defined(PCI_NETBSD_CONFIGURE)
struct malta_config *mcp = &malta_configuration;
pci_chipset_tag_t pc = &mcp->mc_pc;
#endif
#if defined(PCI_NETBSD_ENABLE_IDE)
pcitag_t idetag;
pcireg_t idetim;
#endif
mainbus_found = true;
printf("\n");
#if defined(PCI_NETBSD_CONFIGURE)
struct mips_cache_info * const mci = &mips_cache_info;
struct extent *ioext = extent_create("pciio", 0x00001000, 0x0000efff,
NULL, 0, EX_NOWAIT);
struct extent *memext = extent_create("pcimem", MALTA_PCIMEM1_BASE,
MALTA_PCIMEM1_BASE + MALTA_PCIMEM1_SIZE,
NULL, 0, EX_NOWAIT);
pci_configure_bus(pc, ioext, memext, NULL, 0, mci->mci_dcache_align);
extent_destroy(ioext);
extent_destroy(memext);
#endif /* PCI_NETBSD_CONFIGURE */
#if defined(PCI_NETBSD_ENABLE_IDE)
/*
* Perhaps PMON has not enabled the IDE controller. Easy to
* fix -- just set the ENABLE bits for each channel in the
* IDETIM register. Just clear all the bits for the channel
* except for the ENABLE bits -- the `pciide' driver will
* properly configure it later.
*/
idetim = 0;
if (PCI_NETBSD_ENABLE_IDE & 0x01)
idetim = PIIX_IDETIM_SET(idetim, PIIX_IDETIM_IDE, 0);
if (PCI_NETBSD_ENABLE_IDE & 0x02)
idetim = PIIX_IDETIM_SET(idetim, PIIX_IDETIM_IDE, 1);
/* pciide0 is pci device 10, function 1 */
idetag = pci_make_tag(pc, 0, 10, 1);
pci_conf_write(pc, idetag, PIIX_IDETIM, idetim);
#endif
for (md = mainbusdevs; md->md_name != NULL; md++) {
ma.ma_name = md->md_name;
ma.ma_addr = md->md_addr;
ma.ma_intr = md->md_intr;
(void) config_found_sm_loc(self, "mainbus", NULL, &ma,
mainbus_print, mainbus_submatch);
}
}
/* setup DTE, PPE, IE and TIME field based on PIO mode */
static u_int32_t
piix_setup_idetim_drvs(struct ata_drive_datas *drvp)
{
u_int32_t ret = 0;
struct ata_channel *chp = drvp->chnl_softc;
u_int8_t channel = chp->ch_channel;
u_int8_t drive = drvp->drive;
/*
* If drive is using UDMA, timings setups are independent
* So just check DMA and PIO here.
*/
if (drvp->drive_flags & ATA_DRIVE_DMA) {
/* if mode = DMA mode 0, use compatible timings */
if ((drvp->drive_flags & ATA_DRIVE_DMA) &&
drvp->DMA_mode == 0) {
drvp->PIO_mode = 0;
return ret;
}
ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_TIME(drive), channel);
/*
* PIO and DMA timings are the same, use fast timings for PIO
* too, else use compat timings.
*/
if ((piix_isp_pio[drvp->PIO_mode] !=
piix_isp_dma[drvp->DMA_mode]) ||
(piix_rtc_pio[drvp->PIO_mode] !=
piix_rtc_dma[drvp->DMA_mode]))
drvp->PIO_mode = 0;
/* if PIO mode <= 2, use compat timings for PIO */
if (drvp->PIO_mode <= 2) {
ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_DTE(drive),
channel);
return ret;
}
}
/*
* Now setup PIO modes. If mode < 2, use compat timings.
* Else enable fast timings. Enable IORDY and prefetch/post
* if PIO mode >= 3.
*/
if (drvp->PIO_mode < 2)
return ret;
ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_TIME(drive), channel);
if (drvp->PIO_mode >= 3) {
ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_IE(drive), channel);
ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_PPE(drive), channel);
}
return ret;
}
/* setup ISP and RTC fields, based on mode */
static u_int32_t
piix_setup_idetim_timings(u_int8_t mode, u_int8_t dma, u_int8_t channel)
{
if (dma)
return PIIX_IDETIM_SET(0,
PIIX_IDETIM_ISP_SET(piix_isp_dma[mode]) |
PIIX_IDETIM_RTC_SET(piix_rtc_dma[mode]),
channel);
else
return PIIX_IDETIM_SET(0,
PIIX_IDETIM_ISP_SET(piix_isp_pio[mode]) |
PIIX_IDETIM_RTC_SET(piix_rtc_pio[mode]),
channel);
}
static void
piix3_4_setup_channel(struct wdc_channel *chp)
{
struct ata_drive_datas *drvp;
u_int32_t oidetim, idetim, sidetim, udmareg, ideconf, idedma_ctl;
struct pciide_channel *cp = (struct pciide_channel*)chp;
struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.ch_wdc;
struct wdc_softc *wdc = &sc->sc_wdcdev;
int drive;
int channel = chp->ch_channel;
oidetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM);
sidetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM);
udmareg = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG);
ideconf = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_CONFIG);
idetim = PIIX_IDETIM_CLEAR(oidetim, 0xffff, channel);
sidetim &= ~(PIIX_SIDETIM_ISP_MASK(channel) |
PIIX_SIDETIM_RTC_MASK(channel));
idedma_ctl = 0;
/* set up new idetim: Enable IDE registers decode */
idetim = PIIX_IDETIM_SET(idetim, PIIX_IDETIM_IDE, channel);
/* setup DMA if needed */
pciide_channel_dma_setup(cp);
for (drive = 0; drive < 2; drive++) {
udmareg &= ~(PIIX_UDMACTL_DRV_EN(channel, drive) |
PIIX_UDMATIM_SET(0x3, channel, drive));
drvp = &chp->ch_drive[drive];
/* If no drive, skip */
if ((drvp->drive_flags & DRIVE) == 0)
continue;
if (((drvp->drive_flags & DRIVE_DMA) == 0 &&
(drvp->drive_flags & DRIVE_UDMA) == 0))
goto pio;
if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE ||
sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AB_IDE ||
sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BA_IDE ||
sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BAM_IDE ||
sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_1 ||
sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_2 ||
sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DB_IDE ||
sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DBM_IDE ||
sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801EB_IDE ||
sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_6300ESB_IDE) {
ideconf |= PIIX_CONFIG_PINGPONG;
}
if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BA_IDE ||
sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BAM_IDE ||
sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_1 ||
sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_2 ||
sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DB_IDE ||
sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DBM_IDE ||
sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801EB_IDE ||
sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_6300ESB_IDE) {
/* setup Ultra/100 */
if (drvp->UDMA_mode > 2 &&
(ideconf & PIIX_CONFIG_CR(channel, drive)) == 0)
drvp->UDMA_mode = 2;
if (drvp->UDMA_mode > 4) {
ideconf |= PIIX_CONFIG_UDMA100(channel, drive);
} else {
ideconf &= ~PIIX_CONFIG_UDMA100(channel, drive);
if (drvp->UDMA_mode > 2) {
ideconf |= PIIX_CONFIG_UDMA66(channel,
drive);
} else {
ideconf &= ~PIIX_CONFIG_UDMA66(channel,
drive);
}
}
}
if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE) {
/* setup Ultra/66 */
if (drvp->UDMA_mode > 2 &&
(ideconf & PIIX_CONFIG_CR(channel, drive)) == 0)
drvp->UDMA_mode = 2;
if (drvp->UDMA_mode > 2)
ideconf |= PIIX_CONFIG_UDMA66(channel, drive);
else
ideconf &= ~PIIX_CONFIG_UDMA66(channel, drive);
}
if ((wdc->cap & WDC_CAPABILITY_UDMA) &&
(drvp->drive_flags & DRIVE_UDMA)) {
/* use Ultra/DMA */
drvp->drive_flags &= ~DRIVE_DMA;
udmareg |= PIIX_UDMACTL_DRV_EN( channel, drive);
udmareg |= PIIX_UDMATIM_SET(
piix4_sct_udma[drvp->UDMA_mode], channel, drive);
} else {
/* use Multiword DMA */
drvp->drive_flags &= ~DRIVE_UDMA;
if (drive == 0) {
idetim |= piix_setup_idetim_timings(
drvp->DMA_mode, 1, channel);
} else {
sidetim |= piix_setup_sidetim_timings(
drvp->DMA_mode, 1, channel);
idetim =PIIX_IDETIM_SET(idetim,
PIIX_IDETIM_SITRE, channel);
}
}
idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive);
pio: /* use PIO mode */
idetim |= piix_setup_idetim_drvs(drvp);
if (drive == 0) {
idetim |= piix_setup_idetim_timings(
drvp->PIO_mode, 0, channel);
} else {
sidetim |= piix_setup_sidetim_timings(
drvp->PIO_mode, 0, channel);
idetim =PIIX_IDETIM_SET(idetim,
PIIX_IDETIM_SITRE, channel);
}
}
if (idedma_ctl != 0) {
/* Add software bits in status register */
bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0,
idedma_ctl);
}
pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_IDETIM, idetim);
pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM, sidetim);
pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG, udmareg);
pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_CONFIG, ideconf);
}
static void
piix_setup_channel(struct wdc_channel *chp)
{
u_int8_t mode[2], drive;
u_int32_t oidetim, idetim, idedma_ctl;
struct pciide_channel *cp = (struct pciide_channel*)chp;
struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.ch_wdc;
struct ata_drive_datas *drvp = cp->wdc_channel.ch_drive;
oidetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM);
idetim = PIIX_IDETIM_CLEAR(oidetim, 0xffff, chp->ch_channel);
idedma_ctl = 0;
/* set up new idetim: Enable IDE registers decode */
idetim = PIIX_IDETIM_SET(idetim, PIIX_IDETIM_IDE,
chp->ch_channel);
/* setup DMA */
pciide_channel_dma_setup(cp);
/*
* Here we have to mess up with drives mode: PIIX can't have
* different timings for master and slave drives.
* We need to find the best combination.
*/
/* If both drives supports DMA, take the lower mode */
if ((drvp[0].drive_flags & DRIVE_DMA) &&
(drvp[1].drive_flags & DRIVE_DMA)) {
mode[0] = mode[1] =
min(drvp[0].DMA_mode, drvp[1].DMA_mode);
drvp[0].DMA_mode = mode[0];
drvp[1].DMA_mode = mode[1];
goto ok;
}
/*
* If only one drive supports DMA, use its mode, and
* put the other one in PIO mode 0 if mode not compatible
*/
if (drvp[0].drive_flags & DRIVE_DMA) {
mode[0] = drvp[0].DMA_mode;
mode[1] = drvp[1].PIO_mode;
if (piix_isp_pio[mode[1]] != piix_isp_dma[mode[0]] ||
piix_rtc_pio[mode[1]] != piix_rtc_dma[mode[0]])
mode[1] = drvp[1].PIO_mode = 0;
goto ok;
}
if (drvp[1].drive_flags & DRIVE_DMA) {
mode[1] = drvp[1].DMA_mode;
mode[0] = drvp[0].PIO_mode;
if (piix_isp_pio[mode[0]] != piix_isp_dma[mode[1]] ||
piix_rtc_pio[mode[0]] != piix_rtc_dma[mode[1]])
mode[0] = drvp[0].PIO_mode = 0;
goto ok;
}
/*
* If both drives are not DMA, takes the lower mode, unless
* one of them is PIO mode < 2
*/
if (drvp[0].PIO_mode < 2) {
mode[0] = drvp[0].PIO_mode = 0;
mode[1] = drvp[1].PIO_mode;
} else if (drvp[1].PIO_mode < 2) {
mode[1] = drvp[1].PIO_mode = 0;
mode[0] = drvp[0].PIO_mode;
} else {
mode[0] = mode[1] =
min(drvp[1].PIO_mode, drvp[0].PIO_mode);
drvp[0].PIO_mode = mode[0];
drvp[1].PIO_mode = mode[1];
}
ok: /* The modes are setup */
for (drive = 0; drive < 2; drive++) {
if (drvp[drive].drive_flags & DRIVE_DMA) {
idetim |= piix_setup_idetim_timings(
mode[drive], 1, chp->ch_channel);
goto end;
}
}
/* If we are there, none of the drives are DMA */
if (mode[0] >= 2)
idetim |= piix_setup_idetim_timings(
mode[0], 0, chp->ch_channel);
else
idetim |= piix_setup_idetim_timings(
mode[1], 0, chp->ch_channel);
end: /*
* timing mode is now set up in the controller. Enable
* it per-drive
*/
for (drive = 0; drive < 2; drive++) {
/* If no drive, skip */
if ((drvp[drive].drive_flags & DRIVE) == 0)
continue;
idetim |= piix_setup_idetim_drvs(&drvp[drive]);
if (drvp[drive].drive_flags & DRIVE_DMA)
idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive);
}
if (idedma_ctl != 0) {
/* Add software bits in status register */
bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0,
idedma_ctl);
}
pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_IDETIM, idetim);
}
static void
piix_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa)
{
struct pciide_channel *cp;
int channel;
u_int32_t idetim;
bus_size_t cmdsize, ctlsize;
if (pciide_chipen(sc, pa) == 0)
return;
aprint_normal("%s: bus-master DMA support present",
sc->sc_wdcdev.sc_dev.dv_xname);
pciide_mapreg_dma(sc, pa);
aprint_normal("\n");
sc->sc_wdcdev.cap |= WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 |
WDC_CAPABILITY_MODE;
if (sc->sc_dma_ok) {
sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK;
sc->sc_wdcdev.irqack = pciide_irqack;
switch(sc->sc_pp->ide_product) {
case PCI_PRODUCT_INTEL_82371AB_IDE:
case PCI_PRODUCT_INTEL_82440MX_IDE:
case PCI_PRODUCT_INTEL_82801AA_IDE:
case PCI_PRODUCT_INTEL_82801AB_IDE:
case PCI_PRODUCT_INTEL_82801BA_IDE:
case PCI_PRODUCT_INTEL_82801BAM_IDE:
case PCI_PRODUCT_INTEL_82801CA_IDE_1:
case PCI_PRODUCT_INTEL_82801CA_IDE_2:
case PCI_PRODUCT_INTEL_82801DB_IDE:
case PCI_PRODUCT_INTEL_82801DBM_IDE:
case PCI_PRODUCT_INTEL_82801EB_IDE:
case PCI_PRODUCT_INTEL_6300ESB_IDE:
sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA;
}
}
sc->sc_wdcdev.PIO_cap = 4;
sc->sc_wdcdev.DMA_cap = 2;
switch(sc->sc_pp->ide_product) {
case PCI_PRODUCT_INTEL_82801AA_IDE:
sc->sc_wdcdev.UDMA_cap = 4;
break;
case PCI_PRODUCT_INTEL_82801BA_IDE:
case PCI_PRODUCT_INTEL_82801BAM_IDE:
case PCI_PRODUCT_INTEL_82801CA_IDE_1:
case PCI_PRODUCT_INTEL_82801CA_IDE_2:
case PCI_PRODUCT_INTEL_82801DB_IDE:
case PCI_PRODUCT_INTEL_82801DBM_IDE:
case PCI_PRODUCT_INTEL_82801EB_IDE:
case PCI_PRODUCT_INTEL_6300ESB_IDE:
sc->sc_wdcdev.UDMA_cap = 5;
break;
default:
sc->sc_wdcdev.UDMA_cap = 2;
}
if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82371FB_IDE)
sc->sc_wdcdev.set_modes = piix_setup_channel;
else
sc->sc_wdcdev.set_modes = piix3_4_setup_channel;
sc->sc_wdcdev.channels = sc->wdc_chanarray;
sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS;
WDCDEBUG_PRINT(("piix_setup_chip: old idetim=0x%x",
pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM)),
DEBUG_PROBE);
if (sc->sc_pp->ide_product != PCI_PRODUCT_INTEL_82371FB_IDE) {
WDCDEBUG_PRINT((", sidetim=0x%x",
pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM)),
DEBUG_PROBE);
if (sc->sc_wdcdev.cap & WDC_CAPABILITY_UDMA) {
WDCDEBUG_PRINT((", udamreg 0x%x",
pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG)),
DEBUG_PROBE);
}
if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE ||
sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AB_IDE ||
sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BA_IDE ||
sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BAM_IDE ||
sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_1 ||
sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_2 ||
sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DB_IDE ||
sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DBM_IDE ||
sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801EB_IDE ||
sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_6300ESB_IDE) {
WDCDEBUG_PRINT((", IDE_CONTROL 0x%x",
pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_CONFIG)),
DEBUG_PROBE);
}
}
WDCDEBUG_PRINT(("\n"), DEBUG_PROBE);
for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) {
cp = &sc->pciide_channels[channel];
/* PIIX is compat-only */
if (pciide_chansetup(sc, channel, 0) == 0)
continue;
idetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM);
if ((PIIX_IDETIM_READ(idetim, channel) &
PIIX_IDETIM_IDE) == 0) {
#if 1
aprint_normal("%s: %s channel ignored (disabled)\n",
sc->sc_wdcdev.sc_dev.dv_xname, cp->name);
cp->wdc_channel.ch_flags |= WDCF_DISABLED;
continue;
#else
pcireg_t interface;
idetim = PIIX_IDETIM_SET(idetim, PIIX_IDETIM_IDE,
channel);
pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_IDETIM,
idetim);
interface = PCI_INTERFACE(pci_conf_read(sc->sc_pc,
sc->sc_tag, PCI_CLASS_REG));
aprint_normal("channel %d idetim=%08x interface=%02x\n",
channel, idetim, interface);
#endif
}
/* PIIX are compat-only pciide devices */
pciide_mapchan(pa, cp, 0, &cmdsize, &ctlsize, pciide_pci_intr);
}
WDCDEBUG_PRINT(("piix_setup_chip: idetim=0x%x",
pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM)),
DEBUG_PROBE);
if (sc->sc_pp->ide_product != PCI_PRODUCT_INTEL_82371FB_IDE) {
WDCDEBUG_PRINT((", sidetim=0x%x",
pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM)),
DEBUG_PROBE);
if (sc->sc_wdcdev.cap & WDC_CAPABILITY_UDMA) {
WDCDEBUG_PRINT((", udamreg 0x%x",
pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG)),
DEBUG_PROBE);
}
if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE ||
sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AB_IDE ||
sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BA_IDE ||
sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BAM_IDE ||
sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_1 ||
sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_2 ||
sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DB_IDE ||
sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DBM_IDE ||
sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801EB_IDE ||
sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_6300ESB_IDE) {
WDCDEBUG_PRINT((", IDE_CONTROL 0x%x",
pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_CONFIG)),
DEBUG_PROBE);
}
}
WDCDEBUG_PRINT(("\n"), DEBUG_PROBE);
}
static void
piix_chip_map(struct pciide_softc *sc, const struct pci_attach_args *pa)
{
struct pciide_channel *cp;
int channel;
u_int32_t idetim;
pcireg_t interface = PCI_INTERFACE(pa->pa_class);
if (pciide_chipen(sc, pa) == 0)
return;
aprint_verbose_dev(sc->sc_wdcdev.sc_atac.atac_dev,
"bus-master DMA support present");
pciide_mapreg_dma(sc, pa);
aprint_verbose("\n");
sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DATA16 | ATAC_CAP_DATA32;
if (sc->sc_dma_ok) {
sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA;
sc->sc_wdcdev.irqack = pciide_irqack;
/* Do all revisions require DMA alignment workaround? */
sc->sc_wdcdev.dma_init = piix_dma_init;
switch(sc->sc_pp->ide_product) {
case PCI_PRODUCT_INTEL_82371AB_IDE:
case PCI_PRODUCT_INTEL_82440MX_IDE:
case PCI_PRODUCT_INTEL_82801AA_IDE:
case PCI_PRODUCT_INTEL_82801AB_IDE:
case PCI_PRODUCT_INTEL_82801BA_IDE:
case PCI_PRODUCT_INTEL_82801BAM_IDE:
case PCI_PRODUCT_INTEL_82801CA_IDE_1:
case PCI_PRODUCT_INTEL_82801CA_IDE_2:
case PCI_PRODUCT_INTEL_82801DB_IDE:
case PCI_PRODUCT_INTEL_82801DBM_IDE:
case PCI_PRODUCT_INTEL_82801EB_IDE:
case PCI_PRODUCT_INTEL_6300ESB_IDE:
case PCI_PRODUCT_INTEL_82801FB_IDE:
case PCI_PRODUCT_INTEL_82801G_IDE:
case PCI_PRODUCT_INTEL_82801HBM_IDE:
sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_UDMA;
}
}
sc->sc_wdcdev.sc_atac.atac_pio_cap = 4;
sc->sc_wdcdev.sc_atac.atac_dma_cap = 2;
switch(sc->sc_pp->ide_product) {
case PCI_PRODUCT_INTEL_82801AA_IDE:
sc->sc_wdcdev.sc_atac.atac_udma_cap = 4;
break;
case PCI_PRODUCT_INTEL_82801BA_IDE:
case PCI_PRODUCT_INTEL_82801BAM_IDE:
case PCI_PRODUCT_INTEL_82801CA_IDE_1:
case PCI_PRODUCT_INTEL_82801CA_IDE_2:
case PCI_PRODUCT_INTEL_82801DB_IDE:
case PCI_PRODUCT_INTEL_82801DBM_IDE:
case PCI_PRODUCT_INTEL_82801EB_IDE:
case PCI_PRODUCT_INTEL_6300ESB_IDE:
case PCI_PRODUCT_INTEL_82801FB_IDE:
case PCI_PRODUCT_INTEL_82801G_IDE:
case PCI_PRODUCT_INTEL_82801HBM_IDE:
sc->sc_wdcdev.sc_atac.atac_udma_cap = 5;
break;
default:
sc->sc_wdcdev.sc_atac.atac_udma_cap = 2;
}
if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82371FB_IDE)
sc->sc_wdcdev.sc_atac.atac_set_modes = piix_setup_channel;
else
sc->sc_wdcdev.sc_atac.atac_set_modes = piix3_4_setup_channel;
sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray;
sc->sc_wdcdev.sc_atac.atac_nchannels = PCIIDE_NUM_CHANNELS;
sc->sc_wdcdev.wdc_maxdrives = 2;
ATADEBUG_PRINT(("piix_setup_chip: old idetim=0x%x",
pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM)),
DEBUG_PROBE);
if (sc->sc_pp->ide_product != PCI_PRODUCT_INTEL_82371FB_IDE) {
ATADEBUG_PRINT((", sidetim=0x%x",
pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM)),
DEBUG_PROBE);
if (sc->sc_wdcdev.sc_atac.atac_cap & ATAC_CAP_UDMA) {
ATADEBUG_PRINT((", udamreg 0x%x",
pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG)),
DEBUG_PROBE);
}
if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE ||
sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AB_IDE ||
sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BA_IDE ||
sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BAM_IDE ||
sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_1 ||
sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_2 ||
sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DB_IDE ||
sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DBM_IDE ||
sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801EB_IDE ||
sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801FB_IDE ||
sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_6300ESB_IDE ||
sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801G_IDE ||
sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801HBM_IDE) {
ATADEBUG_PRINT((", IDE_CONTROL 0x%x",
pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_CONFIG)),
DEBUG_PROBE);
}
}
ATADEBUG_PRINT(("\n"), DEBUG_PROBE);
wdc_allocate_regs(&sc->sc_wdcdev);
for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels;
channel++) {
cp = &sc->pciide_channels[channel];
if (pciide_chansetup(sc, channel, interface) == 0)
continue;
idetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM);
if ((PIIX_IDETIM_READ(idetim, channel) &
PIIX_IDETIM_IDE) == 0) {
#if 1
aprint_normal_dev(sc->sc_wdcdev.sc_atac.atac_dev,
"%s channel ignored (disabled)\n", cp->name);
cp->ata_channel.ch_flags |= ATACH_DISABLED;
continue;
#else
pcireg_t interface;
idetim = PIIX_IDETIM_SET(idetim, PIIX_IDETIM_IDE,
channel);
pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_IDETIM,
idetim);
interface = PCI_INTERFACE(pci_conf_read(sc->sc_pc,
sc->sc_tag, PCI_CLASS_REG));
aprint_normal("channel %d idetim=%08x interface=%02x\n",
channel, idetim, interface);
#endif
}
pciide_mapchan(pa, cp, interface, pciide_pci_intr);
}
ATADEBUG_PRINT(("piix_setup_chip: idetim=0x%x",
pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM)),
DEBUG_PROBE);
if (sc->sc_pp->ide_product != PCI_PRODUCT_INTEL_82371FB_IDE) {
ATADEBUG_PRINT((", sidetim=0x%x",
pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM)),
DEBUG_PROBE);
if (sc->sc_wdcdev.sc_atac.atac_cap & ATAC_CAP_UDMA) {
ATADEBUG_PRINT((", udamreg 0x%x",
pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG)),
DEBUG_PROBE);
}
if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE ||
sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AB_IDE ||
sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BA_IDE ||
sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BAM_IDE ||
sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_1 ||
sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_2 ||
sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DB_IDE ||
sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DBM_IDE ||
sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801EB_IDE ||
sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801FB_IDE ||
sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_6300ESB_IDE ||
sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801G_IDE ||
sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801HBM_IDE) {
ATADEBUG_PRINT((", IDE_CONTROL 0x%x",
pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_CONFIG)),
DEBUG_PROBE);
}
}
ATADEBUG_PRINT(("\n"), DEBUG_PROBE);
}
