Пример #1
0
/*
 * get_clocks() fills in gd->cpu_clock and gd->bus_clk
 */
int get_clocks(void)
{
	volatile ccm_t *ccm = (volatile ccm_t *)MMAP_CCM;
	volatile pll_t *pll = (volatile pll_t *)MMAP_PLL;
	volatile u8 *cpld = (volatile u8 *)(CFG_CS2_BASE + 3);
	volatile u8 *fpga = (volatile u8 *)(CFG_CS3_BASE + 14);
	int pllmult_nopci[] = { 20, 10, 24, 18, 12, 6, 16, 8 };
	int pllmult_pci[] = { 12, 6, 16, 8 };
	int vco, bPci, temp, fbtemp, pcrvalue;
	int *pPllmult = NULL;
	u16 fbpll_mask;
	u8 cpldmode;

	/* To determine PCI is present or not */
	if (((ccm->ccr & CCM_CCR_360_FBCONFIG_MASK) == 0x00e0) ||
	    ((ccm->ccr & CCM_CCR_360_FBCONFIG_MASK) == 0x0060)) {
		pPllmult = &pllmult_pci[0];
		fbpll_mask = 3;
		bPci = 1;
	} else {
		pPllmult = &pllmult_nopci[0];
		fbpll_mask = 7;
#ifdef CONFIG_PCI
		gd->pci_clk = 0;
#endif
		bPci = 0;
	}

#ifdef CONFIG_M54455EVB
	/* Temporary place here, belongs in board/freescale/... */
	/* Temporary read from CCR- fixed fb issue, must be the same clock
	   as pci or input clock, causing cpld/fpga read inconsistancy */
	fbtemp = pPllmult[ccm->ccr & fbpll_mask];

	/* Break down into small pieces, code still in flex bus */
	pcrvalue = pll->pcr & 0xFFFFF0FF;
	temp = fbtemp - 1;
	pcrvalue |= PLL_PCR_OUTDIV3(temp);

	pll->pcr = pcrvalue;

	cpldmode = *cpld & 0x03;
	if (cpldmode == 0) {
		/* RCON mode */
		vco = pPllmult[ccm->rcon & fbpll_mask] * CFG_INPUT_CLKSRC;

		if ((vco < CLOCK_PLL_FVCO_MIN) || (vco > CLOCK_PLL_FVCO_MAX)) {
			/* invaild range, re-set in PCR */
			int temp = ((pll->pcr & PLL_PCR_OUTDIV2_MASK) >> 4) + 1;
			int i, j, bus;

			j = (pll->pcr & 0xFF000000) >> 24;
			for (i = j; i < 0xFF; i++) {
				vco = i * CFG_INPUT_CLKSRC;
				if (vco >= CLOCK_PLL_FVCO_MIN) {
					bus = vco / temp;
					if (bus <= CLOCK_PLL_FSYS_MIN - MHZ)
						continue;
					else
						break;
				}
			}
			pcrvalue = pll->pcr & 0x00FF00FF;
			fbtemp = ((i - 1) << 8) | ((i - 1) << 12);
			pcrvalue |= ((i << 24) | fbtemp);

			pll->pcr = pcrvalue;
		}
Пример #2
0
/*
 * get_clocks() fills in gd->cpu_clock and gd->bus_clk
 */
int get_clocks(void)
{

    volatile ccm_t *ccm = (volatile ccm_t *)MMAP_CCM;
    volatile pll_t *pll = (volatile pll_t *)MMAP_PLL;
    int pllmult_nopci[] = { 20, 10, 24, 18, 12, 6, 16, 8 };
    int pllmult_pci[] = { 12, 6, 16, 8 };
    int vco = 0, bPci, temp, fbtemp, pcrvalue;
    int *pPllmult = NULL;
    u16 fbpll_mask;

#ifdef CONFIG_M54455EVB
    volatile u8 *cpld = (volatile u8 *)(CONFIG_SYS_CS2_BASE + 3);
#endif
    u8 bootmode;

    /* To determine PCI is present or not */
    if (((ccm->ccr & CCM_CCR_360_FBCONFIG_MASK) == 0x00e0) ||
            ((ccm->ccr & CCM_CCR_360_FBCONFIG_MASK) == 0x0060)) {
        pPllmult = &pllmult_pci[0];
        fbpll_mask = 3;		/* 11b */
        bPci = 1;
    } else {
        pPllmult = &pllmult_nopci[0];
        fbpll_mask = 7;		/* 111b */
#ifdef CONFIG_PCI
        gd->pci_clk = 0;
#endif
        bPci = 0;
    }

#ifdef CONFIG_M54455EVB
    bootmode = (*cpld & 0x03);

    if (bootmode != 3) {
        /* Temporary read from CCR- fixed fb issue, must be the same clock
           as pci or input clock, causing cpld/fpga read inconsistancy */
        fbtemp = pPllmult[ccm->ccr & fbpll_mask];

        /* Break down into small pieces, code still in flex bus */
        pcrvalue = pll->pcr & 0xFFFFF0FF;
        temp = fbtemp - 1;
        pcrvalue |= PLL_PCR_OUTDIV3(temp);

        pll->pcr = pcrvalue;
    }
#endif
#ifdef CONFIG_M54451EVB
    /* No external logic to read the bootmode, hard coded from built */
#ifdef CONFIG_CF_SBF
    bootmode = 3;
#else
    bootmode = 2;

    /* default value is 16 mul, set to 20 mul */
    pcrvalue = (pll->pcr & 0x00FFFFFF) | 0x14000000;
    pll->pcr = pcrvalue;
    while ((pll->psr & PLL_PSR_LOCK) != PLL_PSR_LOCK);
#endif
#endif

    if (bootmode == 0) {
        /* RCON mode */
        vco = pPllmult[ccm->rcon & fbpll_mask] * CONFIG_SYS_INPUT_CLKSRC;

        if ((vco < CLOCK_PLL_FVCO_MIN) || (vco > CLOCK_PLL_FVCO_MAX)) {
            /* invaild range, re-set in PCR */
            int temp = ((pll->pcr & PLL_PCR_OUTDIV2_MASK) >> 4) + 1;
            int i, j, bus;

            j = (pll->pcr & 0xFF000000) >> 24;
            for (i = j; i < 0xFF; i++) {
                vco = i * CONFIG_SYS_INPUT_CLKSRC;
                if (vco >= CLOCK_PLL_FVCO_MIN) {
                    bus = vco / temp;
                    if (bus <= CLOCK_PLL_FSYS_MIN - MHZ)
                        continue;
                    else
                        break;
                }
            }
            pcrvalue = pll->pcr & 0x00FF00FF;
            fbtemp = ((i - 1) << 8) | ((i - 1) << 12);
            pcrvalue |= ((i << 24) | fbtemp);

            pll->pcr = pcrvalue;
        }