CSL_Status pll_sample()
{
CSL_Status status;
volatile int i;
status = PLL_init(&pllObj, CSL_PLL_INST_0);
if (status != CSL_SOK)
{
return status;
}
hPll = (PLL_Handle)(&pllObj);
PLL_reset(hPll);
status = PLL_bypass(hPll);
if (status != CSL_SOK)
{
return status;
}
/* Configure the PLL */
//pConfigInfo = (PLL_Config *)&pllCfg_40MHz;
pConfigInfo = (PLL_Config *)&pllCfg_100MHz;
//pConfigInfo = (PLL_Config *)&pllCfg_100MHz_ExtClk12Mhz;
//pConfigInfo = (PLL_Config *)&pllCfg_120MHz_ExtClk12Mhz;
status = PLL_config (hPll, pConfigInfo);
if (status != CSL_SOK)
{
return(status);
}
status = PLL_getConfig(hPll, &pllCfg1);
if (status != CSL_SOK)
{
return status;
}
/* Wait for PLL to stabilize */
for (i=0; i<100; i++);
status = PLL_enable(hPll);
if (status != CSL_SOK)
{
return status;
}
// set DSP_LDO to 1.05V
//*(volatile ioport unsigned int *)(0x7004) |= 0x0002;
return CSL_SOK;
}
/*..........................................................................*/
void BSP_init(void) {
PLL_Config pllCfg_100MHz = {
0x8BE8U, 0x8000U, 0x0806U, 0x0000U
};
PLL_Obj pllObj;
uint16_t i;
PLL_init(&pllObj, CSL_PLL_INST_0);
PLL_reset(&pllObj);
PLL_config(&pllObj, &pllCfg_100MHz);
QF_zero(); /* clear the QF variables, see NOTE01 */
CSL_SYSCTRL_REGS->PCGCR1 = 0U; /* enable clocks to all peripherals */
CSL_SYSCTRL_REGS->PCGCR2 = 0U;
CSL_SYSCTRL_REGS->EBSR = 0x1800U; /* configure I/O muxing */
CSL_SYSCTRL_REGS->PSRCR = 0x0020U; /* reset all peripherals */
CSL_SYSCTRL_REGS->PRCR = 0x00BFU;
ULED_init(); /* configure the User LEDs... */
IRQ_globalDisable();
IRQ_disableAll(); /* disable all the interrupts */
IRQ_clearAll(); /* clear any pending interrupts */
IRQ_setVecs((uint32_t)&VECSTART); /* set the vector table */
for (i = 1U; i < 32U; ++i) { /* pre-fill the Vector table */
IRQ_plug(i, &illegal_isr); /* with illegal ISR */
}
/* plug in all ISRs into the vector table...*/
// IRQ_plug(TINT_EVENT, &TINT_isr);
// IRQ_plug(RTC_EVENT, &RTC_isr);
/* ... */
if (QS_INIT((void *)0) == 0) { /* initialize the QS software tracing */
Q_ERROR();
}
QS_OBJ_DICTIONARY(&l_TINT_isr);
}
int pll_frequency_setup(unsigned int frequency)
{
CSL_Status status;
status = PLL_init(&pllObj, CSL_PLL_INST_0);
if(CSL_SOK != status)
{
printf("PLL init failed \n");
return (status);
}
hPll = (PLL_Handle)(&pllObj);
PLL_reset(hPll);
/* Configure the PLL for different frequencies */
if ( frequency == 1)
{
pConfigInfo = &pllCfg_1MHz;
printf("\nLL frequency 1 MHz\n");
}
else if ( frequency == 2)
{
pConfigInfo = &pllCfg_2MHz;
printf("\nPLL frequency 2 MHz\n");
}
else if ( frequency == 12)
{
pConfigInfo = &pllCfg_12MHz;
printf("\nPLL frequency 12 MHz\n");
}
else if ( frequency == 40)
{
pConfigInfo = &pllCfg_40MHz;
printf("\nPLL frequency 40 MHz\n");
}
else if ( frequency == 60)
{
pConfigInfo = &pllCfg_60MHz;
printf("\nPLL frequency 60 MHz\n");
}
else if ( frequency == 75)
{
pConfigInfo = &pllCfg_75MHz;
printf("\nPLL frequency 75 MHz\n");
}
else if ( frequency == 98)
{
pConfigInfo = &pllCfg_98MHz;
printf("\nPLL frequency 98 MHz\n");
}
else if ( frequency == 120)
{
pConfigInfo = &pllCfg_120MHz;
printf("\nPLL frequency 120 MHz\n");
}
else
{
pConfigInfo = &pllCfg_100MHz;
printf("\nPLL frequency 100 MHz\n");
}
status = PLL_config (hPll, pConfigInfo);
if(CSL_SOK != status)
{
printf("PLL config failed\n");
return(status);
}
status = PLL_getConfig(hPll, &pllCfg1);
if(status != CSL_SOK)
{
printf("TEST FAILED: PLL get config... Failed.\n");
printf ("Reason: PLL_getConfig failed. [status = 0x%x].\n", status);
return(status);
}
printf("REGISTER --- CONFIG VALUES\n");
printf("PLL_CNTRL1 %04x --- %04x\n",pllCfg1.PLLCNTL1,hPll->pllConfig->PLLCNTL1);
printf("PLL_CNTRL2 %04x --- %04x Test Lock Mon will get set after PLL is up\n",
pllCfg1.PLLCNTL2,hPll->pllConfig->PLLCNTL2);
printf("PLL_CNTRL3 %04x --- %04x\n",pllCfg1.PLLINCNTL,hPll->pllConfig->PLLINCNTL);
printf("PLL_CNTRL4 %04x --- %04x\n",pllCfg1.PLLOUTCNTL,hPll->pllConfig->PLLOUTCNTL);
status = PLL_bypass(hPll);
if(CSL_SOK != status)
{
printf("PLL bypass failed:%d\n",CSL_ESYS_BADHANDLE);
return(status);
}
status = PLL_enable(hPll);
if(CSL_SOK != status)
{
printf("PLL enable failed:%d\n",CSL_ESYS_BADHANDLE);
return(status);
}
return(CSL_TEST_PASSED);
}
CSL_Status pll_sample_freq(Uint16 freq)
{
CSL_Status status;
volatile int i;
status = PLL_init(&pllObj, CSL_PLL_INST_0);
if (status != CSL_SOK)
{
return status;
}
hPll = (PLL_Handle)(&pllObj);
PLL_reset(hPll);
status = PLL_bypass(hPll);
if (status != CSL_SOK)
{
return status;
}
/* Configure the PLL */
switch(freq){
case 40:
pConfigInfo = (PLL_Config *)&pllCfg_40MHz;
break;
case 100:
pConfigInfo = (PLL_Config *)&pllCfg_100MHz;
break;
case 120:
pConfigInfo = (PLL_Config *)&pllCfg_120MHz;
break;
default:
pConfigInfo = (PLL_Config *)&pllCfg_100MHz;
}
status = PLL_config (hPll, pConfigInfo);
if (status != CSL_SOK)
{
return(status);
}
status = PLL_getConfig(hPll, &pllCfg1);
if (status != CSL_SOK)
{
return status;
}
/* Wait for PLL to stabilize */
for (i=0; i<100; i++);
status = PLL_enable(hPll);
if (status != CSL_SOK)
{
return status;
}
// set DSP_LDO to 1.05V
//*(volatile ioport unsigned int *)(0x7004) |= 0x0002;
return CSL_SOK;
}
