AGESA_STATUS
STATIC
PcieTopologySetCoreConfigCZ (
IN PCIe_WRAPPER_CONFIG *Wrapper,
OUT BOOLEAN *ConfigChanged,
IN PCIe_PLATFORM_CONFIG *Pcie
)
{
UINT8 CoreId;
AGESA_STATUS Status;
D0F0xE4_WRAP_0080_STRUCT D0F0xE4_WRAP_0080;
Status = AGESA_SUCCESS;
IDS_HDT_CONSOLE (GNB_TRACE, "PcieTopologySetCoreConfigCZ Enter\n");
if (PcieLibIsPcieWrapper (Wrapper)) {
for (CoreId = Wrapper->StartPcieCoreId; CoreId <= Wrapper->EndPcieCoreId; CoreId++) {
UINT64 ConfigurationSignature;
UINT8 NewConfigurationValue;
ConfigurationSignature = PcieConfigGetConfigurationSignature (Wrapper, CoreId);
Status = PcieFmGetCoreConfigurationValue (Wrapper, CoreId, ConfigurationSignature, &NewConfigurationValue);
if (Status == AGESA_SUCCESS) {
D0F0xE4_WRAP_0080.Value = PcieRegisterRead (
Wrapper,
WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_0080_ADDRESS),
Pcie
);
IDS_HDT_CONSOLE (PCIE_MISC, " Core Configuration: Wrapper [%s], CoreID [%d] - %s Original configuration - %s\n",
PcieFmDebugGetWrapperNameString (Wrapper),
CoreId,
PcieFmDebugGetCoreConfigurationString (Wrapper, NewConfigurationValue),
PcieFmDebugGetCoreConfigurationString (Wrapper, (UINT8) D0F0xE4_WRAP_0080.Field.StrapBifLinkConfig)
);
if (ConfigChanged != NULL) {
if (D0F0xE4_WRAP_0080.Field.StrapBifLinkConfig != NewConfigurationValue) {
*ConfigChanged = TRUE;
}
}
D0F0xE4_WRAP_0080.Field.StrapBifLinkConfig = NewConfigurationValue;
PcieRegisterWrite (
Wrapper,
WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_0080_ADDRESS),
D0F0xE4_WRAP_0080.Value,
FALSE,
Pcie
);
} else {
IDS_HDT_CONSOLE (PCIE_MISC, " ERROR! Core Configuration : Wrapper [%s], Signature [0x%x, 0x%x]\n",
PcieFmDebugGetWrapperNameString (Wrapper),
((UINT32*)&ConfigurationSignature)[1],
((UINT32*)&ConfigurationSignature)[0]
);
PcieConfigDisableAllEngines (PciePortEngine | PcieDdiEngine, Wrapper);
}
}
}
IDS_HDT_CONSOLE (GNB_TRACE, "PcieTopologySetCoreConfigCZ Exit\n");
return Status;
}
AGESA_STATUS
PcieTopologySetCoreConfig (
IN PCIe_WRAPPER_CONFIG *Wrapper,
IN PCIe_PLATFORM_CONFIG *Pcie
)
{
UINT8 CoreId;
AGESA_STATUS Status;
Status = AGESA_SUCCESS;
if (PcieLibIsPcieWrapper (Wrapper)) {
for (CoreId = Wrapper->StartPcieCoreId; CoreId <= Wrapper->EndPcieCoreId; CoreId++) {
UINT64 ConfigurationSignature;
UINT8 NewConfigurationValue;
ConfigurationSignature = PcieConfigGetConfigurationSignature (Wrapper, CoreId);
Status = PcieFmGetCoreConfigurationValue (Wrapper, CoreId, ConfigurationSignature, &NewConfigurationValue);
if (Status == AGESA_SUCCESS) {
IDS_HDT_CONSOLE (PCIE_MISC, " Core Configuration: Wrapper [%s], CoreID [%d] - %s\n",
PcieFmDebugGetWrapperNameString (Wrapper),
CoreId,
PcieFmDebugGetCoreConfigurationString (Wrapper, NewConfigurationValue)
);
PcieRegisterWriteField (
Wrapper,
WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_0080_ADDRESS),
D0F0xE4_WRAP_0080_StrapBifLinkConfig_OFFSET,
D0F0xE4_WRAP_0080_StrapBifLinkConfig_WIDTH,
NewConfigurationValue,
FALSE,
Pcie
);
} else {
IDS_HDT_CONSOLE (PCIE_MISC, " ERROR! Core Configuration : Wrapper [%s], Signature [0x%x, 0x%x]\n",
PcieFmDebugGetWrapperNameString (Wrapper),
((UINT32*)&ConfigurationSignature)[1],
((UINT32*)&ConfigurationSignature)[0]
);
PcieConfigDisableAllEngines (PciePortEngine | PcieDdiEngine, Wrapper);
}
}
}
return Status;
}
AGESA_STATUS
PcieFP2x8CheckCallbackTN (
IN PCIe_WRAPPER_CONFIG *Wrapper,
IN OUT VOID *Buffer,
IN PCIe_PLATFORM_CONFIG *Pcie
)
{
UINT32 LaneBitmap;
AGESA_STATUS Status;
IDS_HDT_CONSOLE (GNB_TRACE, "PcieFP2x8CheckCallbackTN Enter\n");
Status = AGESA_SUCCESS;
if (Wrapper->WrapId == GFX_WRAP_ID) {
LaneBitmap = PcieUtilGetWrapperLaneBitMap (LANE_TYPE_PCIE_PHY_NATIVE | LANE_TYPE_DDI_PHY_NATIVE, 0, Wrapper);
IDS_HDT_CONSOLE (GNB_TRACE, "FP2 GFX Wrpper phy LaneBitmap = %x\n", LaneBitmap);
if (((LaneBitmap & 0xFF) != 0) && ((LaneBitmap & 0xFF00) != 0)) {
IDS_HDT_CONSOLE (GNB_TRACE, "Error!! FP2 GFX Wrpper cannot use both phy#\n");
Status = AGESA_ERROR;
PcieConfigDisableAllEngines (PciePortEngine | PcieDdiEngine, Wrapper);
PutEventLog (
AGESA_ERROR,
GNB_EVENT_INVALID_LANES_CONFIGURATION,
(LibAmdBitScanForward (LaneBitmap) + Wrapper->StartPhyLane),
(LibAmdBitScanReverse (LaneBitmap) + Wrapper->StartPhyLane),
0,
0,
GnbLibGetHeader (Pcie)
);
ASSERT (FALSE);
}
}
IDS_HDT_CONSOLE (GNB_TRACE, "PcieFP2x8CheckCallbackTN Exit\n");
return Status;
}
AGESA_STATUS
PcieMapTopologyOnComplex (
IN PCIe_COMPLEX_DESCRIPTOR *ComplexDescriptor,
IN PCIe_COMPLEX_CONFIG *Complex,
IN PCIe_PLATFORM_CONFIG *Pcie
)
{
PCIe_SILICON_CONFIG *Silicon;
PCIe_WRAPPER_CONFIG *Wrapper;
AGESA_STATUS AgesaStatus;
AGESA_STATUS Status;
AgesaStatus = AGESA_SUCCESS;
IDS_HDT_CONSOLE (GNB_TRACE, "PcieMapTopologyOnComplex Enter\n");
Silicon = PcieConfigGetChildSilicon (Complex);
while (Silicon != NULL) {
Wrapper = PcieConfigGetChildWrapper (Silicon);
while (Wrapper != NULL) {
Status = PcieMapTopologyOnWrapper (ComplexDescriptor, Wrapper, Pcie);
AGESA_STATUS_UPDATE (Status, AgesaStatus);
if (Status == AGESA_ERROR) {
PcieConfigDisableAllEngines (PciePortEngine | PcieDdiEngine, Wrapper);
IDS_HDT_CONSOLE (PCIE_MISC, " ERROR! Fail to map topology on %s Wrapper\n",
PcieFmDebugGetWrapperNameString (Wrapper)
);
ASSERT (FALSE);
}
Wrapper = PcieLibGetNextDescriptor (Wrapper);
}
Status = PcieMapPortsPciAddresses (Silicon, Pcie);
AGESA_STATUS_UPDATE (Status, AgesaStatus);
Silicon = PcieLibGetNextDescriptor (Silicon);
}
IDS_HDT_CONSOLE (GNB_TRACE, "PcieMapTopologyOnComplex Exit [%x]\n", AgesaStatus);
return AgesaStatus;
}
/**
* Configure engine list to support lane allocation according to configuration ID.
*
* PCIE port
*
*
* 1 Check if lane from user port descriptor (PCIe_PORT_DESCRIPTOR) belongs to wrapper (PCIe_WRAPPER_CONFIG)
* 2 Check if link width from user descriptor less or equal to link width of engine (PCIe_ENGINE_CONFIG)
* 3 Check if link width is correct. Correct link width for PCIe port x1, x2, x4, x8, x16, correct link width for DDI x4, x8
* 4 Check if user port device number (PCIe_PORT_DESCRIPTOR) match engine port device number (PCIe_ENGINE_CONFIG)
* 5 Check if lane can be muxed
*
*
* DDI Link
*
* 1 Check if lane from user port descriptor (PCIe_DDI_DESCRIPTOR) belongs to wrapper (PCIe_WRAPPER_CONFIG)
* 2 Check lane from (PCIe_DDI_DESCRIPTOR) match exactly phy lane (PCIe_ENGINE_CONFIG)
*
*
*
* @param[in] ComplexDescriptor Pointer to used define complex descriptor
* @param[in,out] Wrapper Pointer to wrapper config descriptor
* @param[in] Pcie Pointer to global PCIe configuration
* @retval AGESA_SUCCESS Topology successfully mapped
* @retval AGESA_ERROR Topology can not be mapped
*/
AGESA_STATUS
PcieMapTopologyOnWrapper (
IN PCIe_COMPLEX_DESCRIPTOR *ComplexDescriptor,
IN OUT PCIe_WRAPPER_CONFIG *Wrapper,
IN PCIe_PLATFORM_CONFIG *Pcie
)
{
AGESA_STATUS AgesaStatus;
AGESA_STATUS Status;
PCIe_ENGINE_CONFIG *EngineList;
UINT32 WrapperPhyLaneBitMap;
IDS_HDT_CONSOLE (GNB_TRACE, "PcieMapTopologyOnWrapper Enter\n");
AgesaStatus = AGESA_SUCCESS;
if (PcieLibIsPcieWrapper (Wrapper)) {
Status = PcieEnginesToWrapper (PciePortEngine, ComplexDescriptor, Wrapper);
AGESA_STATUS_UPDATE (Status, AgesaStatus);
if (Status == AGESA_ERROR) {
// If we can not map topology on wrapper we can not enable any engines.
PutEventLog (
AGESA_ERROR,
GNB_EVENT_INVALID_PCIE_TOPOLOGY_CONFIGURATION,
Wrapper->WrapId,
Wrapper->StartPhyLane,
Wrapper->EndPhyLane,
0,
GnbLibGetHeader (Pcie)
);
PcieConfigDisableAllEngines (PciePortEngine, Wrapper);
}
}
if (PcieLibIsDdiWrapper (Wrapper)) {
Status = PcieEnginesToWrapper (PcieDdiEngine, ComplexDescriptor, Wrapper);
AGESA_STATUS_UPDATE (Status, AgesaStatus);
if (Status == AGESA_ERROR) {
// If we can not map topology on wrapper we can not enable any engines.
PutEventLog (
AGESA_ERROR,
GNB_EVENT_INVALID_DDI_TOPOLOGY_CONFIGURATION,
Wrapper->WrapId,
Wrapper->StartPhyLane,
Wrapper->EndPhyLane,
0,
GnbLibGetHeader (Pcie)
);
PcieConfigDisableAllEngines (PcieDdiEngine, Wrapper);
}
}
// Copy engine data
PcieMapInitializeEngineData (ComplexDescriptor, Wrapper, Pcie);
EngineList = PcieConfigGetChildEngine (Wrapper);
// Verify if we oversubscribe lanes and PHY link width
WrapperPhyLaneBitMap = 0;
while (EngineList != NULL) {
UINT32 EnginePhyLaneBitMap;
if (PcieLibIsEngineAllocated (EngineList)) {
EnginePhyLaneBitMap = PcieConfigGetEnginePhyLaneBitMap (EngineList);
if ((WrapperPhyLaneBitMap & EnginePhyLaneBitMap) != 0) {
IDS_HDT_CONSOLE (PCIE_MISC, " ERROR! Lanes double subscribe lanes [Engine Lanes %d..%d]\n",
EngineList->EngineData.StartLane,
EngineList->EngineData.EndLane
);
PutEventLog (
AGESA_ERROR,
GNB_EVENT_INVALID_LANES_CONFIGURATION,
EngineList->EngineData.StartLane,
EngineList->EngineData.EndLane,
0,
0,
GnbLibGetHeader (Pcie)
);
PcieConfigDisableEngine (EngineList);
Status = AGESA_ERROR;
AGESA_STATUS_UPDATE (Status, AgesaStatus);
} else {
WrapperPhyLaneBitMap |= EnginePhyLaneBitMap;
}
}
EngineList = PcieLibGetNextDescriptor (EngineList);
}
IDS_HDT_CONSOLE (GNB_TRACE, "PcieMapTopologyOnWrapper Exit [%d]\n", AgesaStatus);
return AgesaStatus;
}
