/**
* PHY Pll Personality Init Callback
*
*
*
* @param[in] Wrapper Pointer to wrapper config descriptor
* @param[in] Buffer Pointer to buffer
* @param[in] Pcie Pointer to global PCIe configuration
*/
AGESA_STATUS
PciePhyLetPllPersonalityInitCallbackTN (
IN PCIe_WRAPPER_CONFIG *Wrapper,
IN VOID *Buffer,
IN PCIe_PLATFORM_CONFIG *Pcie
)
{
IDS_HDT_CONSOLE (GNB_TRACE, "PciePhyLetPllPersonalityInitCallbackTN Enter\n");
PciePifPllPowerControl (PowerDownPifs, Wrapper, Pcie);
PciePifSetPllRampTime (NormalRampup, Wrapper, Pcie);
PciePollPifForCompeletion (Wrapper, Pcie);
PcieTopologyLaneControl (
DisableLanes,
PcieUtilGetWrapperLaneBitMap (LANE_TYPE_CORE_ALL, LANE_TYPE_PCIE_SB_CORE_CONFIG, Wrapper),
Wrapper,
Pcie
);
PciePollPifForCompeletion (Wrapper, Pcie);
PcieSetPhyPersonalityTN (Wrapper, Pcie);
PcieWrapSetTxS1CtrlForLaneMux (Wrapper, Pcie);
PciePollPifForCompeletion (Wrapper, Pcie);
PcieTopologyLaneControl (
EnableLanes,
PcieUtilGetWrapperLaneBitMap (LANE_TYPE_CORE_ALL, 0, Wrapper),
Wrapper,
Pcie
);
PcieWrapSetTxOffCtrlForLaneMux (Wrapper, Pcie);
PciePollPifForCompeletion (Wrapper, Pcie);
PciePifPllPowerControl (PowerUpPifs, Wrapper, Pcie);
IDS_HDT_CONSOLE (GNB_TRACE, "PciePhyLetPllPersonalityInitCallbackTN Exit\n");
return AGESA_SUCCESS;
}
/**
* Per wrapper Pcie Init prior training.
*
*
* @param[in] Wrapper Pointer to wrapper configuration descriptor
* @param[in] Buffer Pointer buffer
* @param[in] Pcie Pointer to global PCIe configuration
*/
AGESA_STATUS
PcieInitCallback (
IN PCIe_WRAPPER_CONFIG *Wrapper,
IN OUT VOID *Buffer,
IN PCIe_PLATFORM_CONFIG *Pcie
)
{
AGESA_STATUS Status;
PcieTopologyPrepareForReconfig (Wrapper, Pcie);
Status = PcieTopologySetCoreConfig (Wrapper, Pcie);
ASSERT (Status == AGESA_SUCCESS);
PcieTopologyApplyLaneMux (Wrapper, Pcie);
PcieFmPifSetRxDetectPowerMode (Wrapper, Pcie);
PciePifSetLs2ExitTime (Wrapper, Pcie);
PcieTopologySelectMasterPll (Wrapper, Pcie);
PcieTopologyExecuteReconfig (Wrapper, Pcie);
PcieTopologySetLinkReversal (Wrapper, Pcie);
PciePifApplyGanging (Wrapper, Pcie);
PcieFmPhyApplyGanging (Wrapper, Pcie);
PciePifPllInitForDdi (Wrapper, Pcie);
PcieTopologyLaneControl (
DisableLanes,
PcieUtilGetWrapperLaneBitMap (LANE_TYPE_CORE_ALL, LANE_TYPE_PCIE_CORE_ALLOC, Wrapper),
Wrapper,
Pcie
);
PcieSetDdiOwnPhy (Wrapper, Pcie);
PciePollPifForCompeletion (Wrapper, Pcie);
PcieFmAvertClockPickers (Wrapper, Pcie);
PcieCommonCoreInit (Wrapper, Pcie);
PciePifDisableFifoReset (Wrapper, Pcie);
return Status;
}
VOID
PciePwrPowerDownUnusedLanes (
IN PCIe_WRAPPER_CONFIG *Wrapper,
IN PCIe_PLATFORM_CONFIG *Pcie
)
{
UINT32 UnusedLanes;
IDS_HDT_CONSOLE (GNB_TRACE, "PciePwrPowerDownUnusedLanes Enter\n");
if (Wrapper->Features.PowerOffUnusedLanes != 0) {
UnusedLanes = PcieUtilGetWrapperLaneBitMap (LANE_TYPE_CORE_ALL, LANE_TYPE_PCIE_CORE_ALLOC_ACTIVE, Wrapper);
PcieTopologyLaneControl (
DisableLanes,
UnusedLanes,
Wrapper,
Pcie
);
}
if (Wrapper->Features.PowerOffUnusedPlls != 0) {
UnusedLanes = PcieUtilGetWrapperLaneBitMap (LANE_TYPE_PHY_NATIVE_ALL, LANE_TYPE_PCIE_PHY_NATIVE_ALLOC_ACTIVE | LANE_TYPE_DDI_PHY_NATIVE_ACTIVE, Wrapper);
PciePifPllPowerDown (
UnusedLanes,
Wrapper,
Pcie
);
}
IDS_HDT_CONSOLE (GNB_TRACE, "PciePwrPowerDownUnusedLanes Exit\n");
}
VOID
PciePwrPowerDownUnusedLanes (
IN PCIe_WRAPPER_CONFIG *Wrapper,
IN PCIe_PLATFORM_CONFIG *Pcie
)
{
UINT32 UnusedLanes;
UINT32 AllLanes;
IDS_HDT_CONSOLE (GNB_TRACE, "PciePwrPowerDownUnusedLanes Enter\n");
if (Wrapper->Features.PowerOffUnusedPlls != 0) {
AllLanes = PcieUtilGetWrapperLaneBitMap (LANE_TYPE_PHY_NATIVE_ALL, 0, Wrapper);
UnusedLanes = PcieUtilGetWrapperLaneBitMap (LANE_TYPE_PHY_NATIVE_ALL, LANE_TYPE_PCIE_PHY_NATIVE_ALLOC_ACTIVE, Wrapper);
if (AllLanes != UnusedLanes) {
//Some lanes end up beeing used. We should keep master PLL powered up
UnusedLanes = PcieUtilGetWrapperLaneBitMap (LANE_TYPE_PHY_NATIVE_ALL, LANE_TYPE_PCIE_PHY_NATIVE_ALLOC_ACTIVE | LANE_TYPE_PCIE_PHY_NATIVE_MASTER_PLL, Wrapper);
}
PciePifPllPowerDown (
UnusedLanes,
Wrapper,
Pcie
);
}
if (Wrapper->Features.PowerOffUnusedLanes != 0) {
UnusedLanes = PcieUtilGetWrapperLaneBitMap (LANE_TYPE_CORE_ALL, LANE_TYPE_PCIE_CORE_ALLOC_ACTIVE, Wrapper);
PcieTopologyLaneControl (
DisableLanes,
UnusedLanes,
Wrapper,
Pcie
);
}
IDS_HDT_CONSOLE (GNB_TRACE, "PciePwrPowerDownUnusedLanes Exit\n");
}
/**
* Per wrapper Pcie Init prior training.
*
*
* @param[in] Wrapper Pointer to wrapper configuration descriptor
* @param[in] Buffer Pointer buffer
* @param[in] Pcie Pointer to global PCIe configuration
*/
AGESA_STATUS
STATIC
PcieEarlyInitCallbackTN (
IN PCIe_WRAPPER_CONFIG *Wrapper,
IN OUT VOID *Buffer,
IN PCIe_PLATFORM_CONFIG *Pcie
)
{
AGESA_STATUS Status;
BOOLEAN CoreConfigChanged;
BOOLEAN PllConfigChanged;
IDS_HDT_CONSOLE (GNB_TRACE, "PcieEarlyInitCallbackTN Enter\n");
CoreConfigChanged = FALSE;
PllConfigChanged = FALSE;
PcieTopologyPrepareForReconfig (Wrapper, Pcie);
Status = PcieTopologySetCoreConfig (Wrapper, &CoreConfigChanged, Pcie);
ASSERT (Status == AGESA_SUCCESS);
PcieTopologyApplyLaneMux (Wrapper, Pcie);
PciePifSetRxDetectPowerMode (Wrapper, Pcie);
PciePifSetLs2ExitTime (Wrapper, Pcie);
PcieTopologySelectMasterPll (Wrapper, &PllConfigChanged, Pcie);
if (CoreConfigChanged || PllConfigChanged) {
PcieTopologyExecuteReconfigV4 (Wrapper, Pcie);
}
PcieTopologyCleanUpReconfig (Wrapper, Pcie);
PcieTopologySetLinkReversalV4 (Wrapper, Pcie);
if (Wrapper->Features.PowerOffUnusedPlls != 0) {
PciePifPllPowerDown (
PcieUtilGetWrapperLaneBitMap (LANE_TYPE_CORE_ALL, LANE_TYPE_PCIE_CORE_ALLOC | LANE_TYPE_DDI_PHY_NATIVE, Wrapper),
Wrapper,
Pcie
);
PciePifPllInitForDdi (Wrapper, Pcie);
PciePwrPowerDownDdiPllsV4 (Wrapper, Pcie);
}
PcieTopologyLaneControl (
DisableLanes,
PcieUtilGetWrapperLaneBitMap (LANE_TYPE_CORE_ALL, LANE_TYPE_PCIE_CORE_ALLOC, Wrapper),
Wrapper,
Pcie
);
PcieSetReciverTerminationTN (Wrapper, Pcie);
PcieSetDdiOwnPhyV4 (Wrapper, Pcie);
PciePollPifForCompeletion (Wrapper, Pcie);
PciePhyAvertClockPickers (Wrapper, Pcie);
PcieEarlyCoreInitTN (Wrapper, Pcie);
PcieSetSsidV4 (UserOptions.CfgGnbPcieSSID, Wrapper, Pcie);
if (PcieConfigIsPcieWrapper (Wrapper)) {
PcieSetDllCapTN (Wrapper, Pcie);
}
IDS_HDT_CONSOLE (GNB_TRACE, "PcieEarlyInitCallbackTN Exit [%x]\n", Status);
return Status;
}
/**
* RX offset cancellation enablement
*
*
*
* @param[in] Wrapper Pointer to Wrapper configuration data area
* @param[in] Pcie Pointer to PCIe configuration data area
*/
VOID
PcieOffsetCancelCalibration (
IN PCIe_WRAPPER_CONFIG *Wrapper,
IN PCIe_PLATFORM_CONFIG *Pcie
)
{
UINT32 LaneBitmap;
D0F0xBC_x1F39C_STRUCT D0F0xBC_x1F39C;
LaneBitmap = PcieUtilGetWrapperLaneBitMap (LANE_TYPE_PHY_NATIVE_ALL, LANE_TYPE_PCIE_SB_CORE_CONFIG, Wrapper);
if ((Wrapper->WrapId != GFX_WRAP_ID) && (Wrapper->WrapId != GPP_WRAP_ID)) {
return;
}
if (LaneBitmap != 0) {
D0F0xBC_x1F39C.Value = 0;
D0F0xBC_x1F39C.Field.Tx = 1;
D0F0xBC_x1F39C.Field.Rx = 1;
D0F0xBC_x1F39C.Field.UpperLaneID = LibAmdBitScanReverse (LaneBitmap) + Wrapper->StartPhyLane;
D0F0xBC_x1F39C.Field.LowerLaneID = LibAmdBitScanForward (LaneBitmap) + Wrapper->StartPhyLane;
GnbRegisterWriteTN (D0F0xBC_x1F39C_TYPE, D0F0xBC_x1F39C_ADDRESS, &D0F0xBC_x1F39C.Value, GNB_REG_ACC_FLAG_S3SAVE, GnbLibGetHeader (Pcie));
GnbSmuServiceRequestV4 (
PcieConfigGetParentSilicon (Wrapper)->Address,
SMC_MSG_PHY_LN_OFF,
GNB_REG_ACC_FLAG_S3SAVE,
GnbLibGetHeader (Pcie)
);
GnbSmuServiceRequestV4 (
PcieConfigGetParentSilicon (Wrapper)->Address,
SMC_MSG_PHY_LN_ON,
GNB_REG_ACC_FLAG_S3SAVE,
GnbLibGetHeader (Pcie)
);
}
PcieTopologyLaneControl (
EnableLanes,
PcieUtilGetWrapperLaneBitMap (LANE_TYPE_ALL, 0, Wrapper),
Wrapper,
Pcie
);
}
/**
* Reduce link width
*
*
* @param[in] LinkWidth Link width
* @param[in] Engine Pointer to Engine config descriptor
* @param[in] Pcie Pointer to global PCIe configuration
*/
VOID
PcieTopologyReduceLinkWidth (
IN UINT8 LinkWidth,
IN PCIe_ENGINE_CONFIG *Engine,
IN PCIe_PLATFORM_CONFIG *Pcie
)
{
PCIe_WRAPPER_CONFIG *Wrapper;
UINT32 LinkReversed;
UINT8 DeltaLinkWidthBitmap;
UINT32 LanesToDisable;
Wrapper = PcieConfigGetParentWrapper (Engine);
LinkReversed = PcieUtilIsLinkReversed (TRUE, Engine, Pcie);
DeltaLinkWidthBitmap = (1 << (PcieConfigGetNumberOfCoreLane (Engine) - LinkWidth)) - 1;
LanesToDisable = (DeltaLinkWidthBitmap << ((LinkReversed == 1) ? Engine->Type.Port.StartCoreLane : (Engine->Type.Port.StartCoreLane + LinkWidth)));
PcieTopologyLaneControl (
DisableLanes,
LanesToDisable,
Wrapper,
Pcie
);
}
