AGESA_STATUS
STATIC
PcieMidPortInitKV (
IN OUT PCIe_INFO_BUFFER *PcieInfoBuffer,
IN PCIe_PLATFORM_CONFIG *Pcie
)
{
AGESA_STATUS Status;
PCIE_LINK_SPEED_CAP GlobalSpeedCap;
Status = AGESA_SUCCESS;
PcieConfigRunProcForAllEngines (
DESCRIPTOR_ALLOCATED | DESCRIPTOR_PCIE_ENGINE,
PcieMidPortInitCallbackKV,
PcieInfoBuffer,
Pcie
);
GlobalSpeedCap = PcieUtilGlobalGenCapability (
PCIE_PORT_GEN_CAP_BOOT | PCIE_GLOBAL_GEN_CAP_TRAINED_PORTS | PCIE_GLOBAL_GEN_CAP_HOTPLUG_PORTS,
Pcie
);
PcieSetVoltageKV (GlobalSpeedCap, Pcie);
return Status;
}
AGESA_STATUS
STATIC
PciePostInitML (
IN PCIe_PLATFORM_CONFIG *Pcie
)
{
PCIE_LINK_SPEED_CAP GlobalSpeedCap;
GlobalSpeedCap = PcieUtilGlobalGenCapability (
PCIE_PORT_GEN_CAP_BOOT | PCIE_GLOBAL_GEN_CAP_TRAINED_PORTS | PCIE_GLOBAL_GEN_CAP_HOTPLUG_PORTS,
Pcie
);
PcieSetVoltageML (GlobalSpeedCap, Pcie);
return AGESA_SUCCESS;
}
/**
* Per wrapper Pcie Init prior training.
*
*
* @param[in] Wrapper Pointer to wrapper configuration descriptor
* @param[in] Buffer Pointer buffer
* @param[in] Pcie Pointer to global PCIe configuration
*/
AGESA_STATUS
PciePostInitCallback (
IN PCIe_WRAPPER_CONFIG *Wrapper,
IN OUT VOID *Buffer,
IN PCIe_PLATFORM_CONFIG *Pcie
)
{
AGESA_STATUS Status;
Status = AGESA_SUCCESS;
PcieFmConfigureClock (
PcieUtilGlobalGenCapability (PCIE_PORT_GEN_CAP_BOOT | PCIE_GLOBAL_GEN_CAP_ALL_PORTS, Pcie),
Wrapper,
Pcie
);
return Status;
}
AGESA_STATUS
PciePostInit (
IN PCIe_PLATFORM_CONFIG *Pcie
)
{
AGESA_STATUS Status;
AGESA_STATUS AgesaStatus;
IDS_HDT_CONSOLE (GNB_TRACE, "PciePostInit Enter\n");
AgesaStatus = AGESA_SUCCESS;
Status = PcieConfigRunProcForAllWrappers (DESCRIPTOR_PCIE_WRAPPER, PciePostInitCallback, NULL, Pcie);
AGESA_STATUS_UPDATE (Status, AgesaStatus);
PcieFmSetBootUpVoltage (
PcieUtilGlobalGenCapability (PCIE_PORT_GEN_CAP_BOOT | PCIE_GLOBAL_GEN_CAP_ALL_PORTS, Pcie),
Pcie
);
IDS_HDT_CONSOLE (GNB_TRACE, "PciePostInit Exit [%x]\n", AgesaStatus);
return AgesaStatus;
}
/**
* Various initialization needed prior topology and configuration initialization
*
*
*
* @param[in] Pcie Pointer to global PCIe configuration
*
*/
VOID
PcieFmPreInit (
IN PCIe_PLATFORM_CONFIG *Pcie
)
{
UINT32 Index;
PCIe_SILICON_CONFIG *Silicon;
PCIE_LINK_SPEED_CAP GlobalCapability;
F14_PCIe_WRAPPER_CONFIG *F14PcieWrapper;
Silicon = PcieComplexGetSiliconList (&Pcie->ComplexList[0]);
F14PcieWrapper = &((F14_COMPLEX_CONFIG*) Silicon)->FmGppWrapper ;
GlobalCapability = PcieUtilGlobalGenCapability (
PCIE_PORT_GEN_CAP_MAX | PCIE_GLOBAL_GEN_CAP_ALL_PORTS,
Pcie
);
if ((GlobalCapability == PcieGen1) && (F14PcieWrapper->NativeGen1Support == TRUE)) {
PcieFmExecuteNativeGen1Reconfig (Pcie);
}
Silicon = PcieComplexGetSiliconList (&Pcie->ComplexList[0]);
for (Index = 0; Index < (sizeof (PcieInitTable) / sizeof (PCIE_HOST_REGISTER_ENTRY)); Index++) {
PcieSiliconRegisterRMW (
Silicon,
PcieInitTable[Index].Reg,
PcieInitTable[Index].Mask,
PcieInitTable[Index].Data,
FALSE,
Pcie
);
}
// Set PCIe SSID.
PcieSiliconRegisterRMW (
Silicon,
WRAP_SPACE (0, D0F0xE4_WRAP_8002_ADDRESS),
D0F0xE4_WRAP_8002_SubsystemVendorID_MASK | D0F0xE4_WRAP_8002_SubsystemID_MASK,
UserOptions.CfgGnbPcieSSID,
FALSE,
Pcie
);
}
