unsigned char SPIRecvByte(int channel)
{
unsigned int timeout = 65535;
char value;
spi_chanel_select(channel);
spi_enable();
while((timeout > 1) &&( !spi_rxfifo_empty()) )
{
timeout--;
}
value = (char ) SPIReadReg(SSP_DR);
PDEBUG("the value in spi read is :%02x\n",value);
while(spi_busy());
PrintRegs();
spi_desable();
return value;
}
void CTestCrashDataSource::ReadRegistersL( const TUint64 aThreadId, RRegisterList &aRegisterList )
{
//RDebug::Print( _L("CTestCrashDataSource::ReadRegisters( threadId=0x%X)\n"), I64LOW(aThreadId) );
if( aRegisterList.Count() )
{
RDebug::Printf( "Register list already supplied\n" );
User::LeaveIfError(SetSimRegValues( aThreadId, aRegisterList ));
}
else
{
RDebug::Printf( "Creating register list\n" );
GetRegisterListL( aRegisterList );
User::LeaveIfError(SetSimRegValues( aThreadId, aRegisterList ));
}
PrintRegs( aRegisterList );
}
static int hi3511_spi_probe(struct platform_device *pdev)
{
int temp = 0;
spi_reset();
YX_GPIO_SC_PERCTRL1(10, 1); //set the gpio pin function to spi
YX_GPIO_SC_PERCTRL1(0, 0);
YX_GPIO_SC_PERCTRL1(1, 1);
// Enable the SPI clock
SPISetBitValue(7, 1, SC_PEREN);
//Set the CR0 value Here SSP is not Enabled,so we can set the value .
temp |= (0x7) | (0x0 << 4) | (0x0 << 6) | (0x3 << 8);
SPIWrtieRes(temp, SSP_CR0);
//Set the SSP_CPSR regs value
temp = 36;
SPIWrtieRes(temp, SSP_CPSR);
spi_enable();
//SPISetBitValue(0, 1, SSP_CR1);
PrintRegs();
return 0;
}
void Interpreter::Run (unsigned int cycles)
{
m_run = true;
CLOCK.ResetCounter();
while(m_run && CLOCK.GetCounter() < cycles)
{
switch (m_haltcnt)
{
case 255: // normal mode
PrintRegs();
if (FLAG_T)
{
if (R(15) & 0x1)
met_abort("PC not 16 bit aligned : " << IOS_ADD << R(15));
code = MEM.Read16(R(15)-2);
if (traceenabled)
{
std::stringstream ss;
ss << IOS_TRACE << R(15) - 2 << ':' << std::setw(4) << code << " ";
ss.setf(std::ios::left, std::ios::adjustfield);
ss << std::setw(32) << std::setfill(' ') << Disassembler::Instruction(R(15), (uint16_t)code).ToString();
ss.setf(std::ios::right, std::ios::adjustfield);
ss << IOS_TRACE;
for (int i = 0; i < 16; i++)
ss << std::setw(8) << R(i) << ' ';
UpdateCpsr();
ss << std::setw(8) << m_st.cpsr.dw << ' ';
ss << std::setw(8) << m_st.spsr.dw << ' ';
trace_bizhawk(ss.str());
}
R(15) += 2;
t_Code();
}
else
{
if (R(15) & 0x3)
met_abort("PC not 32 bit aligned : " << IOS_ADD << R(15));
if (R(15) < 0x01000000 && !MEM.HasBios())
{
switch (R(15))
{
case 0x004:
Bios::Bios000h();
break;
case 0x00C:
Bios::Bios008h();
break;
case 0x01C:
Bios::Bios018h();
break;
case 0x134:
Bios::Bios130h();
break;
case 0x33C:
Bios::Bios338h();
break;
case 0x16C:
Bios::Bios168h();
break;
default:
met_abort("Jump to " << IOS_ADD << R(15));
}
}
else
{
code = MEM.Read32(R(15)-4);
if (traceenabled)
{
std::stringstream ss;
ss << IOS_TRACE << R(15) - 4 << ':' << std::setw(8) << code << ' ';
ss.setf(std::ios::left, std::ios::adjustfield);
ss << std::setw(32) << std::setfill(' ') << Disassembler::Instruction(R(15), (uint32_t)code).ToString();
ss.setf(std::ios::right, std::ios::adjustfield);
ss << IOS_TRACE;
for (int i = 0; i < 16; i++)
ss << std::setw(8) << R(i) << ' ';
UpdateCpsr();
ss << std::setw(8) << m_st.cpsr.dw << ' ';
ss << std::setw(8) << m_st.spsr.dw << ' ';
trace_bizhawk(ss.str());
}
R(15) += 4;
a_Code();
}
}
if (R(15) < 0x01000000 && FLAG_T && !MEM.HasBios())
met_abort("Jump to " << IOS_ADD << R(15));
CLOCK.Commit();
if (m_interrupt)
// irq are enabled and there are irq waiting...
{
// FIXME : do we really need this ??
// if not, we can get rid of save and load state and reset
if (m_interrupt_)
{
m_interrupt_ = false;
// XXX we must be sure the cpu isn't halted when an interrupt
// occurs
// should be removed after since it takes no time to make a new
// iteration of the loop
m_haltcnt = 255;
CPU.Interrupt();
}
else
{
// XXX
if (m_haltcnt != 255)
{
m_haltcnt = 255;
CPU.Interrupt();
}
else
m_interrupt_ = true;
}
}
break;
case 0: // halt mode
if (m_if & m_ie) // interrupt occured
{
m_haltcnt = 255; // return to normal mode
CPU.Interrupt();
// XXX use an else
break;
}
CLOCK.WaitForNext();
// XXX remove this block
if (m_if & m_ie) // interrupt occured
{
m_haltcnt = 255; // return to normal mode
CPU.Interrupt();
}
break;
case 1: // stop mode
met_abort("Stop mode not implemented");
break;
default:
met_abort("Unknown HALTCNT value : " << (int)m_haltcnt);
break;
}
}
m_run = false;
}
