/* Master transmit in interrupt mode */
static void sendI2CMaster(uint16_t AddressI2C, bool ledStateOut,
uint8_t regAddr)
{
uint8_t SendData[10];
I2C_PARAM_T param;
I2C_RESULT_T result;
ErrorCode_t error_code;
int index = 0;
SendData[index++] = (uint8_t) AddressI2C;
SendData[index++] = (uint8_t) regAddr; /* I2C device regAddr */
SendData[index++] = (uint8_t) 0x00;
SendData[index++] = (uint8_t) ledValues[ledValue];
SendData[index++] = (uint8_t) displayNumber;
/* Setup I2C parameters for number of bytes with stop
- appears as follows on bus:
Start - address7 or address10upper - ack
(10 bits addressing only) address10lower - ack
value 1 - ack
value 2 - ack - stop */
param.num_bytes_send = index;
param.buffer_ptr_send = &SendData[0];
param.num_bytes_rec = 0;
param.stop_flag = 1;
param.func_pt = cbI2CComplete;
/* Set timeout (much) greater than the transfer length */
//LPC_I2CD_API->i2c_set_timeout(i2cHandleMaster, 100000);
/* Do master write transfer */
intErrCode = -1;
/* Function is non-blocking, returned error should
be LPC_OK, but isn't checked here */
error_code = LPC_I2CD_API->i2c_master_transmit_intr(i2cHandleMaster,
¶m, &result);
/* Sleep until transfer is complete, but allow IRQ to wake system
to handle I2C IRQ */
while (intErrCode == -1) {
__WFI();
}
/* Cast saved error code from callback */
error_code = (ErrorCode_t) intErrCode;
// /* Completed without erors? */
if (error_code != LPC_OK) {
/* Likely cause is NAK */
Print_Val("i2c_master_transmit error code : 0x", error_code);
errorI2C();
}
/* Note results are only valid when there are no errors */
}
/**
* @brief Main routine for SPI example
* @return Does not return
*/
int main(void)
{
uint16_t seed = 0;
SystemCoreClockUpdate();
Board_Init();
/* SPI initialization */
Init_SPI_PinMux();
/* Initialize stopwatch driver so some event times can be measured */
StopWatch_Init();
/* Setup SPI controllers */
setupMaster();
setupSlave();
/* Enable SPI controller interrupts */
NVIC_EnableIRQ(LPC_SPIMASTERIRQNUM);
NVIC_EnableIRQ(LPC_SPISLAVEIRQNUM);
DEBUGSTR("SPI master/slave combined example\r\n");
/* If you enable loopback mode and connect the master and slave controller's clock
and SSEL lines together, the master and slave will wrap data to each other */
// Chip_SPIM_EnableLoopBack(LPC_SPIMASTERPORT);
/* Loop forever */
while (1) {
/* Setup some data for transmit from master to slave and slave to master */
seed = bufferInit(seed);
/* Set slave transfer, this is only the initial transfer,
the callbacks can change this later */
spiSlaveXfer.pTXData16 = slaveTXBuffer16;
spiSlaveXfer.txCount = sizeof(slaveTXBuffer16) / sizeof(uint16_t); /* Count is in transfer size */
spiSlaveXfer.pRXData16 = slaveRXBuffer16;
spiSlaveXfer.rxCount = sizeof(slaveRXBuffer16) / sizeof(uint16_t); /* Count is in transfer size */
/* Set master transfer, this is only the initial transfer,
the callbacks can change this later */
spiMasterXfer.pTXData16 = masterTXBuffer16; /* Use NULL to send 0x0 */
spiMasterXfer.txCount = sizeof(masterTXBuffer16) / sizeof(uint16_t);/* Count is in transfer size */
spiMasterXfer.pRXData16 = masterRXBuffer16;
spiMasterXfer.rxCount = sizeof(masterRXBuffer16) / sizeof(uint16_t);/* Count is in transfer size */
/* Setup master transfer options - 16 data bits per transfer, EOT, EOF */
spiMasterXfer.options =
SPI_TXCTL_FLEN(16) | /* This must be enabled as a minimum, use 16 data bits */
// SPI_TXCTL_EOT | /* Enable this to assert and deassert SSEL for each individual byte/word, current slave functions for this example do not support this */
// SPI_TXCTL_EOF | /* Insert a delay between bytes/words as defined by frame delay time */
// SPI_TXCTL_RXIGNORE | /* Enable this to ignore incoming data, or set spiMasterXfer.pRXData16 to NULL to ignore RX data */
0;
/* Transfer will terminate after current buffer is sent. If terminate is not set, the buffers
must be setup by the callbacks */
spiMasterXfer.terminate = true;
/* Use SPI select 0 */
spiMasterXfer.sselNum = 0;
/* Time master and slave transfers */
masterTime = StopWatch_Start();
/* Limitation: The call below 'pre-buffers' the initial slave transmit datum.
If this isn't pre-buffered, a slave transmit underflow will always occur
at slave assertion time for the initial transmit datum. The datum sent to the
master will be 0. This is ok as we are only using a single slave, but with multiple
slaves pre-buffering is not always an option and the master might need to toss the
first byte. */
Chip_SPI_FlushFifos(LPC_SPIMASTERPORT);
Chip_SPI_FlushFifos(LPC_SPISLAVEPORT);
Chip_SPIS_PreBuffSlave(LPC_SPISLAVEPORT, &spiSlaveXfer);
/* Start master transfer */
Chip_SPIM_Xfer(LPC_SPIMASTERPORT, &spiMasterXfer);
/* Sleep until transfers are complete */
mEnd = sEnd = false;
while ((mEnd == false) || (sEnd == false)) {
__WFI();
}
/* Toggle LED */
Board_LED_Toggle(0);
/* Display some information about the transfer */
Print_Val("\r\nTRANSFER COMPLETE: errors = 0x", errors);
errors = 0;
Print_Val("Master total transfer time in uS: 0x", StopWatch_TicksToUs(StopWatch_Elapsed(masterTime)));
/* Show data */
showData("Master TX data", masterTXBuffer16);
showData("Master RX data", masterRXBuffer16);
showData("Slave TX data", slaveTXBuffer16);
showData("Slave RX data", slaveRXBuffer16);
}
}
