int qm_ss_spi_irq_transfer(const qm_ss_spi_t spi, const qm_ss_spi_async_transfer_t *const xfer) { QM_CHECK(spi < QM_SS_SPI_NUM, -EINVAL); QM_CHECK(xfer, -EINVAL); /* Load and save initial control register */ uint32_t ctrl = __builtin_arc_lr(base[spi] + QM_SS_SPI_CTRL); uint8_t tmode = (uint8_t)((ctrl & QM_SS_SPI_CTRL_TMOD_MASK) >> QM_SS_SPI_CTRL_TMOD_OFFS); uint8_t bytes = BYTES_PER_FRAME(ctrl); QM_CHECK(tmode == QM_SS_SPI_TMOD_TX_RX ? (xfer->tx_len == xfer->rx_len) : 1, -EINVAL); spi_async_transfer[spi] = xfer; tx_c[spi] = xfer->tx_len; rx_c[spi] = xfer->rx_len; /* Set NDF (Number of Data Frames) in RX or EEPROM Read mode. (-1) */ if (tmode == QM_SS_SPI_TMOD_RX || tmode == QM_SS_SPI_TMOD_EEPROM_READ) { ctrl &= ~QM_SS_SPI_CTRL_NDF_MASK; ctrl |= ((xfer->rx_len - 1) << QM_SS_SPI_CTRL_NDF_OFFS) & QM_SS_SPI_CTRL_NDF_MASK; __builtin_arc_sr(ctrl, base[spi] + QM_SS_SPI_CTRL); } uint32_t ftlr = (((FIFO_RX_W_MARK < xfer->rx_len ? FIFO_RX_W_MARK : xfer->rx_len) - 1) << QM_SS_SPI_FTLR_RFT_OFFS) & QM_SS_SPI_FTLR_RFT_MASK; __builtin_arc_sr(ftlr, base[spi] + QM_SS_SPI_FTLR); /* Unmask all interrupts */ __builtin_arc_sr(QM_SS_SPI_INTR_ALL, base[spi] + QM_SS_SPI_INTR_MASK); /* Enable SPI device */ QM_SS_REG_AUX_OR(base[spi] + QM_SS_SPI_SPIEN, QM_SS_SPI_SPIEN_EN); /* RX only transfers need a dummy frame byte to be sent. */ if (tmode == QM_SS_SPI_TMOD_RX) { fifo_write(spi, (uint8_t *)&dummy_frame, bytes); } return 0; }
int qm_ss_spi_irq_transfer(const qm_ss_spi_t spi, const qm_ss_spi_async_transfer_t *const xfer) { QM_CHECK(spi < QM_SS_SPI_NUM, -EINVAL); QM_CHECK(xfer, -EINVAL); /* Load and save initial control register */ uint32_t ctrl = __builtin_arc_lr(base[spi] + QM_SS_SPI_CTRL); uint8_t tmode = (uint8_t)((ctrl & QM_SS_SPI_CTRL_TMOD_MASK) >> QM_SS_SPI_CTRL_TMOD_OFFS); QM_CHECK(tmode == QM_SS_SPI_TMOD_TX_RX ? (xfer->tx_len == xfer->rx_len) : 1, -EINVAL); transfer[spi] = xfer; tx_c[spi] = xfer->tx_len; rx_c[spi] = xfer->rx_len; tx_p[spi] = xfer->tx; rx_p[spi] = xfer->rx; /* RX only transfers need a dummy frame byte to be sent. */ if (tmode == QM_SS_SPI_TMOD_RX) { tx_p[spi] = (uint8_t *)&dummy_frame; tx_c[spi] = 1; } uint32_t ftlr = (((FIFO_RX_W_MARK < xfer->rx_len ? FIFO_RX_W_MARK : xfer->rx_len) - 1) << QM_SS_SPI_FTLR_RFT_OFFS) & QM_SS_SPI_FTLR_RFT_MASK; __builtin_arc_sr(ftlr, base[spi] + QM_SS_SPI_FTLR); /* Unmask all interrupts */ __builtin_arc_sr(QM_SS_SPI_INTR_ALL, base[spi] + QM_SS_SPI_INTR_MASK); /* Enable SPI device */ QM_SS_REG_AUX_OR(base[spi] + QM_SS_SPI_SPIEN, QM_SS_SPI_SPIEN_EN); return 0; }
int qm_ss_spi_transfer(const qm_ss_spi_t spi, const qm_ss_spi_transfer_t *const xfer, qm_ss_spi_status_t *const status) { QM_CHECK(spi < QM_SS_SPI_NUM, -EINVAL); QM_CHECK(xfer, -EINVAL); uint32_t ctrl = __builtin_arc_lr(base[spi] + QM_SS_SPI_CTRL); uint8_t tmode = (uint8_t)((ctrl & QM_SS_SPI_CTRL_TMOD_MASK) >> QM_SS_SPI_CTRL_TMOD_OFFS); QM_CHECK(tmode == QM_SS_SPI_TMOD_TX_RX ? (xfer->tx_len == xfer->rx_len) : 1, -EINVAL); QM_CHECK(tmode == QM_SS_SPI_TMOD_TX ? (xfer->rx_len == 0) : 1, -EINVAL); QM_CHECK(tmode == QM_SS_SPI_TMOD_EEPROM_READ ? (xfer->rx_len > 0) : 1, -EINVAL); QM_CHECK(tmode == QM_SS_SPI_TMOD_RX ? (xfer->rx_len > 0) : 1, -EINVAL); QM_CHECK(tmode == QM_SS_SPI_TMOD_RX ? (xfer->tx_len == 0) : 1, -EINVAL); uint32_t tx_cnt = xfer->tx_len; uint32_t rx_cnt = xfer->rx_len; uint8_t *rx_buffer = xfer->rx; uint8_t *tx_buffer = xfer->tx; int ret = 0; /* Disable all SPI interrupts */ __builtin_arc_sr(0, base[spi] + QM_SS_SPI_INTR_MASK); /* Set NDF (Number of Data Frames) in RX or EEPROM Read mode. (-1) */ if (tmode == QM_SS_SPI_TMOD_RX || tmode == QM_SS_SPI_TMOD_EEPROM_READ) { ctrl &= ~QM_SS_SPI_CTRL_NDF_MASK; ctrl |= ((xfer->rx_len - 1) << QM_SS_SPI_CTRL_NDF_OFFS) & QM_SS_SPI_CTRL_NDF_MASK; __builtin_arc_sr(ctrl, base[spi] + QM_SS_SPI_CTRL); } /* RX only transfers need a dummy frame to be sent. */ if (tmode == QM_SS_SPI_TMOD_RX) { tx_buffer = (uint8_t *)&dummy_frame; tx_cnt = 1; } /* Calculate number of bytes per frame (1 or 2)*/ uint8_t bytes = BYTES_PER_FRAME(ctrl); /* Enable SPI device */ QM_SS_REG_AUX_OR(base[spi] + QM_SS_SPI_SPIEN, QM_SS_SPI_SPIEN_EN); while (tx_cnt || rx_cnt) { uint32_t sr = __builtin_arc_lr(base[spi] + QM_SS_SPI_SR); /* Break and report error if RX FIFO has overflown */ if (__builtin_arc_lr(base[spi] + QM_SS_SPI_INTR_STAT) & QM_SS_SPI_INTR_RXOI) { ret = -EIO; if (status) { *status |= QM_SS_SPI_RX_OVERFLOW; } break; } /* Copy data to buffer as long RX-FIFO is not empty */ if (sr & QM_SS_SPI_SR_RFNE && rx_cnt) { fifo_read(spi, rx_buffer, bytes); rx_buffer += bytes; rx_cnt--; } /* Copy data from buffer as long TX-FIFO is not full. */ if (sr & QM_SS_SPI_SR_TFNF && tx_cnt) { fifo_write(spi, tx_buffer, bytes); tx_buffer += bytes; tx_cnt--; } } /* Wait for last byte transfered */ while (__builtin_arc_lr(base[spi] + QM_SS_SPI_SR) & QM_SS_SPI_SR_BUSY) ; spi_disable(spi); return ret; }