/** * @brief This function handles RCC interrupt request. * @param None * @retval None */ void RCC_IRQHandler(void) { if(RCC_GetITStatus(RCC_IT_HSERDY) != RESET) { /* Clear HSERDY interrupt pending bit */ RCC_ClearITPendingBit(RCC_IT_HSERDY); /* Check if the HSE clock is still available */ if (RCC_GetFlagStatus(RCC_FLAG_HSERDY) != RESET) { #ifdef SYSCLK_HSE /* Select HSE as system clock source */ RCC_SYSCLKConfig(RCC_SYSCLKSource_HSE); #else #ifdef STM32F10X_CL /* Enable PLL2 */ RCC_PLL2Cmd(ENABLE); #else /* Enable PLL: once the PLL is ready the PLLRDY interrupt is generated */ RCC_PLLCmd(ENABLE); #endif /* STM32F10X_CL */ #endif /* SYSCLK_HSE */ } } #ifdef STM32F10X_CL if(RCC_GetITStatus(RCC_IT_PLL2RDY) != RESET) { /* Clear PLL2RDY interrupt pending bit */ RCC_ClearITPendingBit(RCC_IT_PLL2RDY); /* Enable PLL: once the PLL is ready the PLLRDY interrupt is generated */ RCC_PLLCmd(ENABLE); } #endif /* STM32F10X_CL */ if(RCC_GetITStatus(RCC_IT_PLLRDY) != RESET) { /* Clear PLLRDY interrupt pending bit */ RCC_ClearITPendingBit(RCC_IT_PLLRDY); /* Check if the PLL is still locked */ if (RCC_GetFlagStatus(RCC_FLAG_PLLRDY) != RESET) { /* Select PLL as system clock source */ RCC_SYSCLKConfig(RCC_SYSCLKSource_PLLCLK); } } }
void SYSCLKConfig_STOP(void) { ErrorStatus HSEStartUpStatus; /* Enable HSE */ RCC_HSEConfig(RCC_HSE_ON); /* Wait till HSE is ready */ HSEStartUpStatus = RCC_WaitForHSEStartUp(); if(HSEStartUpStatus == SUCCESS) { #ifdef STM32F10X_CL /* Enable PLL2 */ RCC_PLL2Cmd(ENABLE); /* Wait till PLL2 is ready */ while(RCC_GetFlagStatus(RCC_FLAG_PLL2RDY) == RESET) { } #endif /* Enable PLL */ RCC_PLLCmd(ENABLE); /* Wait till PLL is ready */ while(RCC_GetFlagStatus(RCC_FLAG_PLLRDY) == RESET) { } /* Select PLL as system clock source */ RCC_SYSCLKConfig(RCC_SYSCLKSource_PLLCLK); /* Wait till PLL is used as system clock source */ while(RCC_GetSYSCLKSource() != 0x08) { } } }
/******************************************************************************* * Function Name : Set_System * Description : Configures Main system clocks & power * Input : None. * Return : None. *******************************************************************************/ void Set_System(void) { GPIO_InitTypeDef GPIO_InitStructure; /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration -----------------------------*/ /* RCC system reset(for debug purpose) */ RCC_DeInit(); /* Enable HSE */ RCC_HSEConfig(RCC_HSE_ON); /* Wait till HSE is ready */ HSEStartUpStatus = RCC_WaitForHSEStartUp(); if (HSEStartUpStatus == SUCCESS) { /* Enable Prefetch Buffer */ FLASH_PrefetchBufferCmd(FLASH_PrefetchBuffer_Enable); /* Flash 2 wait state */ FLASH_SetLatency(FLASH_Latency_2); /* HCLK = SYSCLK */ RCC_HCLKConfig(RCC_SYSCLK_Div1); /* PCLK2 = HCLK */ RCC_PCLK2Config(RCC_HCLK_Div1); /* PCLK1 = HCLK/2 */ RCC_PCLK1Config(RCC_HCLK_Div2); #ifdef STM32F10X_CL /* Configure PLLs *********************************************************/ /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */ RCC_PREDIV2Config(RCC_PREDIV2_Div5); RCC_PLL2Config(RCC_PLL2Mul_8); /* Enable PLL2 */ RCC_PLL2Cmd(ENABLE); /* Wait till PLL2 is ready */ while (RCC_GetFlagStatus(RCC_FLAG_PLL2RDY) == RESET) {} /* PLL configuration: PLLCLK = (PLL2 / 5) * 9 = 72 MHz */ RCC_PREDIV1Config(RCC_PREDIV1_Source_PLL2, RCC_PREDIV1_Div5); RCC_PLLConfig(RCC_PLLSource_PREDIV1, RCC_PLLMul_9); #else /* PLLCLK = 8MHz * 9 = 72 MHz */ RCC_PLLConfig(RCC_PLLSource_HSE_Div1, RCC_PLLMul_9); #endif /* Enable PLL */ RCC_PLLCmd(ENABLE); /* Wait till PLL is ready */ while (RCC_GetFlagStatus(RCC_FLAG_PLLRDY) == RESET) { } /* Select PLL as system clock source */ RCC_SYSCLKConfig(RCC_SYSCLKSource_PLLCLK); /* Wait till PLL is used as system clock source */ while(RCC_GetSYSCLKSource() != 0x08) { } } else { /* If HSE fails to start-up, the application will have wrong clock configuration. User can add here some code to deal with this error */ /* Go to infinite loop */ while (1) { } } /* Enable USB_DISCONNECT GPIO clock */ RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIO_DISCONNECT, ENABLE); RCC_APB2PeriphClockCmd(RCC_APB2Periph_AFIO, ENABLE); RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOC | RCC_APB2Periph_GPIOA, ENABLE); /* Configure USB pull-up pin - PC11 */ GPIO_InitStructure.GPIO_Pin = GPIO_Pin_11; GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_OD; GPIO_Init(GPIOC, &GPIO_InitStructure); /* Configure status LED - PC12 */ GPIO_InitStructure.GPIO_Pin = GPIO_Pin_12; GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP; GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; GPIO_Init(GPIOC, &GPIO_InitStructure); }
/** * @brief Configures the different system clocks. * @param None * @retval None */ void RCC_Configuration(void) { /* RCC system reset(for debug purpose) */ RCC_DeInit(); /* Enable HSE */ RCC_HSEConfig(RCC_HSE_ON); /* Wait till HSE is ready */ HSEStartUpStatus = RCC_WaitForHSEStartUp(); if(HSEStartUpStatus == SUCCESS) { /* Enable Prefetch Buffer */ FLASH_PrefetchBufferCmd(FLASH_PrefetchBuffer_Enable); /* Flash 2 wait state */ FLASH_SetLatency(FLASH_Latency_2); /* HCLK = SYSCLK */ RCC_HCLKConfig(RCC_SYSCLK_Div1); /* PCLK2 = HCLK */ RCC_PCLK2Config(RCC_HCLK_Div1); /* PCLK1 = HCLK/2 */ RCC_PCLK1Config(RCC_HCLK_Div2); /* ADCCLK = PCLK2/4 */ RCC_ADCCLKConfig(RCC_PCLK2_Div4); #ifndef STM32F10X_CL /* PLLCLK = 8MHz * 7 = 56 MHz */ RCC_PLLConfig(RCC_PLLSource_HSE_Div1, RCC_PLLMul_7); #else /* Configure PLLs *********************************************************/ /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */ RCC_PREDIV2Config(RCC_PREDIV2_Div5); RCC_PLL2Config(RCC_PLL2Mul_8); /* Enable PLL2 */ RCC_PLL2Cmd(ENABLE); /* Wait till PLL2 is ready */ while (RCC_GetFlagStatus(RCC_FLAG_PLL2RDY) == RESET) {} /* PLL configuration: PLLCLK = (PLL2 / 5) * 7 = 56 MHz */ RCC_PREDIV1Config(RCC_PREDIV1_Source_PLL2, RCC_PREDIV1_Div5); RCC_PLLConfig(RCC_PLLSource_PREDIV1, RCC_PLLMul_7); #endif /* Enable PLL */ RCC_PLLCmd(ENABLE); /* Wait till PLL is ready */ while(RCC_GetFlagStatus(RCC_FLAG_PLLRDY) == RESET) { } /* Select PLL as system clock source */ RCC_SYSCLKConfig(RCC_SYSCLKSource_PLLCLK); /* Wait till PLL is used as system clock source */ while(RCC_GetSYSCLKSource() != 0x08) { } } /* Enable peripheral clocks --------------------------------------------------*/ /* Enable ADC1 and GPIO_LED clock */ RCC_APB2PeriphClockCmd(RCC_APB2Periph_ADC1, ENABLE); }
/** * @brief Configures the different system clocks. * @param None * @retval None */ void RCC_Configuration(void) { /* RCC system reset(for debug purpose) */ RCC_DeInit(); /* Enable HSE */ RCC_HSEConfig(RCC_HSE_ON); /* Wait till HSE is ready */ HSEStartUpStatus = RCC_WaitForHSEStartUp(); if(HSEStartUpStatus == SUCCESS) { /* Enable Prefetch Buffer */ FLASH_PrefetchBufferCmd(FLASH_PrefetchBuffer_Enable); /* Flash 2 wait state */ FLASH_SetLatency(FLASH_Latency_2); /* HCLK = SYSCLK */ RCC_HCLKConfig(RCC_SYSCLK_Div1); /* PCLK2 = HCLK */ RCC_PCLK2Config(RCC_HCLK_Div1); /* PCLK1 = HCLK/2 */ RCC_PCLK1Config(RCC_HCLK_Div2); /* ADCCLK = PCLK2/4 */ RCC_ADCCLKConfig(RCC_PCLK2_Div4); #ifndef STM32F10X_CL /* PLLCLK = 8MHz * 9 = 72 MHz */ RCC_PLLConfig(RCC_PLLSource_HSE_Div1, RCC_PLLMul_9); #else /* Configure PLLs *********************************************************/ /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */ RCC_PREDIV2Config(RCC_PREDIV2_Div5); RCC_PLL2Config(RCC_PLL2Mul_8); /* Enable PLL2 */ RCC_PLL2Cmd(ENABLE); /* Wait till PLL2 is ready */ while (RCC_GetFlagStatus(RCC_FLAG_PLL2RDY) == RESET) {} /* PLL configuration: PLLCLK = (PLL2 / 5) * 9 = 72 MHz */ RCC_PREDIV1Config(RCC_PREDIV1_Source_PLL2, RCC_PREDIV1_Div5); RCC_PLLConfig(RCC_PLLSource_PREDIV1, RCC_PLLMul_9); /* PPL3 configuration: PLL3CLK = (HSE / 5) * 11 = PLL3_VCO = 110 MHz */ RCC_PLL3Config(RCC_PLL3Mul_11); /* Enable PLL3 */ RCC_PLL3Cmd(ENABLE); /* Wait till PLL3 is ready */ while (RCC_GetFlagStatus(RCC_FLAG_PLL3RDY) == RESET) {} /* Configure I2S clock source: On Connectivity-Line Devices, the I2S can be clocked by PLL3 VCO instead of SYS_CLK in order to guarantee higher precision */ RCC_I2S3CLKConfig(RCC_I2S3CLKSource_PLL3_VCO); RCC_I2S2CLKConfig(RCC_I2S2CLKSource_PLL3_VCO); #endif /* Enable PLL */ RCC_PLLCmd(ENABLE); /* Wait till PLL is ready */ while(RCC_GetFlagStatus(RCC_FLAG_PLLRDY) == RESET) { } /* Select PLL as system clock source */ RCC_SYSCLKConfig(RCC_SYSCLKSource_PLLCLK); /* Wait till PLL is used as system clock source */ while(RCC_GetSYSCLKSource() != 0x08) { } } /* Enable peripheral clocks --------------------------------------------------*/ /* GPIOA, GPIOB and AFIO clocks enable */ RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOA | RCC_APB2Periph_GPIOB | RCC_APB2Periph_AFIO, ENABLE); #ifdef USE_STM3210C_EVAL /* GPIOC Clock enable (for the SPI3 remapped pins) */ RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOC , ENABLE); #endif /* USE_STM3210C_EVAL */ /* SPI2 and SPI3 clocks enable */ RCC_APB1PeriphClockCmd(RCC_APB1Periph_SPI2 | RCC_APB1Periph_SPI3, ENABLE); }
void BSP_Init (void) { //gpc 2-2-2011 BSP_IntInit(); RCC_DeInit(); RCC_HSEConfig(RCC_HSE_ON); /* HSE = 25MHz ext. crystal. */ RCC_WaitForHSEStartUp(); RCC_PREDIV2Config(RCC_PREDIV2_Div5); /* Fprediv2 = HSE / 5 = 5MHz. */ RCC_PLL2Config(RCC_PLL2Mul_8); /* PLL2 = Fprediv2 * 8 = 40MHz. */ RCC_PLL2Cmd(ENABLE); RCC_PLL3Config(RCC_PLL3Mul_10); /* PLL3 = Fprediv2 * 10 = 50MHz. */ RCC_PLL3Cmd(ENABLE); RCC_HCLKConfig(RCC_SYSCLK_Div1); /* HCLK = AHBCLK = PLL1 / AHBPRES(1) = 72MHz. */ RCC_PCLK2Config(RCC_HCLK_Div1); /* APB2CLK = AHBCLK / APB2DIV(1) = 72MHz. */ RCC_PCLK1Config(RCC_HCLK_Div2); /* APB1CLK = AHBCLK / APB1DIV(2) = 36MHz (max). */ RCC_ADCCLKConfig(RCC_PCLK2_Div6); /* ADCCLK = AHBCLK / APB2DIV / 6 = 12MHz. */ RCC_OTGFSCLKConfig(RCC_OTGFSCLKSource_PLL1VCO_Div3); /* OTGCLK = PLL1VCO / USBPRES(3) = 144MHz / 3 = 48MHz */ FLASH_SetLatency(FLASH_Latency_2); /* 2 Flash wait states when HCLK > 48MHz. */ FLASH_PrefetchBufferCmd(FLASH_PrefetchBuffer_Enable); while (RCC_GetFlagStatus(RCC_FLAG_PLL2RDY) == RESET) { /* Wait for PLL2 to lock. */ ; } while (RCC_GetFlagStatus(RCC_FLAG_PLL3RDY) == RESET) { /* Wait for PLL3 to lock. */ ; } /* Fprediv1 = PLL2 / 5 = 8MHz. */ RCC_PREDIV1Config(RCC_PREDIV1_Source_PLL2, RCC_PREDIV1_Div5); RCC_PLL1Config(RCC_PLL1Source_PREDIV1, RCC_PLL1Mul_9); /* PLL1 = Fprediv1 * 9 = 72Mhz. */ RCC_PLL1Cmd(ENABLE); while (RCC_GetFlagStatus(RCC_FLAG_PLL1RDY) == RESET) { /* Wait for PLL1 to lock. */ ; } RCC_SYSCLKConfig(RCC_SYSCLKSource_PLL1CLK); /* HCLK = SYSCLK = PLL1 = 72MHz. */ while (RCC_GetSYSCLKSource() != 0x08) { ; } BSP_CPU_ClkFreq_MHz = BSP_CPU_ClkFreq() / (CPU_INT32U)1000000; BSP_CPU_ClkFreq_MHz = BSP_CPU_ClkFreq_MHz; /* Surpress compiler warning BSP_CPU_ClkFreq_MHz ... */ /* ... set and not used. */ BSP_LED_Init(); /* Initialize the I/Os for the LED controls. */ BSP_StatusInit(); /* Initialize the status input(s) */ #ifdef TRACE_EN /* See project / compiler preprocessor options. */ DBGMCU_CR |= DBGMCU_CR_TRACE_IOEN_MASK; /* Enable tracing (see Note #2). */ DBGMCU_CR &= ~DBGMCU_CR_TRACE_MODE_MASK; /* Clr trace mode sel bits. */ DBGMCU_CR |= DBGMCU_CR_TRACE_MODE_SYNC_04; /* Cfg trace mode to synch 4-bit. */ #endif }
/** * @brief Sets System clock frequency to 72MHz and configure HCLK, PCLK2 * and PCLK1 prescalers. * @param None * @retval None */ void SetSysClockTo72(void) { /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration -----------------------------*/ /* RCC system reset(for debug purpose) */ RCC_DeInit(); /* Enable HSE */ RCC_HSEConfig(RCC_HSE_ON); /* Wait till HSE is ready */ HSEStartUpStatus = RCC_WaitForHSEStartUp(); if (HSEStartUpStatus == SUCCESS) { /* Enable Prefetch Buffer */ FLASH_PrefetchBufferCmd(FLASH_PrefetchBuffer_Enable); /* Flash 2 wait state */ FLASH_SetLatency(FLASH_Latency_2); /* HCLK = SYSCLK */ RCC_HCLKConfig(RCC_SYSCLK_Div1); /* PCLK2 = HCLK */ RCC_PCLK2Config(RCC_HCLK_Div1); /* PCLK1 = HCLK/2 */ RCC_PCLK1Config(RCC_HCLK_Div2); #ifdef STM32F10X_CL /* Configure PLLs *********************************************************/ /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */ RCC_PREDIV2Config(RCC_PREDIV2_Div5); RCC_PLL2Config(RCC_PLL2Mul_8); /* Enable PLL2 */ RCC_PLL2Cmd(ENABLE); /* Wait till PLL2 is ready */ while (RCC_GetFlagStatus(RCC_FLAG_PLL2RDY) == RESET) {} /* PLL configuration: PLLCLK = (PLL2 / 5) * 9 = 72 MHz */ RCC_PREDIV1Config(RCC_PREDIV1_Source_PLL2, RCC_PREDIV1_Div5); RCC_PLLConfig(RCC_PLLSource_PREDIV1, RCC_PLLMul_9); #else /* PLLCLK = 8MHz * 9 = 72 MHz */ RCC_PLLConfig(RCC_PLLSource_HSE_Div1, RCC_PLLMul_9); #endif /* Enable PLL */ RCC_PLLCmd(ENABLE); /* Wait till PLL is ready */ while (RCC_GetFlagStatus(RCC_FLAG_PLLRDY) == RESET) { } /* Select PLL as system clock source */ RCC_SYSCLKConfig(RCC_SYSCLKSource_PLLCLK); /* Wait till PLL is used as system clock source */ while(RCC_GetSYSCLKSource() != 0x08) { } } else { /* If HSE fails to start-up, the application will have wrong clock configuration. User can add here some code to deal with this error */ /* Go to infinite loop */ while (1) { } } }
//配置系统时钟 void RCC_Configuration(void){ //定义枚举类型变量 ErrorStatus HSEStartUpStatus; /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration -----------*/ /* RCC system reset(for debug purpose) */ //复位系统时钟设置 RCC_DeInit(); /* Enable HSE */ //开启HSE时钟 RCC_HSEConfig(RCC_HSE_ON); /* Wait till HSE is ready */ //等待HSE起振并稳定 HSEStartUpStatus=RCC_WaitForHSEStartUp(); //判断HSE是否起振成功 if(HSEStartUpStatus == SUCCESS){ /* Enable Prefetch Buffer */ //使能预取缓冲 FLASH_PrefetchBufferCmd(FLASH_PrefetchBuffer_Enable); /* Flash 2 wait state */ //设置flash延时周期数为2 FLASH_SetLatency(FLASH_Latency_2); /* HCLK = SYSCLK */ //HCLK(AHB)时钟源为SYSCLK, HSE 1分频 RCC_HCLKConfig(RCC_SYSCLK_Div1); /* PCLK2 = HCLK */ //PCLK2时钟源为HCLK(AHB) 1分频 RCC_PCLK2Config(RCC_HCLK_Div1); /* PCLK1 = HCLK/2 */ //PCLK1时钟源为HCLK(AHB) 1分频 RCC_PCLK1Config(RCC_HCLK_Div1); /* Configure PLLs ***********************/ /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */ //cl芯片,默认外部时钟是25M //PLL2时钟源为HSE, 预分频数为5,倍频数为8 //则PLL2输出频率为25M/5 * 8 = 40M RCC_PREDIV2Config(RCC_PREDIV2_Div5); //由PLL2进行8倍频 RCC_PLL2Config(RCC_PLL2Mul_8); /* Enable PLL2 */ //使能PLL2 RCC_PLL2Cmd(ENABLE); /* Wait till PLL2 is ready */ //等待PLL2输出稳定 while (RCC_GetFlagStatus(RCC_FLAG_PLL2RDY) == RESET) {} /* PLL configuration: PLLCLK = (PLL2 / 5) * 9 = 72 MHz */ //对PLL2进行5倍预分频 RCC_PREDIV1Config(RCC_PREDIV1_Source_PLL2, RCC_PREDIV1_Div5); //再用PLL进行9倍频 RCC_PLLConfig(RCC_PLLSource_PREDIV1, RCC_PLLMul_9); /* Enable PLL */ //使能PLL RCC_PLLCmd(ENABLE); /* Wait till PLL is ready */ //等待PLL输出稳定 while (RCC_GetFlagStatus(RCC_FLAG_PLLRDY) == RESET){ } /* Select PLL as system clock source */ //选择PLL为系统时钟源 RCC_SYSCLKConfig(RCC_SYSCLKSource_PLLCLK); /* Wait till PLL is used as system clock source */ //等待PLL准备好 while(RCC_GetSYSCLKSource() != 0x08) { } } //4个LED对应PE2~PE5 //因此要使能APB2总线上的GPIOE时钟 //其他均在GPIO中配置 RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOE, ENABLE); RCC_APB1PeriphClockCmd(RCC_APB1Periph_TIM2 | RCC_APB1Periph_TIM3, ENABLE); }
void configureSystem(void) { /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration -----------------------------*/ /* RCC system reset(for debug purpose) */ RCC_DeInit(); /* Enable HSE */ RCC_HSEConfig(RCC_HSE_ON); /* Wait till HSE is ready */ ErrorStatus HSEStartUpStatus = RCC_WaitForHSEStartUp(); if (HSEStartUpStatus == SUCCESS) { /* Enable Prefetch Buffer */ FLASH->ACR |= FLASH_ACR_PRFTBE; /* Flash 2 wait state */ FLASH->ACR &= (uint32_t) ((uint32_t) ~FLASH_ACR_LATENCY); FLASH->ACR |= (uint32_t) FLASH_ACR_LATENCY_2; /* HCLK = SYSCLK */ RCC_HCLKConfig(RCC_SYSCLK_Div1); /* PCLK2 = HCLK */ RCC_PCLK2Config(RCC_HCLK_Div1); /* PCLK1 = HCLK/2 */ RCC_PCLK1Config(RCC_HCLK_Div2); // PLL configuration: PLLCLK /* Configure PLLs *********************************************************/ /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */ //RCC_PREDIV2Config(RCC_PREDIV2_Div5); //RCC_PLL2Config(RCC_PLL2Mul_8); /* PLL2 configuration: PLL2CLK = (HSE / 4) * 20 = 40 MHz */ RCC_PREDIV2Config(RCC_PREDIV2_Div4); RCC_PLL2Config(RCC_PLL2Mul_20); // Enable PLL2 RCC_PLL2Cmd(ENABLE); // Wait till PLL2 is ready while (RCC_GetFlagStatus(RCC_FLAG_PLL2RDY) == RESET) { } // PLL configuration: PLLCLK = (PLL2 / 5) * 9 = 72 MHz * RCC_PREDIV1Config(RCC_PREDIV1_Source_PLL2, RCC_PREDIV1_Div5); RCC_PLLConfig(RCC_PLLSource_PREDIV1, RCC_PLLMul_9); /* Enable PLL */ RCC_PLLCmd(ENABLE); /* Wait till PLL is ready */ while (RCC_GetFlagStatus(RCC_FLAG_PLLRDY) == RESET) { } /* Select PLL as system clock source */ RCC_SYSCLKConfig(RCC_SYSCLKSource_PLLCLK); /* Wait till PLL is used as system clock source */ while (RCC_GetSYSCLKSource() != 0x08) { } } else { /* If HSE fails to start-up, the application will have wrong clock configuration. User can add here some code to deal with this error */ /* Go to infinite loop */ while (1) { } } rtc_init(); configureNVIC(); SysTick_Config(72000); }
/******************************************************************************* * Function Name : Set_System * Description : Configures Main system clocks & power * Input : None. * Return : None. *******************************************************************************/ void Set_System(void) { /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration -----------------------------*/ /* RCC system reset(for debug purpose) */ RCC_DeInit(); /* Enable HSE */ RCC_HSEConfig(RCC_HSE_ON); /* Wait till HSE is ready */ HSEStartUpStatus = RCC_WaitForHSEStartUp(); if (HSEStartUpStatus == SUCCESS) { /* Enable Prefetch Buffer */ FLASH_PrefetchBufferCmd(FLASH_PrefetchBuffer_Enable); /* Flash 2 wait state */ FLASH_SetLatency(FLASH_Latency_2); /* HCLK = SYSCLK */ RCC_HCLKConfig(RCC_SYSCLK_Div1); /* PCLK2 = HCLK */ RCC_PCLK2Config(RCC_HCLK_Div1); /* PCLK1 = HCLK/2 */ RCC_PCLK1Config(RCC_HCLK_Div2); #ifdef STM32F10X_CL /* Configure PLLs *********************************************************/ #ifdef EXTERNAL_CRYSTAL_25MHz /* PLL2 configuration: PLL2CLK = (HSE / 9) * 13 = 36.111 MHz */ RCC_PREDIV2Config(RCC_PREDIV2_Div9); RCC_PLL2Config(RCC_PLL2Mul_13); /* Enable PLL2 */ RCC_PLL2Cmd(ENABLE); /* Wait till PLL2 is ready */ while (RCC_GetFlagStatus(RCC_FLAG_PLL2RDY) == RESET) {} /* PPL3 configuration: PLL3CLK = (HSE / 9) * 14 = PLL3_VCO = 77.777 MHz */ RCC_PLL3Config(RCC_PLL3Mul_14); /* Enable PLL3 */ RCC_PLL3Cmd(ENABLE); /* Wait till PLL3 is ready */ while (RCC_GetFlagStatus(RCC_FLAG_PLL3RDY) == RESET) {} /* PLL configuration: PLLCLK = (PLL2 / 4) * 8 = 72.222 MHz */ RCC_PREDIV1Config(RCC_PREDIV1_Source_PLL2, RCC_PREDIV1_Div4); RCC_PLLConfig(RCC_PLLSource_PREDIV1, RCC_PLLMul_8); #elif defined (EXTERNAL_CRYSTAL_14_7456MHz) /* PLL2 configuration: PLL2CLK = (HSE / 4) * 13 = 47.932 MHz */ RCC_PREDIV2Config(RCC_PREDIV2_Div4); RCC_PLL2Config(RCC_PLL2Mul_13); /* Enable PLL2 */ RCC_PLL2Cmd(ENABLE); /* Wait till PLL2 is ready */ while (RCC_GetFlagStatus(RCC_FLAG_PLL2RDY) == RESET) {} /* PPL3 configuration: PLL3CLK = (HSE / 4) * 20 = PLL3_VCO = 147.456 MHz */ RCC_PLL3Config(RCC_PLL3Mul_20); /* Enable PLL3 */ RCC_PLL3Cmd(ENABLE); /* Wait till PLL3 is ready */ while (RCC_GetFlagStatus(RCC_FLAG_PLL3RDY) == RESET) {} /* PPL1 configuration: PLL1CLK = (PLL2 / 4) * 6 = 71.8848 MHz */ RCC_PREDIV1Config(RCC_PREDIV1_Source_PLL2, RCC_PREDIV1_Div4); RCC_PLLConfig(RCC_PLLSource_PREDIV1, RCC_PLLMul_6); #endif /* EXTERNAL_CRYSTAL_25MHz */ /* Configure I2S clock source: PLL3 VCO clock */ RCC_I2S2CLKConfig(RCC_I2S2CLKSource_PLL3_VCO); #else /* PLLCLK = 8MHz * 9 = 72 MHz */ RCC_PLLConfig(RCC_PLLSource_HSE_Div1, RCC_PLLMul_9); #endif /* STM32F10X_CL */ /* Enable PLL */ RCC_PLLCmd(ENABLE); /* Wait till PLL is ready */ while (RCC_GetFlagStatus(RCC_FLAG_PLLRDY) == RESET) { } /* Select PLL as system clock source */ RCC_SYSCLKConfig(RCC_SYSCLKSource_PLLCLK); /* Wait till PLL is used as system clock source */ while(RCC_GetSYSCLKSource() != 0x08) { } } else { /* If HSE fails to start-up, the application will have wrong clock configuration. User can add here some code to deal with this error */ /* Go to infinite loop */ while (1) { } } }