static void s_hal_brdcfg_device_switch__mco_initialise(void)
{
// this function initialises MCO in order to provide clock ref to switch.
// PA8 is MCO. it must be configured = Output mode, max speed 50 MHz + Alternate function output Push-pull (B)
// also, we connect pll3 at 50mhz to it
// clock gpioa as alternate function
RCC->APB2ENR |= 0x00000005;
// init pa8
GPIOA->CRH &= 0xFFFFFFF0;
GPIOA->CRH |= 0x0000000B;
// set pll3 clock output to 50mhz: (25mhz/5)*10 = 50mhz, thus we use multiplier 10
RCC_PLL3Config(RCC_PLL3Mul_10);
// enable pll3
RCC_PLL3Cmd(ENABLE);
// wait until it is ready
while(RCC_GetFlagStatus(RCC_FLAG_PLL3RDY) == RESET);
// connect mco on pa8 with pll3
RCC_MCOConfig(RCC_MCO_PLL3CLK);
}
void GPIO_ENETConfiguration(void)
{
RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOE, ENABLE);
GPIO_InitTypeDef GPIO_InitStructure;
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_2;
GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
GPIO_Init(GPIOA, &GPIO_InitStructure);
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_1 ;
GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
GPIO_Init(GPIOC, &GPIO_InitStructure);
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_11 | GPIO_Pin_12 | GPIO_Pin_13;
GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
GPIO_Init(GPIOB, &GPIO_InitStructure);
/* Configure PA1 and PA7 as input */
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_1 | GPIO_Pin_7;
GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;
GPIO_Init(GPIOA, &GPIO_InitStructure);
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_4 | GPIO_Pin_5;
GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;
GPIO_Init(GPIOC, &GPIO_InitStructure);
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_8;
GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
GPIO_Init(GPIOA, &GPIO_InitStructure);
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_9;
GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP;
GPIO_Init(GPIOE, &GPIO_InitStructure);
GPIO_WriteBit(GPIOE, GPIO_Pin_9, Bit_SET);
RCC_PLL3Config(RCC_PLL3Mul_10);
RCC_PLL3Cmd(ENABLE);
while (RCC_GetFlagStatus(RCC_FLAG_PLL3RDY) == RESET);
RCC_MCOConfig(RCC_MCO_PLL3CLK);
}
/**
* @brief Configures the different system clocks.
* @param None
* @retval None
*/
void RCC_Configuration(void)
{
/* RCC system reset(for debug purpose) */
RCC_DeInit();
/* Enable HSE */
RCC_HSEConfig(RCC_HSE_ON);
/* Wait till HSE is ready */
HSEStartUpStatus = RCC_WaitForHSEStartUp();
if(HSEStartUpStatus == SUCCESS)
{
/* Enable Prefetch Buffer */
FLASH_PrefetchBufferCmd(FLASH_PrefetchBuffer_Enable);
/* Flash 2 wait state */
FLASH_SetLatency(FLASH_Latency_2);
/* HCLK = SYSCLK */
RCC_HCLKConfig(RCC_SYSCLK_Div1);
/* PCLK2 = HCLK */
RCC_PCLK2Config(RCC_HCLK_Div1);
/* PCLK1 = HCLK/2 */
RCC_PCLK1Config(RCC_HCLK_Div2);
/* ADCCLK = PCLK2/4 */
RCC_ADCCLKConfig(RCC_PCLK2_Div4);
#ifndef STM32F10X_CL
/* PLLCLK = 8MHz * 9 = 72 MHz */
RCC_PLLConfig(RCC_PLLSource_HSE_Div1, RCC_PLLMul_9);
#else
/* Configure PLLs *********************************************************/
/* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
RCC_PREDIV2Config(RCC_PREDIV2_Div5);
RCC_PLL2Config(RCC_PLL2Mul_8);
/* Enable PLL2 */
RCC_PLL2Cmd(ENABLE);
/* Wait till PLL2 is ready */
while (RCC_GetFlagStatus(RCC_FLAG_PLL2RDY) == RESET)
{}
/* PLL configuration: PLLCLK = (PLL2 / 5) * 9 = 72 MHz */
RCC_PREDIV1Config(RCC_PREDIV1_Source_PLL2, RCC_PREDIV1_Div5);
RCC_PLLConfig(RCC_PLLSource_PREDIV1, RCC_PLLMul_9);
/* PPL3 configuration: PLL3CLK = (HSE / 5) * 11 = PLL3_VCO = 110 MHz */
RCC_PLL3Config(RCC_PLL3Mul_11);
/* Enable PLL3 */
RCC_PLL3Cmd(ENABLE);
/* Wait till PLL3 is ready */
while (RCC_GetFlagStatus(RCC_FLAG_PLL3RDY) == RESET)
{}
/* Configure I2S clock source: On Connectivity-Line Devices, the I2S can be
clocked by PLL3 VCO instead of SYS_CLK in order to guarantee higher
precision */
RCC_I2S3CLKConfig(RCC_I2S3CLKSource_PLL3_VCO);
RCC_I2S2CLKConfig(RCC_I2S2CLKSource_PLL3_VCO);
#endif
/* Enable PLL */
RCC_PLLCmd(ENABLE);
/* Wait till PLL is ready */
while(RCC_GetFlagStatus(RCC_FLAG_PLLRDY) == RESET)
{
}
/* Select PLL as system clock source */
RCC_SYSCLKConfig(RCC_SYSCLKSource_PLLCLK);
/* Wait till PLL is used as system clock source */
while(RCC_GetSYSCLKSource() != 0x08)
{
}
}
/* Enable peripheral clocks --------------------------------------------------*/
/* GPIOA, GPIOB and AFIO clocks enable */
RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOA | RCC_APB2Periph_GPIOB |
RCC_APB2Periph_AFIO, ENABLE);
#ifdef USE_STM3210C_EVAL
/* GPIOC Clock enable (for the SPI3 remapped pins) */
RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOC , ENABLE);
#endif /* USE_STM3210C_EVAL */
/* SPI2 and SPI3 clocks enable */
RCC_APB1PeriphClockCmd(RCC_APB1Periph_SPI2 | RCC_APB1Periph_SPI3, ENABLE);
}
/**
* @brief Configures the Ethernet Interface
* @param None
* @retval None
*/
void Ethernet_Configuration(void)
{
ETH_InitTypeDef ETH_InitStructure;
/* MII/RMII Media interface selection ------------------------------------------*/
#ifdef MII_MODE /* Mode MII with STM3210C-EVAL */
GPIO_ETH_MediaInterfaceConfig(GPIO_ETH_MediaInterface_MII);
/* Get HSE clock = 25MHz on PA8 pin (MCO) */
RCC_MCOConfig(RCC_MCO_HSE);
#elif defined RMII_MODE /* Mode RMII with STM3210C-EVAL */
GPIO_ETH_MediaInterfaceConfig(GPIO_ETH_MediaInterface_RMII);
/* Set PLL3 clock output to 50MHz (25MHz /5 *10 =50MHz) */
RCC_PLL3Config(RCC_PLL3Mul_10);
/* Enable PLL3 */
RCC_PLL3Cmd(ENABLE);
/* Wait till PLL3 is ready */
while (RCC_GetFlagStatus(RCC_FLAG_PLL3RDY) == RESET)
{}
/* Get PLL3 clock on PA8 pin (MCO) */
RCC_MCOConfig(RCC_MCO_PLL3CLK);
#endif
/* Reset ETHERNET on AHB Bus */
ETH_DeInit();
/* Software reset */
ETH_SoftwareReset();
/* Wait for software reset */
while (ETH_GetSoftwareResetStatus() == SET);
/* ETHERNET Configuration ------------------------------------------------------*/
/* Call ETH_StructInit if you don't like to configure all ETH_InitStructure parameter */
ETH_StructInit(Ð_InitStructure);
/* Fill ETH_InitStructure parametrs */
/*------------------------ MAC -----------------------------------*/
ETH_InitStructure.ETH_AutoNegotiation = ETH_AutoNegotiation_Enable ;
ETH_InitStructure.ETH_LoopbackMode = ETH_LoopbackMode_Disable;
ETH_InitStructure.ETH_RetryTransmission = ETH_RetryTransmission_Disable;
ETH_InitStructure.ETH_AutomaticPadCRCStrip = ETH_AutomaticPadCRCStrip_Disable;
ETH_InitStructure.ETH_ReceiveAll = ETH_ReceiveAll_Disable;
ETH_InitStructure.ETH_BroadcastFramesReception = ETH_BroadcastFramesReception_Enable;
ETH_InitStructure.ETH_PromiscuousMode = ETH_PromiscuousMode_Disable;
ETH_InitStructure.ETH_MulticastFramesFilter = ETH_MulticastFramesFilter_Perfect;
ETH_InitStructure.ETH_UnicastFramesFilter = ETH_UnicastFramesFilter_Perfect;
#ifdef CHECKSUM_BY_HARDWARE
ETH_InitStructure.ETH_ChecksumOffload = ETH_ChecksumOffload_Enable;
#endif
/*------------------------ DMA -----------------------------------*/
/* When we use the Checksum offload feature, we need to enable the Store and Forward mode:
the store and forward guarantee that a whole frame is stored in the FIFO, so the MAC can insert/verify the checksum,
if the checksum is OK the DMA can handle the frame otherwise the frame is dropped */
ETH_InitStructure.ETH_DropTCPIPChecksumErrorFrame = ETH_DropTCPIPChecksumErrorFrame_Enable;
ETH_InitStructure.ETH_ReceiveStoreForward = ETH_ReceiveStoreForward_Enable;
ETH_InitStructure.ETH_TransmitStoreForward = ETH_TransmitStoreForward_Enable;
ETH_InitStructure.ETH_ForwardErrorFrames = ETH_ForwardErrorFrames_Disable;
ETH_InitStructure.ETH_ForwardUndersizedGoodFrames = ETH_ForwardUndersizedGoodFrames_Disable;
ETH_InitStructure.ETH_SecondFrameOperate = ETH_SecondFrameOperate_Enable;
ETH_InitStructure.ETH_AddressAlignedBeats = ETH_AddressAlignedBeats_Enable;
ETH_InitStructure.ETH_FixedBurst = ETH_FixedBurst_Enable;
ETH_InitStructure.ETH_RxDMABurstLength = ETH_RxDMABurstLength_32Beat;
ETH_InitStructure.ETH_TxDMABurstLength = ETH_TxDMABurstLength_32Beat;
ETH_InitStructure.ETH_DMAArbitration = ETH_DMAArbitration_RoundRobin_RxTx_2_1;
/* Configure Ethernet */
ETH_Init(Ð_InitStructure, PHY_ADDRESS);
/* Enable the Ethernet Rx Interrupt */
ETH_DMAITConfig(ETH_DMA_IT_NIS | ETH_DMA_IT_R, ENABLE);
}
void BSP_Init (void)
{
//gpc 2-2-2011 BSP_IntInit();
RCC_DeInit();
RCC_HSEConfig(RCC_HSE_ON); /* HSE = 25MHz ext. crystal. */
RCC_WaitForHSEStartUp();
RCC_PREDIV2Config(RCC_PREDIV2_Div5); /* Fprediv2 = HSE / 5 = 5MHz. */
RCC_PLL2Config(RCC_PLL2Mul_8); /* PLL2 = Fprediv2 * 8 = 40MHz. */
RCC_PLL2Cmd(ENABLE);
RCC_PLL3Config(RCC_PLL3Mul_10); /* PLL3 = Fprediv2 * 10 = 50MHz. */
RCC_PLL3Cmd(ENABLE);
RCC_HCLKConfig(RCC_SYSCLK_Div1); /* HCLK = AHBCLK = PLL1 / AHBPRES(1) = 72MHz. */
RCC_PCLK2Config(RCC_HCLK_Div1); /* APB2CLK = AHBCLK / APB2DIV(1) = 72MHz. */
RCC_PCLK1Config(RCC_HCLK_Div2); /* APB1CLK = AHBCLK / APB1DIV(2) = 36MHz (max). */
RCC_ADCCLKConfig(RCC_PCLK2_Div6); /* ADCCLK = AHBCLK / APB2DIV / 6 = 12MHz. */
RCC_OTGFSCLKConfig(RCC_OTGFSCLKSource_PLL1VCO_Div3); /* OTGCLK = PLL1VCO / USBPRES(3) = 144MHz / 3 = 48MHz */
FLASH_SetLatency(FLASH_Latency_2); /* 2 Flash wait states when HCLK > 48MHz. */
FLASH_PrefetchBufferCmd(FLASH_PrefetchBuffer_Enable);
while (RCC_GetFlagStatus(RCC_FLAG_PLL2RDY) == RESET) { /* Wait for PLL2 to lock. */
;
}
while (RCC_GetFlagStatus(RCC_FLAG_PLL3RDY) == RESET) { /* Wait for PLL3 to lock. */
;
}
/* Fprediv1 = PLL2 / 5 = 8MHz. */
RCC_PREDIV1Config(RCC_PREDIV1_Source_PLL2, RCC_PREDIV1_Div5);
RCC_PLL1Config(RCC_PLL1Source_PREDIV1, RCC_PLL1Mul_9); /* PLL1 = Fprediv1 * 9 = 72Mhz. */
RCC_PLL1Cmd(ENABLE);
while (RCC_GetFlagStatus(RCC_FLAG_PLL1RDY) == RESET) { /* Wait for PLL1 to lock. */
;
}
RCC_SYSCLKConfig(RCC_SYSCLKSource_PLL1CLK); /* HCLK = SYSCLK = PLL1 = 72MHz. */
while (RCC_GetSYSCLKSource() != 0x08) {
;
}
BSP_CPU_ClkFreq_MHz = BSP_CPU_ClkFreq() / (CPU_INT32U)1000000;
BSP_CPU_ClkFreq_MHz = BSP_CPU_ClkFreq_MHz; /* Surpress compiler warning BSP_CPU_ClkFreq_MHz ... */
/* ... set and not used. */
BSP_LED_Init(); /* Initialize the I/Os for the LED controls. */
BSP_StatusInit(); /* Initialize the status input(s) */
#ifdef TRACE_EN /* See project / compiler preprocessor options. */
DBGMCU_CR |= DBGMCU_CR_TRACE_IOEN_MASK; /* Enable tracing (see Note #2). */
DBGMCU_CR &= ~DBGMCU_CR_TRACE_MODE_MASK; /* Clr trace mode sel bits. */
DBGMCU_CR |= DBGMCU_CR_TRACE_MODE_SYNC_04; /* Cfg trace mode to synch 4-bit. */
#endif
}
/**
* @brief Configures the DP83848V : Ethernet RMII Interface.
* @param None
* @retval None
*/
void ET_STM32_ETH_Configuration(void)
{
vu32 Value = 0;
GPIO_InitTypeDef GPIO_InitStructure;
ETH_InitTypeDef ETH_InitStructure;
/* Enable ETHERNET Clock */
RCC_AHBPeriphClockCmd(RCC_AHBPeriph_ETH_MAC |
RCC_AHBPeriph_ETH_MAC_Tx |
RCC_AHBPeriph_ETH_MAC_Rx, ENABLE);
// Start Initial GPIO For Interface DP83848V
// Initial ET-STM32F ARM KIT Ethernet Interface = RMII Mode
// PA1 <- ETH_RMII_REF_CLK(Default)
// PA2 -> ETH_RMII_MDIO(Default)
// PA8 -> MCO(Default)
// PB11 -> ETH_RMII_TXEN(Default)
// PB12 -> ETH_RMII_TXD0(Default)
// PB13 -> ETH_RMII_TXD1(Default)
// PC1 -> ETH_RMII_MDC(Default)
// PD8 <- ETH_RMII_RXDV(Remap)
// PD9 <- ETH_RMII_RXD0(Remap)
// PD10 <- ETH_RMII_RXD1(Remap)
// Configure PA2 as alternate function push-pull
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_2; //PA2 = ETH_RMII_MDIO
GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
GPIO_Init(GPIOA, &GPIO_InitStructure);
// Configure PC1 as alternate function push-pull
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_1; //PC1 = ETH_RMII_MDC
GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
GPIO_Init(GPIOC, &GPIO_InitStructure);
// Configure PB11, PB12 and PB13 as alternate function push-pull
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_11 | //PB11 = ETH_RMII_TXEN
GPIO_Pin_12 | //PB12 = ETH_RMII_TXD0
GPIO_Pin_13; //PB13 = ETH_RMII_TXD1
GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
GPIO_Init(GPIOB, &GPIO_InitStructure);
// Configure PA1 as input
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_1; //PA1 = ETH_RMII_REF_CLK
GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;
GPIO_Init(GPIOA, &GPIO_InitStructure);
// ETHERNET pins remapp in ET-STM32F ARM KIT board: RX_DV and RxD[1:0]
// PD8=CRS_DV(RMII Remap)
// PD9=RXD0(RMII Remap)
// PD10=RXD1(RMII Remap)
GPIO_PinRemapConfig(GPIO_Remap_ETH, ENABLE);
// Configure PD8, PD9, PD10 as input
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_8 | //PD8 = ETH_RMII_RX_DV
GPIO_Pin_9 | //PD9 = ETH_RMII_RXD0
GPIO_Pin_10; //PD10 = ETH_RMII_RXD1
GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;
GPIO_Init(GPIOD, &GPIO_InitStructure);
/* Start of Config MCO Clock = 50MHz on PA8 */
// Configure MCO (PA8) as alternate function push-pull
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_8; //PA8 = MCO
GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
GPIO_Init(GPIOA, &GPIO_InitStructure);
// set PLL3 clock output to 50MHz (25MHz / 5 * 10 = 50MHz)
RCC_PLL3Config(RCC_PLL3Mul_10);
// Enable PLL3
RCC_PLL3Cmd(ENABLE);
// Wait till PLL3 is ready
while (RCC_GetFlagStatus(RCC_FLAG_PLL3RDY) == RESET){}
// Get clock PLL3 clock on PA8 pin
RCC_MCOConfig(RCC_MCO_PLL3CLK);
/*End of Initial MCO Clock = 50MHz on PA8 */
//Initial Ethernet Interface = RMII Mode
GPIO_ETH_MediaInterfaceConfig(GPIO_ETH_MediaInterface_RMII);
/* Reset ETHERNET on AHB Bus */
ETH_DeInit();
/* Software reset */
ETH_SoftwareReset();
/* Wait for software reset */
while(ETH_GetSoftwareResetStatus()==SET);
/* ETHERNET Configuration ------------------------------------------------------*/
/* Call ETH_StructInit if you don't like to configure all ETH_InitStructure parameter */
ETH_StructInit(Ð_InitStructure);
/* Fill ETH_InitStructure parametrs */
/*------------------------ MAC -----------------------------------*/
ETH_InitStructure.ETH_AutoNegotiation = ETH_AutoNegotiation_Enable ;
//ETH_InitStructure.ETH_Speed = ETH_Speed_100M; //Test 100 MHz
ETH_InitStructure.ETH_LoopbackMode = ETH_LoopbackMode_Disable;
//ETH_InitStructure.ETH_Mode = ETH_Mode_FullDuplex; //Test
ETH_InitStructure.ETH_RetryTransmission = ETH_RetryTransmission_Disable;
ETH_InitStructure.ETH_AutomaticPadCRCStrip = ETH_AutomaticPadCRCStrip_Disable;
ETH_InitStructure.ETH_ReceiveAll = ETH_ReceiveAll_Enable;
ETH_InitStructure.ETH_BroadcastFramesReception = ETH_BroadcastFramesReception_Disable;
ETH_InitStructure.ETH_PromiscuousMode = ETH_PromiscuousMode_Disable;
ETH_InitStructure.ETH_MulticastFramesFilter = ETH_MulticastFramesFilter_Perfect;
ETH_InitStructure.ETH_UnicastFramesFilter = ETH_UnicastFramesFilter_Perfect;
/* Configure ETHERNET */
Value = ETH_Init(Ð_InitStructure, PHY_ADDRESS);
}
/*******************************************************************************
* Function Name : Set_System
* Description : Configures Main system clocks & power
* Input : None.
* Return : None.
*******************************************************************************/
void Set_System(void)
{
/* SYSCLK, HCLK, PCLK2 and PCLK1 configuration -----------------------------*/
/* RCC system reset(for debug purpose) */
RCC_DeInit();
/* Enable HSE */
RCC_HSEConfig(RCC_HSE_ON);
/* Wait till HSE is ready */
HSEStartUpStatus = RCC_WaitForHSEStartUp();
if (HSEStartUpStatus == SUCCESS)
{
/* Enable Prefetch Buffer */
FLASH_PrefetchBufferCmd(FLASH_PrefetchBuffer_Enable);
/* Flash 2 wait state */
FLASH_SetLatency(FLASH_Latency_2);
/* HCLK = SYSCLK */
RCC_HCLKConfig(RCC_SYSCLK_Div1);
/* PCLK2 = HCLK */
RCC_PCLK2Config(RCC_HCLK_Div1);
/* PCLK1 = HCLK/2 */
RCC_PCLK1Config(RCC_HCLK_Div2);
#ifdef STM32F10X_CL
/* Configure PLLs *********************************************************/
#ifdef EXTERNAL_CRYSTAL_25MHz
/* PLL2 configuration: PLL2CLK = (HSE / 9) * 13 = 36.111 MHz */
RCC_PREDIV2Config(RCC_PREDIV2_Div9);
RCC_PLL2Config(RCC_PLL2Mul_13);
/* Enable PLL2 */
RCC_PLL2Cmd(ENABLE);
/* Wait till PLL2 is ready */
while (RCC_GetFlagStatus(RCC_FLAG_PLL2RDY) == RESET)
{}
/* PPL3 configuration: PLL3CLK = (HSE / 9) * 14 = PLL3_VCO = 77.777 MHz */
RCC_PLL3Config(RCC_PLL3Mul_14);
/* Enable PLL3 */
RCC_PLL3Cmd(ENABLE);
/* Wait till PLL3 is ready */
while (RCC_GetFlagStatus(RCC_FLAG_PLL3RDY) == RESET)
{}
/* PLL configuration: PLLCLK = (PLL2 / 4) * 8 = 72.222 MHz */
RCC_PREDIV1Config(RCC_PREDIV1_Source_PLL2, RCC_PREDIV1_Div4);
RCC_PLLConfig(RCC_PLLSource_PREDIV1, RCC_PLLMul_8);
#elif defined (EXTERNAL_CRYSTAL_14_7456MHz)
/* PLL2 configuration: PLL2CLK = (HSE / 4) * 13 = 47.932 MHz */
RCC_PREDIV2Config(RCC_PREDIV2_Div4);
RCC_PLL2Config(RCC_PLL2Mul_13);
/* Enable PLL2 */
RCC_PLL2Cmd(ENABLE);
/* Wait till PLL2 is ready */
while (RCC_GetFlagStatus(RCC_FLAG_PLL2RDY) == RESET)
{}
/* PPL3 configuration: PLL3CLK = (HSE / 4) * 20 = PLL3_VCO = 147.456 MHz */
RCC_PLL3Config(RCC_PLL3Mul_20);
/* Enable PLL3 */
RCC_PLL3Cmd(ENABLE);
/* Wait till PLL3 is ready */
while (RCC_GetFlagStatus(RCC_FLAG_PLL3RDY) == RESET)
{}
/* PPL1 configuration: PLL1CLK = (PLL2 / 4) * 6 = 71.8848 MHz */
RCC_PREDIV1Config(RCC_PREDIV1_Source_PLL2, RCC_PREDIV1_Div4);
RCC_PLLConfig(RCC_PLLSource_PREDIV1, RCC_PLLMul_6);
#endif /* EXTERNAL_CRYSTAL_25MHz */
/* Configure I2S clock source: PLL3 VCO clock */
RCC_I2S2CLKConfig(RCC_I2S2CLKSource_PLL3_VCO);
#else
/* PLLCLK = 8MHz * 9 = 72 MHz */
RCC_PLLConfig(RCC_PLLSource_HSE_Div1, RCC_PLLMul_9);
#endif /* STM32F10X_CL */
/* Enable PLL */
RCC_PLLCmd(ENABLE);
/* Wait till PLL is ready */
while (RCC_GetFlagStatus(RCC_FLAG_PLLRDY) == RESET)
{
}
/* Select PLL as system clock source */
RCC_SYSCLKConfig(RCC_SYSCLKSource_PLLCLK);
/* Wait till PLL is used as system clock source */
while(RCC_GetSYSCLKSource() != 0x08)
{
}
}
else
{ /* If HSE fails to start-up, the application will have wrong clock configuration.
User can add here some code to deal with this error */
/* Go to infinite loop */
while (1)
{
}
}
}
void stm32f107EthInitGpio(NetInterface *interface)
{
GPIO_InitTypeDef GPIO_InitStructure;
//STM3210C-EVAL evaluation board?
#if defined(USE_STM3210C_EVAL)
//Enable AFIO clock
RCC_APB2PeriphClockCmd(RCC_APB2Periph_AFIO, ENABLE);
//Enable GPIO clocks
RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOA | RCC_APB2Periph_GPIOB |
RCC_APB2Periph_GPIOC | RCC_APB2Periph_GPIOD, ENABLE);
//Configure MCO (PA8) as an output
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_8;
GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
GPIO_Init(GPIOA, &GPIO_InitStructure);
//Configure MCO pin to output the HSE clock (25MHz)
RCC_MCOConfig(RCC_MCO_HSE);
//Select MII interface mode
GPIO_ETH_MediaInterfaceConfig(GPIO_ETH_MediaInterface_MII);
//Configure MII_MDIO (PA2)
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_2;
GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
GPIO_Init(GPIOA, &GPIO_InitStructure);
//Configure MII_PPS_OUT (PB5), ETH_MII_TXD3 (PB8), MII_TX_EN (PB11),
//MII_TXD0 (PB12) and MII_TXD1 (PB13)
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_5 | GPIO_Pin_8 | GPIO_Pin_11 | GPIO_Pin_12 | GPIO_Pin_13;
GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
GPIO_Init(GPIOB, &GPIO_InitStructure);
//Configure MII_MDC (PC1) and MII_TXD2 (PC2)
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_1 | GPIO_Pin_2;
GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
GPIO_Init(GPIOC, &GPIO_InitStructure);
//Configure ETH_MII_CRS (PA0), ETH_MII_RX_CLK (PA1) and ETH_MII_COL (PA3)
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_1 | GPIO_Pin_3;
GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;
GPIO_Init(GPIOA, &GPIO_InitStructure);
//Configure ETH_MII_RX_ER (PB10)
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_10;
GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;
GPIO_Init(GPIOB, &GPIO_InitStructure);
//Configure ETH_MII_TX_CLK (PC3)
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_3;
GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;
GPIO_Init(GPIOC, &GPIO_InitStructure);
//Configure ETH_MII_RX_DV (PD8), ETH_MII_RXD0 (PD9), ETH_MII_RXD1 (PD10),
//ETH_MII_RXD2 (PD11) and ETH_MII_RXD3 (PD12)
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_8 | GPIO_Pin_9 | GPIO_Pin_10 | GPIO_Pin_11 | GPIO_Pin_12;
GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;
GPIO_Init(GPIOD, &GPIO_InitStructure);
//Remap Ethernet pins
GPIO_PinRemapConfig(GPIO_Remap_ETH, ENABLE);
//STM32-P107 evaluation board?
#elif defined(USE_STM32_P107)
//Enable AFIO clock
RCC_APB2PeriphClockCmd(RCC_APB2Periph_AFIO, ENABLE);
//Enable GPIO clocks
RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOA |
RCC_APB2Periph_GPIOB | RCC_APB2Periph_GPIOC, ENABLE);
//Configure MCO (PA8) as an output
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_8;
GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
GPIO_Init(GPIOA, &GPIO_InitStructure);
//Configure PLL3 to output a 50MHz clock
RCC_PLL3Config(RCC_PLL3Mul_10);
//Enable PLL3
RCC_PLL3Cmd(ENABLE);
//Wait for the PLL3 to lock
while(RCC_GetFlagStatus(RCC_FLAG_PLL3RDY) == RESET);
//Configure MCO pin to output the PLL3 clock
RCC_MCOConfig(RCC_MCO_PLL3CLK);
//Select RMII interface mode
GPIO_ETH_MediaInterfaceConfig(GPIO_ETH_MediaInterface_RMII);
//Configure ETH_MDIO (PA2)
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_2;
GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
GPIO_Init(GPIOA, &GPIO_InitStructure);
//Configure ETH_RMII_TX_EN (PB11), ETH_RMII_TXD0 (PB12) and ETH_RMII_TXD1 (PB13)
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_11 | GPIO_Pin_12 | GPIO_Pin_13;
GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
GPIO_Init(GPIOB, &GPIO_InitStructure);
//Configure ETH_MDC (PC1)
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_1;
GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
GPIO_Init(GPIOC, &GPIO_InitStructure);
//Configure ETH_RMII_REF_CLK (PA1) and ETH_RMII_CRS_DV (PA7)
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_1 | GPIO_Pin_7;
GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;
GPIO_Init(GPIOA, &GPIO_InitStructure);
//Configure ETH_RMII_RXD0 (PC4) and ETH_RMII_RXD1 (PC5)
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_4 | GPIO_Pin_5;
GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;
GPIO_Init(GPIOC, &GPIO_InitStructure);
//Do not remap Ethernet pins
GPIO_PinRemapConfig(GPIO_Remap_ETH, DISABLE);
#endif
}
