uint32_t ass_multiply(char** line)
{
if(strcmp(line[0], "mul") == 0)
{
return 0xE0000090 | (REG_D(regToInt(line[1]))
| REG_M(regToInt(line[2])) | REG_S(regToInt(line[3])));
}
return 0xE0200090 | (REG_D(regToInt(line[1])) | REG_M(regToInt(line[2]))
| REG_S(regToInt(line[3])) | REG_N(regToInt(line[4])));
}
uint32_t multiply_instr(char** line)
{
uint32_t instr;
if(strcmp(line[0], "mul") == 0)
{
instr = 0xE0000090;
instr |= (REG_D(regToInt(line[1])) | REG_M(regToInt(line[2])) | REG_S(regToInt(line[3])));
}
else
{
instr = 0xE0200090;
instr |= (REG_D(regToInt(line[1])) | REG_M(regToInt(line[2]))
| REG_S(regToInt(line[3])) | REG_N(regToInt(line[4])));
}
return instr;
}
static void WRITE_EA_32(m68000_base_device *m68k, int ea, UINT32 data)
{
int mode = (ea >> 3) & 0x7;
int reg = (ea & 0x7);
switch (mode)
{
case 0: // Dn
{
REG_D(m68k)[reg] = data;
break;
}
case 1: // An
{
REG_A(m68k)[reg] = data;
break;
}
case 2: // (An)
{
UINT32 ea = REG_A(m68k)[reg];
m68ki_write_32(m68k, ea, data);
break;
}
case 3: // (An)+
{
UINT32 ea = EA_AY_PI_32(m68k);
m68ki_write_32(m68k, ea, data);
break;
}
case 4: // -(An)
{
UINT32 ea = EA_AY_PD_32(m68k);
m68ki_write_32(m68k, ea, data);
break;
}
case 5: // (d16, An)
{
UINT32 ea = EA_AY_DI_32(m68k);
m68ki_write_32(m68k, ea, data);
break;
}
case 6: // (An) + (Xn) + d8
{
UINT32 ea = EA_AY_IX_32(m68k);
m68ki_write_32(m68k, ea, data);
break;
}
case 7:
{
switch (reg)
{
case 1: // (xxx).L
{
UINT32 d1 = OPER_I_16(m68k);
UINT32 d2 = OPER_I_16(m68k);
UINT32 ea = (d1 << 16) | d2;
m68ki_write_32(m68k, ea, data);
break;
}
case 2: // (d16, PC)
{
UINT32 ea = EA_PCDI_32(m68k);
m68ki_write_32(m68k, ea, data);
break;
}
default: fatalerror("M68kFPU: WRITE_EA_32: unhandled mode %d, reg %d at %08X\n", mode, reg, REG_PC(m68k));
}
break;
}
default: fatalerror("M68kFPU: WRITE_EA_32: unhandled mode %d, reg %d, data %08X at %08X\n", mode, reg, data, REG_PC(m68k));
}
}
static UINT32 READ_EA_32(m68000_base_device *m68k, int ea)
{
int mode = (ea >> 3) & 0x7;
int reg = (ea & 0x7);
switch (mode)
{
case 0: // Dn
{
return REG_D(m68k)[reg];
}
case 2: // (An)
{
UINT32 ea = REG_A(m68k)[reg];
return m68ki_read_32(m68k, ea);
}
case 3: // (An)+
{
UINT32 ea = EA_AY_PI_32(m68k);
return m68ki_read_32(m68k, ea);
}
case 4: // -(An)
{
UINT32 ea = EA_AY_PD_32(m68k);
return m68ki_read_32(m68k, ea);
}
case 5: // (d16, An)
{
UINT32 ea = EA_AY_DI_32(m68k);
return m68ki_read_32(m68k, ea);
}
case 6: // (An) + (Xn) + d8
{
UINT32 ea = EA_AY_IX_32(m68k);
return m68ki_read_32(m68k, ea);
}
case 7:
{
switch (reg)
{
case 0: // (xxx).W
{
UINT32 ea = (UINT32)OPER_I_16(m68k);
return m68ki_read_32(m68k, ea);
}
case 1: // (xxx).L
{
UINT32 d1 = OPER_I_16(m68k);
UINT32 d2 = OPER_I_16(m68k);
UINT32 ea = (d1 << 16) | d2;
return m68ki_read_32(m68k, ea);
}
case 2: // (d16, PC)
{
UINT32 ea = EA_PCDI_32(m68k);
return m68ki_read_32(m68k, ea);
}
case 3: // (PC) + (Xn) + d8
{
UINT32 ea = EA_PCIX_32(m68k);
return m68ki_read_32(m68k, ea);
}
case 4: // #<data>
{
return OPER_I_32(m68k);
}
default: fatalerror("M68kFPU: READ_EA_32: unhandled mode %d, reg %d at %08X\n", mode, reg, REG_PC(m68k));
}
break;
}
default: fatalerror("M68kFPU: READ_EA_32: unhandled mode %d, reg %d at %08X\n", mode, reg, REG_PC(m68k));
}
return 0;
}
int apollo_debug_instruction_hook(m68000_base_device *device, offs_t curpc)
{
// trap data remembered for next rte
static struct {
UINT32 pc;
UINT32 sp;
UINT16 trap_no;
UINT16 trap_code;
} trap = { 0, 0, 0, 0 };
if (apollo_config( APOLLO_CONF_TRAP_TRACE | APOLLO_CONF_FPU_TRACE))
{
UINT32 ppc_save;
UINT16 ir;
m68000_base_device *m68k = device;
m68k->mmu_tmp_buserror_occurred = 0;
/* Read next instruction */
ir = (m68k->pref_addr == REG_PC(m68k)) ? m68k->pref_data : m68k->readimm16(REG_PC(m68k));
// apollo_cpu_context expects the PC of current opcode in REG_PPC (not the previous PC)
ppc_save = REG_PPC(m68k);
REG_PPC(m68k) = REG_PC(m68k);
if (m68k->mmu_tmp_buserror_occurred)
{
m68k->mmu_tmp_buserror_occurred = 0;
// give up
}
else if ((ir & 0xff00) == 0xf200 && (apollo_config( APOLLO_CONF_FPU_TRACE)))
{
char sb[256];
LOG(("%s sp=%08x FPU: %x %s", apollo_cpu_context(device->machine().firstcpu),
REG_A(m68k)[7], ir, disassemble(m68k, REG_PC(m68k), sb)));
}
else if (!m68k->pmmu_enabled)
{
// skip
}
else if (ir == 0x4e73) // RTE
{
const UINT16 *data = get_data(m68k, REG_A(m68k)[7]);
if ( REG_USP(m68k) == 0 && (data[0] & 0x2000) == 0) {
LOG(("%s sp=%08x RTE: sr=%04x pc=%04x%04x v=%04x usp=%08x",
apollo_cpu_context(device->machine().firstcpu),
REG_A(m68k)[7], data[0], data[1], data[2], data[3], REG_USP(m68k)));
}
}
else if ((ir & 0xfff0) == 0x4e40 && (ir & 0x0f) <= 8 && apollo_config(APOLLO_CONF_TRAP_TRACE))
{
// trap n
trap.pc = REG_PC(m68k);
trap.sp = REG_A(m68k)[7];
trap.trap_no = ir & 0x0f;
trap.trap_code = REG_D(m68k)[0] & 0xffff;
char sb[1000];
LOG(("%s sp=%08x Domain/OS SVC: trap %x 0x%02x: %s",
apollo_cpu_context(device->machine().firstcpu), trap.sp,
trap.trap_no, trap.trap_code,
get_svc_call(m68k, trap.trap_no, trap.trap_code, sb)));
}
else if (trap.pc == REG_PC(m68k) - 2 && trap.sp == REG_A(m68k)[7])
{
// rte
char sb[1000];
LOG(("%s sp=%08x Domain/OS SVC: %s D0=0x%x",
apollo_cpu_context(device->machine().firstcpu), trap.sp,
get_svc_call(m68k, trap.trap_no, trap.trap_code, sb), REG_D(m68k)[0]));
trap.pc = 0;
trap.sp = 0;
trap.trap_no = 0;
trap.trap_code = 0;
}
// restore previous PC
REG_PPC(m68k) = ppc_save;
}
return 0;
}
