int dmic_handler(int pre_ints)
{
volatile int ret;
REG_DMIC_ICR |= 0x3f;
REG_DMIC_IMR |= 1<<0 | 1<<4;
last_dma_count = REG_DMADTC(_dma_channel);
if(dmic_current_state == WAITING_TRIGGER) {
if(is_int_rtc(pre_ints)) {
// TCSM_PCHAR('F');
REG_DMIC_ICR |= 0x3f;
REG_DMIC_IMR &= ~(1<<0 | 1<<4);
return SYS_WAKEUP_FAILED;
}
dmic_current_state = WAITING_DATA;
/*change trigger value to 0, make dmic wakeup cpu all the time*/
#ifdef CONFIG_CPU_IDLE_SLEEP
tcu_timer_mod(ms_to_count(TCU_TIMER_MS)); /* start a timer */
#else
REG_DMIC_THRL = 0;
#endif
} else if (dmic_current_state == WAITING_DATA){
}
#ifdef CONFIG_CPU_SWITCH_FREQUENCY
ret = process_dma_data_3();
#else
ret = process_dma_data_2();
#endif
if(ret == SYS_WAKEUP_OK) {
return SYS_WAKEUP_OK;
} else if(ret == SYS_NEED_DATA) {
#ifdef CONFIG_CPU_IDLE_SLEEP
/* do nothing */
#else
REG_DMIC_TRINMAX = 5;
REG_DMIC_CR0 |= 1 << 6;
REG_DMIC_IMR &= ~( 1<<4 | 1<<0);
#endif
last_dma_count = REG_DMADTC(_dma_channel);
return SYS_NEED_DATA;
} else if(ret == SYS_WAKEUP_FAILED) {
/*
* if current wakeup operation failed. we need reconfig dmic
* to work at appropriate mode.
* */
dmic_current_state = WAITING_TRIGGER;
wakeup_failed_times++;
TCSM_PCHAR('F');
TCSM_PCHAR('A');
TCSM_PCHAR('I');
TCSM_PCHAR('L');
TCSM_PCHAR('E');
TCSM_PCHAR('D');
reconfig_thr_value();
#ifdef CONFIG_CPU_IDLE_SLEEP
/* del a timer, when dmic trigger. it will re start a timer */
tcu_timer_del();
#endif
/* change trigger mode to > N times*/
//REG_DMIC_TRICR |= 2 << 16;
REG_DMIC_TRINMAX = 5;
REG_DMIC_TRICR |= 1<<0; /*clear trigger*/
REG_DMIC_CR0 |= 3<<6; /* disable data path*/
REG_DMIC_ICR |= 0x3f;
REG_DMIC_IMR &= ~(1<<0 | 1<<4);
return SYS_WAKEUP_FAILED;
}
return SYS_WAKEUP_FAILED;
}
void dump_dma_register(int chn)
{
printk("=============== dma dump register ===============\n");
printk("DMAC : 0x%08X\n", REG_DMADMAC);
printk("DIRQP : 0x%08X\n", REG_DMADIRQP);
printk("DDB : 0x%08X\n", REG_DMADDB);
printk("DDS : 0x%08X\n", REG_DMADDS);
printk("DMACP : 0x%08X\n", REG_DMADMACP);
printk("DSIRQP : 0x%08X\n", REG_DMADSIRQP);
printk("DSIRQM : 0x%08X\n", REG_DMADSIRQM);
printk("DCIRQP : 0x%08X\n", REG_DMADCIRQP);
printk("DCIRQM : 0x%08X\n", REG_DMADCIRQM);
printk("DMCS : 0x%08X\n", REG_DMADMCS);
printk("DMNMB : 0x%08X\n", REG_DMADMNMB);
printk("DMSMB : 0x%08X\n", REG_DMADMSMB);
printk("DMINT : 0x%08X\n", REG_DMADMINT);
printk("* DMAC.FMSC = 0x%d\n", DMA_READBIT(REG_DMADMAC, 31, 1));
printk("* DMAC.FSSI = 0x%d\n", DMA_READBIT(REG_DMADMAC, 30, 1));
printk("* DMAC.FTSSI= 0x%d\n", DMA_READBIT(REG_DMADMAC, 29, 1));
printk("* DMAC.FUART= 0x%d\n", DMA_READBIT(REG_DMADMAC, 28, 1));
printk("* DMAC.FAIC = 0x%d\n", DMA_READBIT(REG_DMADMAC, 27, 1));
printk("* DMAC.INTCC= 0x%d\n", DMA_READBIT(REG_DMADMAC, 17, 5));
printk("* DMAC.INTCE= 0x%d\n", DMA_READBIT(REG_DMADMAC, 16, 1));
printk("* DMAC.HLT = 0x%d\n", DMA_READBIT(REG_DMADMAC, 3, 1));
printk("* DMAC.AR = 0x%d\n", DMA_READBIT(REG_DMADMAC, 2, 1));
printk("* DMAC.CH01 = 0x%d\n", DMA_READBIT(REG_DMADMAC, 1, 1));
printk("* DMAC.DMAE = 0x%d\n", DMA_READBIT(REG_DMADMAC, 0, 1));
if(chn>=0 && chn<=31){
printk("");
printk("DSA(%02d) : 0x%08X\n", chn, REG_DMADSA(chn));
printk("DTA(%02d) : 0x%08X\n", chn, REG_DMADTA(chn));
printk("DTC(%02d) : 0x%08X\n", chn, REG_DMADTC(chn));
printk("DRT(%02d) : 0x%08X\n", chn, REG_DMADRT(chn));
printk("DCS(%02d) : 0x%08X\n", chn, REG_DMADCS(chn));
printk("DCM(%02d) : 0x%08X\n", chn, REG_DMADCM(chn));
printk("DDA(%02d) : 0x%08X\n", chn, REG_DMADDA(chn));
printk("DSD(%02d) : 0x%08X\n", chn, REG_DMADSD(chn));
printk("* DCS(%02d).NDES = 0x%d\n", chn, DMA_READBIT(REG_DMADCS(chn), 31, 1));
printk("* DCS(%02d).DES8 = 0x%d\n", chn, DMA_READBIT(REG_DMADCS(chn), 30, 1));
printk("* DCS(%02d).CDOA = 0x%d\n", chn, DMA_READBIT(REG_DMADCS(chn), 8, 8));
printk("* DCS(%02d).AR = 0x%d\n", chn, DMA_READBIT(REG_DMADCS(chn), 4, 1));
printk("* DCS(%02d).TT = 0x%d\n", chn, DMA_READBIT(REG_DMADCS(chn), 3, 1));
printk("* DCS(%02d).HLT = 0x%d\n", chn, DMA_READBIT(REG_DMADCS(chn), 2, 1));
printk("* DCS(%02d).CTE = 0x%d\n", chn, DMA_READBIT(REG_DMADCS(chn), 0, 1));
printk("* DCM(%02d).SDI = 0x%d\n", chn, DMA_READBIT(REG_DMADCM(chn), 26, 2));
printk("* DCM(%02d).DID = 0x%d\n", chn, DMA_READBIT(REG_DMADCM(chn), 24, 2));
printk("* DCM(%02d).SAI = 0x%d\n", chn, DMA_READBIT(REG_DMADCM(chn), 23, 1));
printk("* DCM(%02d).DAI = 0x%d\n", chn, DMA_READBIT(REG_DMADCM(chn), 22, 1));
printk("* DCM(%02d).RDIL = 0x%d\n", chn, DMA_READBIT(REG_DMADCM(chn), 16, 4));
printk("* DCM(%02d).SP = 0x%d\n", chn, DMA_READBIT(REG_DMADCM(chn), 14, 2));
printk("* DCM(%02d).DP = 0x%d\n", chn, DMA_READBIT(REG_DMADCM(chn), 12, 2));
printk("* DCM(%02d).TSZ = 0x%d\n", chn, DMA_READBIT(REG_DMADCM(chn), 8, 3));
printk("* DCM(%02d).STDE = 0x%d\n", chn, DMA_READBIT(REG_DMADCM(chn), 2, 1));
printk("* DCM(%02d).TIE = 0x%d\n", chn, DMA_READBIT(REG_DMADCM(chn), 1, 1));
printk("* DCM(%02d).LINK = 0x%d\n", chn, DMA_READBIT(REG_DMADCM(chn), 0, 1));
printk("* DDA(%02d).DBA = 0x%08X\n", chn, DMA_READBIT(REG_DMADDA(chn), 12, 20));
printk("* DDA(%02d).DOA = 0x%08X\n", chn, DMA_READBIT(REG_DMADDA(chn), 4, 8));
printk("* DSD(%02d).TSD = 0x%08X\n", chn, DMA_READBIT(REG_DMADSD(chn), 16, 16));
printk("* DSD(%02d).SSD = 0x%08X\n", chn, DMA_READBIT(REG_DMADSD(chn), 0, 16));
}
printk("INT_ICSR0:0x%08X\n",*(int volatile*)0xB0001000);
printk("\n");
}
int cpu_should_sleep(void)
{
return ((REG_DMIC_FSR & 0x7f) < (DMIC_FIFO_THR - 10)) &&(last_dma_count != REG_DMADTC(_dma_channel)) ? 1 : 0;
}
