void hw_aes_hash_cfg_dma(const uint8 *src, uint8 *dst, unsigned int len)
{
/* Source address setting */
AES_HASH->CRYPTO_FETCH_ADDR_REG = DA15000_phy_addr((uint32)src);
/* Destination address setting */
if (dst) {
unsigned int remap_type = REG_GETF(CRG_TOP, SYS_CTRL_REG, REMAP_ADR0);
if (IS_SYSRAM_ADDRESS(dst) ||
(IS_REMAPPED_ADDRESS(dst) && (remap_type == 0x3))) {
AES_HASH->CRYPTO_DEST_ADDR_REG = DA15000_phy_addr((uint32)dst);
#if dg_configEXEC_MODE != MODE_IS_CACHED
} else if (IS_CACHERAM_ADDRESS(dst)) {
AES_HASH->CRYPTO_DEST_ADDR_REG = DA15000_phy_addr((uint32)dst);
#endif
} else {
/*
* Destination address can only reside in RAM or Cache RAM, but in case of remapped
* address, REMAP_ADR0 cannot be 0x6 (Cache Data RAM)
*/
ASSERT_ERROR(0);
}
}
/* Data length setting */
AES_HASH->CRYPTO_LEN_REG = (uint32)len;
}
HW_WDG_RESET hw_watchdog_is_irq_or_rst_gen(void)
{
if (REG_GETF(WDOG, WATCHDOG_CTRL_REG, NMI_RST))
{
return HW_WDG_RESET_RST;
}
return HW_WDG_RESET_NMI;
}
uint32_t DA15000_phy_addr(uint32_t addr)
{
static const uint32_t remap[] =
{
MEMORY_ROM_BASE,
MEMORY_OTP_BASE,
MEMORY_QSPIF_BASE,
MEMORY_SYSRAM_BASE,
MEMORY_QSPIF_BASE,
MEMORY_OTP_BASE,
MEMORY_CACHERAM_BASE,
0
};
if (addr >= MEMORY_REMAPPED_END)
{
return addr;
}
return addr + remap[REG_GETF(CRG_TOP, SYS_CTRL_REG, REMAP_ADR0)];
}
void hw_aes_hash_cfg_dma(const uint8 *src, uint8 *dst, unsigned int len)
{
/* Source address setting */
AES_HASH->CRYPTO_FETCH_ADDR_REG = black_orca_phy_addr((uint32)src);
/* Destination address setting */
if (dst) {
unsigned int remap_type = REG_GETF(CRG_TOP, SYS_CTRL_REG, REMAP_ADR0);
if (IS_SYSRAM_ADDRESS(dst) ||
(IS_REMAPPED_ADDRESS(dst) && (remap_type == 0x3))) {
AES_HASH->CRYPTO_DEST_ADDR_REG = black_orca_phy_addr((uint32)dst);
}
else {
/* Destination address can only reside in RAM */
ASSERT_ERROR(0);
}
}
/* Data length setting */
AES_HASH->CRYPTO_LEN_REG = (uint32)len;
}
__RETAINED_CODE void hw_watchdog_handle_int(unsigned long *exception_args)
{
// Reached this point due to a WDOG timeout
uint16_t pmu_ctrl_reg = CRG_TOP->PMU_CTRL_REG;
pmu_ctrl_reg |= ((1 << CRG_TOP_PMU_CTRL_REG_BLE_SLEEP_Pos) | /* turn off BLE */
(1 << CRG_TOP_PMU_CTRL_REG_FTDF_SLEEP_Pos) | /* turn off FTDF */
(1 << CRG_TOP_PMU_CTRL_REG_RADIO_SLEEP_Pos) | /* turn off radio PD */
(1 << CRG_TOP_PMU_CTRL_REG_PERIPH_SLEEP_Pos)); /* turn off peripheral power domain */
CRG_TOP->PMU_CTRL_REG = pmu_ctrl_reg;
REG_SET_BIT(CRG_TOP, CLK_RADIO_REG, BLE_LP_RESET); /* reset the BLE LP timer */
#if (dg_configIMAGE_SETUP == DEVELOPMENT_MODE)
hw_watchdog_freeze(); // Stop WDOG
ENABLE_DEBUGGER;
if (exception_args != NULL)
{
*(volatile unsigned long *)(STATUS_BASE) = exception_args[0]; // R0
*(volatile unsigned long *)(STATUS_BASE + 0x04) = exception_args[1]; // R1
*(volatile unsigned long *)(STATUS_BASE + 0x08) = exception_args[2]; // R2
*(volatile unsigned long *)(STATUS_BASE + 0x0C) = exception_args[3]; // R3
*(volatile unsigned long *)(STATUS_BASE + 0x10) = exception_args[4]; // R12
*(volatile unsigned long *)(STATUS_BASE + 0x14) = exception_args[5]; // LR
*(volatile unsigned long *)(STATUS_BASE + 0x18) = exception_args[6]; // PC
*(volatile unsigned long *)(STATUS_BASE + 0x1C) = exception_args[7]; // PSR
*(volatile unsigned long *)(STATUS_BASE + 0x20) = (unsigned long)exception_args; // Stack Pointer
*(volatile unsigned long *)(STATUS_BASE + 0x24) = (*((volatile unsigned long *)(0xE000ED28))); // CFSR
*(volatile unsigned long *)(STATUS_BASE + 0x28) = (*((volatile unsigned long *)(0xE000ED2C))); // HFSR
*(volatile unsigned long *)(STATUS_BASE + 0x2C) = (*((volatile unsigned long *)(0xE000ED30))); // DFSR
*(volatile unsigned long *)(STATUS_BASE + 0x30) = (*((volatile unsigned long *)(0xE000ED3C))); // AFSR
*(volatile unsigned long *)(STATUS_BASE + 0x34) = (*((volatile unsigned long *)(0xE000ED34))); // MMAR
*(volatile unsigned long *)(STATUS_BASE + 0x38) = (*((volatile unsigned long *)(0xE000ED38))); // BFAR
}
hw_cpm_assert_trigger_gpio();
if (REG_GETF(CRG_TOP, SYS_STAT_REG, DBG_IS_ACTIVE))
{
__BKPT(0);
}
else
{
while (1);
}
#else // dg_configIMAGE_SETUP == DEVELOPMENT_MODE
if (exception_args != NULL)
{
nmi_event_data[0] = NMI_MAGIC_NUMBER;
nmi_event_data[1] = exception_args[0]; // R0
nmi_event_data[2] = exception_args[1]; // R1
nmi_event_data[3] = exception_args[2]; // R2
nmi_event_data[4] = exception_args[3]; // R3
nmi_event_data[5] = exception_args[4]; // R12
nmi_event_data[6] = exception_args[5]; // LR
nmi_event_data[7] = exception_args[6]; // PC
nmi_event_data[8] = exception_args[7]; // PSR
}
// Wait for the reset to occur
while (1);
#endif // dg_configIMAGE_SETUP == DEVELOPMENT_MODE
}
bool hw_watchdog_freeze(void)
{
GPREG->SET_FREEZE_REG = GPREG_SET_FREEZE_REG_FRZ_WDOG_Msk;
return !REG_GETF(WDOG, WATCHDOG_CTRL_REG, NMI_RST);
}
static void hw_aes_hash_wait_on_inactive(void)
{
while (!REG_GETF(AES_HASH, CRYPTO_STATUS_REG, CRYPTO_INACTIVE)) {
;
};
}
bool hw_aes_hash_wait_for_in()
{
return REG_GETF(AES_HASH, CRYPTO_STATUS_REG, CRYPTO_WAIT_FOR_IN) == 1;
}
bool hw_aes_hash_is_active()
{
return REG_GETF(AES_HASH, CRYPTO_STATUS_REG, CRYPTO_INACTIVE) == 0;
}
