int32_t scale_stop(void)
{
enum scale_drv_rtn rtn = SCALE_RTN_SUCCESS;
uint32_t flag;
spin_lock_irqsave(&scale_lock, flag);
if (atomic_read(&g_path->start_flag)) {
s_wait_flag = 1;
down_interruptible(&scale_done_sema);
}
spin_unlock_irqrestore(&scale_lock, flag);
REG_MWR(SCALE_CFG, 1, 0);
REG_MWR(SCALE_INT_MASK, SCALE_IRQ_BIT, 0 << 9);
REG_MWR(SCALE_INT_CLR, SCALE_IRQ_BIT, 0 << 9);
free_irq(SCALE_IRQ, &g_scale_irq);
_scale_free_tmp_buf();
SCALE_TRACE("SCALE DRV: stop is OK.\n");
return rtn;
}
static int32_t _scale_trim(void)
{
enum scale_drv_rtn rtn = SCALE_RTN_SUCCESS;
if (g_path->input_size.w != g_path->input_rect.w ||
g_path->input_size.h != g_path->input_rect.h) {
REG_OWR(SCALE_CFG, 1 << 1);
} else {
REG_MWR(SCALE_CFG, 1 << 1, 0 << 1);
}
return rtn;
}
static int32_t isp_k_fcs_block(struct isp_io_param *param)
{
int32_t ret = 0;
struct isp_dev_fcs_info fcs_info;
memset(&fcs_info, 0x00, sizeof(fcs_info));
ret = copy_from_user((void *)&fcs_info, param->property_param, sizeof(fcs_info));
if (0 != ret) {
printk("isp_k_fcs_bypass: copy error, ret=0x%x\n", (uint32_t)ret);
return -1;
}
REG_MWR(ISP_FCS_PARAM, BIT_16, (fcs_info.mode << 16));
if (fcs_info.bypass) {
REG_OWR(ISP_FCS_PARAM, BIT_0);
} else {
REG_MWR(ISP_FCS_PARAM, BIT_0, 0);
}
return ret;
}
static int32_t isp_k_brightness_block(struct isp_io_param *param)
{
int32_t ret = 0;
struct isp_dev_brightness_info brightness_info;
memset(&brightness_info, 0x00, sizeof(brightness_info));
ret = copy_from_user((void *)&brightness_info, param->property_param, sizeof(brightness_info));
if (0 != ret) {
printk("isp_k_brightness_block: copy error, ret=0x%x\n", (uint32_t)ret);
return -1;
}
REG_MWR(ISP_BRIGHT_PARAM, 0x1FE, ((brightness_info.factor & 0xFF) << 1));
if (brightness_info.bypass) {
REG_OWR(ISP_BRIGHT_PARAM, BIT_0);
} else {
REG_MWR(ISP_BRIGHT_PARAM, BIT_0, 0);
}
return ret;
}
int32_t dcam_module_init(enum dcam_cap_if_mode if_mode,
enum dcam_cap_sensor_mode sn_mode)
{
enum dcam_drv_rtn rtn = DCAM_RTN_SUCCESS;
struct dcam_cap_desc *cap_desc = &s_dcam_mod.dcam_cap;
int ret = 0;
if (if_mode >= DCAM_CAP_IF_MODE_MAX) {
rtn = -DCAM_RTN_CAP_IF_MODE_ERR;
} else {
if (sn_mode >= DCAM_CAP_MODE_MAX) {
rtn = -DCAM_RTN_CAP_SENSOR_MODE_ERR;
} else {
DCAM_CLEAR(&s_dcam_mod);
_dcam_link_frm(0); /* set default base frame index as 0 */
cap_desc->interface = if_mode;
cap_desc->input_format = sn_mode;
/*REG_OWR(DCAM_EB, BIT_13);//MM_EB*/
/*REG_OWR(DCAM_MATRIX_EB, BIT_10|BIT_5);*/
if (DCAM_CAP_IF_CSI2 == if_mode) {
/* REG_OWR(CSI2_DPHY_EB, MIPI_EB_BIT);*/
ret = _dcam_mipi_clk_en();
REG_OWR(DCAM_CFG, BIT_9);
REG_MWR(CAP_MIPI_CTRL, BIT_2 | BIT_1, sn_mode << 1);
} else {
/*REG_OWR(DCAM_EB, CCIR_IN_EB_BIT);
REG_OWR(DCAM_EB, CCIR_EB_BIT);*/
ret = _dcam_ccir_clk_en();
REG_MWR(DCAM_CFG, BIT_9, 0 << 9);
REG_MWR(CAP_CCIR_CTRL, BIT_2 | BIT_1, sn_mode << 1);
}
rtn = DCAM_RTN_SUCCESS;
}
}
return -rtn;
}
int32_t scale_module_dis(void)
{
int ret = 0;
REG_MWR(SCALE_BASE, 1 << 2, 0 << 2);
ret = dcam_module_dis();
if (ret) {
printk("scale_module_dis, failed to disable scale module %d \n", ret);
return ret;
}
ret = dcam_rel_resizer();
return ret;
}
static int32_t isp_k_yiq_ae_src_sel(struct isp_io_param *param)
{
int32_t ret = 0;
uint32_t src_sel = 0;
ret = copy_from_user((void *)&src_sel, param->property_param, sizeof(src_sel));
if (0 != ret) {
printk("isp_k_yiq_ae_src_sel: copy error, ret=0x%x\n", (uint32_t)ret);
return -1;
}
REG_MWR(ISP_YIQ_PARAM, (BIT_4 | BIT_3), (src_sel << 3));
return ret;
}
static int32_t isp_k_raw_sizer_bpc_shift_flactor(struct isp_io_param *param)
{
int32_t ret = 0;
uint32_t shift = 0;
ret = copy_from_user((void *)&shift, param->property_param, sizeof(shift));
if (0 != ret) {
printk("isp_k_raw_sizer_bpc_shift_flactor: copy_from_user error, ret = 0x%x\n", (uint32_t)ret);
return -1;
}
REG_MWR(ISP_RAW_SIZER_BPC, 0x7, shift);
return ret;
}
static int32_t isp_b4awb_switch_buf(struct isp_k_private *isp_private)
{
int32_t ret = 0;
int32_t i = 0;
/*first bypass b4awb*/
REG_MWR(ISP_BINNING_PARAM, BIT_0, 0x1);
/*switch buf*/
if (isp_private->b4awb_buf[0].buf_flag == 1) {
isp_private->b4awb_buf[1].buf_flag = 1;
REG_WR(ISP_BINNING_MEM_ADDR, isp_private->b4awb_buf[1].buf_phys_addr);
isp_private->b4awb_buf[0].buf_flag = 0;
} else if (isp_private->b4awb_buf[1].buf_flag == 1) {
isp_private->b4awb_buf[0].buf_flag = 1;
REG_WR(ISP_BINNING_MEM_ADDR, isp_private->b4awb_buf[0].buf_phys_addr);
isp_private->b4awb_buf[1].buf_flag = 0;
}
/*enable b4awb*/
REG_MWR(ISP_BINNING_PARAM, BIT_0, 0x0);
return ret;
}
static int32_t isp_k_prefilter_writeback(struct isp_io_param *param)
{
int32_t ret = 0;
uint32_t val = 0;
ret = copy_from_user((void *)&val, param->property_param, sizeof(val));
if (0 != ret) {
printk("isp_k_prefilter_writeback: copy error, ret=0x%x\n", (uint32_t)ret);
return -1;
}
REG_MWR(ISP_PREF_PARAM, (BIT_2 | BIT_1), ((val & 0x03) << 1));
return ret;
}
static int32_t isp_k_yiq_flicker_vheight(struct isp_io_param *param)
{
int32_t ret = 0;
uint32_t v_height = 0;
ret = copy_from_user((void *)&v_height, param->property_param, sizeof(v_height));
if (0 != ret) {
printk("isp_k_yiq_flicker_vheight: copy error, ret=0x%x\n", (uint32_t)ret);
return -1;
}
REG_MWR(ISP_AF_V_HEIGHT, 0xFFFF, v_height);
return ret;
}
static int32_t isp_k_yiq_flicker_line_conter(struct isp_io_param *param)
{
int32_t ret = 0;
uint32_t line_counter = 0;
ret = copy_from_user((void *)&line_counter, param->property_param, sizeof(line_counter));
if (0 != ret) {
printk("isp_k_yiq_flicker_line_conter: copy error, ret=0x%x\n", (uint32_t)ret);
return -1;
}
REG_MWR(ISP_AF_LINE_COUNTER, 0x1FF, line_counter);
return ret;
}
static int32_t isp_k_grgb_block(struct isp_io_param *param)
{
int32_t ret = 0;
uint32_t val = 0;
struct isp_dev_grgb_info_v1 grgb_info;
memset(&grgb_info, 0x00, sizeof(grgb_info));
ret = copy_from_user((void *)&grgb_info, param->property_param, sizeof(grgb_info));
if (0 != ret) {
printk("isp_k_grgb_block: copy error, ret=0x%x\n", (uint32_t)ret);
return -1;
}
REG_MWR(ISP_GRGB_PARAM, BIT_0, grgb_info.bypass);
val = ((grgb_info.diff & 0x3FF) << 7) | ((grgb_info.edge & 0x3F) << 1);
REG_MWR(ISP_GRGB_PARAM, 0x1FFFE, val);
val = grgb_info.grid & 0xFFF;
REG_MWR(ISP_GRGB_GRID, 0xFFF, val);
return ret;
}
static int32_t isp_k_raw_sizer_bpc_min_diff(struct isp_io_param *param)
{
int32_t ret = 0;
uint32_t min_diff = 0;
ret = copy_from_user((void *)&min_diff, param->property_param, sizeof(min_diff));
if (0 != ret) {
printk("isp_k_raw_sizer_bpc_multi_flactor: copy_from_user error, ret = 0x%x\n", (uint32_t)ret);
return -1;
}
REG_MWR(ISP_RAW_SIZER_BPC, (0xFF << 8), (min_diff << 8));
return ret;
}
static int32_t isp_k_yiq_ae_skip_num(struct isp_io_param *param)
{
int32_t ret = 0;
uint32_t skip_num = 0;
ret = copy_from_user((void *)&skip_num, param->property_param, sizeof(skip_num));
if (0 != ret) {
printk("isp_k_yiq_ae_skip_num: copy error, ret=0x%x\n", (uint32_t)ret);
return -1;
}
REG_MWR(ISP_YIQ_PARAM, (BIT_20 | BIT_19 | BIT_18 | BIT_17), (skip_num << 17));
return ret;
}
static int32_t isp_k_yiq_flicker_line_start(struct isp_io_param *param)
{
int32_t ret = 0;
uint32_t line_start = 0;
ret = copy_from_user((void *)&line_start, param->property_param, sizeof(line_start));
if (0 != ret) {
printk("isp_k_yiq_flicker_line_start: copy error, ret=0x%x\n", (uint32_t)ret);
return -1;
}
REG_MWR(ISP_AF_LINE_START, 0xFFF, line_start);
return ret;
}
static int32_t isp_k_yiq_flicker_mode(struct isp_io_param *param)
{
int32_t ret = 0;
uint32_t mode = 0;
ret = copy_from_user((void *)&mode, param->property_param, sizeof(mode));
if (0 != ret) {
printk("isp_k_yiq_flicker_mode: copy error, ret=0x%x\n", (uint32_t)ret);
return -1;
}
REG_MWR(ISP_YIQ_PARAM, BIT_21, (mode << 21));
return ret;
}
static int32_t isp_k_feeder_data_type(struct isp_io_param *param)
{
int32_t ret = 0;
uint32_t data_type = 0;
ret = copy_from_user((void *)&data_type, param->property_param, sizeof(data_type));
if (0 != ret) {
printk("isp_k_feeder_data_type: copy error, ret=0x%x\n", (uint32_t)ret);
return -1;
}
REG_MWR(ISP_FEEDER_PARAM, (BIT_3 | BIT_2 | BIT_1), (data_type << 1));
return ret;
}
static int32_t isp_k_feeder_block(struct isp_io_param *param)
{
int32_t ret = 0;
struct isp_dev_feeder_info feeder_info;
memset(&feeder_info, 0x00, sizeof(feeder_info));
ret = copy_from_user((void *)&feeder_info, param->property_param, sizeof(feeder_info));
if (0 != ret) {
printk("isp_k_feeder_block: copy error, ret=0x%x\n", (uint32_t)ret);
return -1;
}
REG_MWR(ISP_FEEDER_PARAM, (BIT_3 | BIT_2 | BIT_1), (feeder_info.data_type << 1));
return ret;
}
static int32_t isp_k_ct_block(struct isp_io_param *param,
struct isp_k_private *isp_private)
{
int32_t ret = 0;
uint32_t buf_size = 0;
unsigned long dst_buf = 0;
struct isp_dev_ct_info ct_info;
void *data_ptr = NULL;
buf_size = ISP_3D_LUT_ITEM * 4;
memset(&ct_info, 0x00, sizeof(ct_info));
ret = copy_from_user((void *)&ct_info, param->property_param, sizeof(ct_info));
if (0 != ret) {
printk("isp_k_ct_block: copy error, ret=0x%x\n", (uint32_t)ret);
return -1;
}
#ifdef CONFIG_64BIT
data_ptr = (void*)(((unsigned long)ct_info.data_ptr[1] << 32) | ct_info.data_ptr[0]);
#else
data_ptr = (void*)(ct_info.data_ptr[0]);
#endif
if (NULL == data_ptr || ct_info.size > buf_size) {
printk("isp_k_ct_block: memory error: %p %x.\n",
data_ptr, ct_info.size);
}
dst_buf = ISP_3D_LUT0_OUTPUT;
isp_private->ct_load_buf_id = ISP_3D_LUT_BUF0;
ret = copy_from_user((void *)dst_buf, data_ptr, ct_info.size);
if (0 != ret) {
printk("isp_k_ct_block: copy error, ret=0x%x\n", (uint32_t)ret);
return -1;
}
//REG_MWR(ISP_CT_PARAM, BIT_1, (isp_private->ct_load_buf_id << 1));
REG_MWR(ISP_CT_PARAM, BIT_0, ct_info.bypass);
return ret;
}
static int32_t isp_k_raw_sizer_bpc_bypass(struct isp_io_param *param)
{
int32_t ret = 0;
uint32_t bypass = 0;
ret = copy_from_user((void *)&bypass, param->property_param, sizeof(bypass));
if (0 != ret) {
printk("isp_k_raw_sizer_bpc_bypass: copy_from_user error, ret = 0x%x\n", (uint32_t)ret);
return -1;
}
if (bypass) {
REG_OWR(ISP_RAW_SIZER_PARAM, BIT_1);
} else {
REG_MWR(ISP_RAW_SIZER_PARAM, BIT_1, 0);
}
return ret;
}
static int32_t isp_k_cce_block_matrix(struct isp_io_param *param)
{
int32_t ret = 0;
uint32_t val = 0;
uint32_t val1 = 0;
struct isp_dev_cce_info_v1 cce_info;
memset(&cce_info, 0x00, sizeof(cce_info));
ret = copy_from_user((void *)&cce_info, param->property_param, sizeof(cce_info));
if (0 != ret) {
printk("isp_k_cce_block_matrix: copy error, ret=0x%x\n", (uint32_t)ret);
return -1;
}
val = ((cce_info.matrix[1] & 0x7FF) << 11) | (cce_info.matrix[0] & 0x7FF);
val1 = ((cce_info.matrix[3] & 0x7FF) << 11) | (cce_info.matrix[2] & 0x7FF);
if ((0 == val)
|| (0 == val1)) {
printk("isp_k_cce_block_matrix: copy error, 0x%x, 0x%x, 0x%x, 0x%x\n", cce_info.matrix[0], cce_info.matrix[1], cce_info.matrix[2], cce_info.matrix[3]);
return ret;
}
REG_MWR(ISP_CCE_PARAM, BIT_1, cce_info.mode << 1);
val = ((cce_info.matrix[1] & 0x7FF) << 11) | (cce_info.matrix[0] & 0x7FF);
REG_WR(ISP_CCE_MATRIX0, val);
val = ((cce_info.matrix[3] & 0x7FF) << 11) | (cce_info.matrix[2] & 0x7FF);
REG_WR(ISP_CCE_MATRIX1, val);
val = ((cce_info.matrix[5] & 0x7FF) << 11) | (cce_info.matrix[4] & 0x7FF);
REG_WR(ISP_CCE_MATRIX2, val);
val = ((cce_info.matrix[7] & 0x7FF) << 11) | (cce_info.matrix[6] & 0x7FF);
REG_WR(ISP_CCE_MATRIX3, val);
val = cce_info.matrix[8] & 0x7FF;
REG_WR(ISP_CCE_MATRIX4, val);
val = (cce_info.y_offset & 0x1FF) | ((cce_info.u_offset & 0x1FF) << 9)
| ((cce_info.v_offset & 0x1FF) << 18);
REG_WR(ISP_CCE_SHIFT, (val & 0x7FFFFFF));
return ret;
}
static int32_t isp_k_yiq_flicker_bypass(struct isp_io_param *param)
{
int32_t ret = 0;
uint32_t bypass = 0;
ret = copy_from_user((void *)&bypass, param->property_param, sizeof(bypass));
if (0 != ret) {
printk("isp_k_yiq_flicker_bypass: copy error, ret=0x%x\n", (uint32_t)ret);
return -1;
}
if (bypass) {
REG_OWR(ISP_YIQ_PARAM, BIT_2);
} else {
REG_MWR(ISP_YIQ_PARAM, BIT_2, 0);
}
return ret;
}
static int32_t isp_k_pingpang_frgb_gamc(struct coordinate_xy *nodes,
struct isp_k_private *isp_private)
{
int32_t ret = 0;
uint32_t i, j;
uint32_t val = 0;
unsigned long r_buf_addr;
unsigned long g_buf_addr;
unsigned long b_buf_addr;
struct coordinate_xy *p_nodes = NULL;
if (!nodes) {
ret = -1;
printk("isp_k_pingpang_frgb_gamc: node is null error .\n");
return ret;
}
p_nodes = nodes;
if (ISP_FRGB_GAMC_BUF0 == isp_private->full_gamma_buf_id) {
r_buf_addr = ISP_FGAMMA_R_BUF1_CH0;
g_buf_addr = ISP_FGAMMA_G_BUF1_CH0;
b_buf_addr = ISP_FGAMMA_B_BUF1_CH0;
isp_private->full_gamma_buf_id = ISP_FRGB_GAMC_BUF1;
} else {
r_buf_addr = ISP_FGAMMA_R_BUF0_CH0;
g_buf_addr = ISP_FGAMMA_G_BUF0_CH0;
b_buf_addr = ISP_FGAMMA_B_BUF0_CH0;
isp_private->full_gamma_buf_id = ISP_FRGB_GAMC_BUF0;
}
for(i = 0,j = 0;i < ISP_PINGPANG_FRGB_GAMC_NUM;i++,j+=4) {
REG_WR(r_buf_addr + j, p_nodes[i].node_y & 0xff);
REG_WR(g_buf_addr + j, p_nodes[i].node_y & 0xff);
REG_WR(b_buf_addr + j, p_nodes[i].node_y & 0xff);
}
val = ((isp_private->full_gamma_buf_id & 0x1 ) << 1) | ((isp_private->full_gamma_buf_id & 0x1) << 2) | ((isp_private->full_gamma_buf_id & 0x1 ) << 3);
REG_MWR(ISP_GAMMA_PARAM, 0x0000000E, val);
return ret;
}
static int32_t isp_k_gamma_block(struct isp_io_param *param,
struct isp_k_private *isp_private)
{
int32_t ret = 0;
uint32_t bypass;
struct isp_dev_gamma_info_v1 *param_p= (struct isp_dev_gamma_info_v1 *)param->property_param;
struct coordinate_xy *nodes = NULL;
nodes = (struct coordinate_xy *)isp_private->full_gamma_buf_addr;
if (!nodes) {
ret = -1;
printk("isp_k_gamma_block: alloc memory error.\n");
return -1;
}
ret = copy_from_user((void *)&bypass, (void *)¶m_p->bypass, sizeof(uint32_t));
if (0 != ret) {
printk("isp_k_gamma_block: copy bypass error, ret=0x%x\n", (uint32_t)ret);
return -1;
}
ret = copy_from_user((void *)nodes, (void *)param_p->nodes, ISP_FRGB_GAMMA_BUF_SIZE);
if (0 != ret) {
printk("isp_k_gamma_block: copy nodes error, ret=0x%x\n", (uint32_t)ret);
return -1;
}
ret = isp_k_pingpang_frgb_gamc(nodes, isp_private);
if (0 != ret) {
printk("isp_k_gamma_block: pingpang error, ret=0x%x\n", (uint32_t)ret);
return -1;
}
REG_MWR(ISP_GAMMA_PARAM, BIT_0, bypass);
return ret;
}
static int32_t isp_k_nlm_block(struct isp_io_param *param)
{
int32_t ret = 0;
uint32_t val = 0;
uint32_t i = 0;
struct isp_dev_nlm_info_v1 nlm_info;
uint32_t *buff0 = NULL;
uint32_t *buff1 = NULL;
uint32_t *buff2 = NULL;
unsigned long buf_addr = 0;
void *vst_addr = NULL;
void *ivst_addr = NULL;
void *nlm_addr = NULL;
ret = copy_from_user((void *)&nlm_info, param->property_param, sizeof(nlm_info));
if (0 != ret) {
printk("isp_k_nlm_block: copy error, ret=0x%x\n", (uint32_t)ret);
return -1;
}
buff0 = vzalloc(nlm_info.vst_len);
if (NULL == buff0) {
printk("isp_k_nlm_block:vst kmalloc error\n");
return -1;
}
buff1 = vzalloc(nlm_info.ivst_len);
if (NULL == buff1) {
printk("isp_k_nlm_block:ivst kmalloc error\n");
vfree(buff0);
return -1;
}
buff2 = vzalloc(nlm_info.nlm_len);
if (NULL == buff2) {
printk("isp_k_nlm_block:nlm kmalloc error\n");
vfree(buff0);
vfree(buff1);
return -1;
}
#ifdef CONFIG_64BIT
vst_addr = (void*)(((unsigned long)nlm_info.vst_addr[1] << 32) | nlm_info.vst_addr[0]);
#else
vst_addr = (void*)(nlm_info.vst_addr[0]);
#endif
ret = copy_from_user((void *)buff0, vst_addr, nlm_info.vst_len);
if (0 != ret) {
printk("isp_k_nlm_block: vst copy error, ret=0x%x\n", (uint32_t)ret);
vfree(buff0);
vfree(buff1);
vfree(buff2);
return -1;
}
#ifdef CONFIG_64BIT
ivst_addr = (void*)(((unsigned long)nlm_info.ivst_addr[1] << 32) | nlm_info.ivst_addr[0]);
#else
ivst_addr = (void*)(nlm_info.ivst_addr[0]);
#endif
ret = copy_from_user((void *)buff1, ivst_addr, nlm_info.ivst_len);
if (0 != ret) {
printk("isp_k_nlm_block: ivst copy error, ret=0x%x\n", (uint32_t)ret);
vfree(buff0);
vfree(buff1);
vfree(buff2);
return -1;
}
#ifdef CONFIG_64BIT
nlm_addr = (void*)(((unsigned long)nlm_info.nlm_addr[1] << 32) | nlm_info.nlm_addr[0]);
#else
nlm_addr = (void*)(nlm_info.nlm_addr[0]);
#endif
ret = copy_from_user((void *)buff2, nlm_addr, nlm_info.nlm_len);
if (0 != ret) {
printk("isp_k_nlm_block: nlm copy error, ret=0x%x\n", (uint32_t)ret);
vfree(buff0);
vfree(buff1);
vfree(buff2);
return -1;
}
REG_MWR(ISP_NLM_PARA, BIT_1, nlm_info.imp_opt_bypass << 1);
REG_MWR(ISP_NLM_PARA, BIT_2, nlm_info.flat_opt_bypass << 2);
REG_MWR(ISP_NLM_PARA, BIT_3, nlm_info.flat_thr_bypass << 3);
REG_MWR(ISP_NLM_PARA, BIT_4, nlm_info.direction_mode_bypass << 4);
REG_MWR(ISP_NLM_PARA, BIT_31, nlm_info.buf_sel);
for (i = 0; i < 5; i++) {
val = (nlm_info.thresh[i] & 0x3FFF) | ((nlm_info.cnt[i] & 0x1F) << 16)
| ((nlm_info.strength[i] & 0xFF) << 24);
REG_WR(ISP_NLM_FLAT_PARA_0 + i * 4, val);
}
REG_MWR(ISP_NLM_STERNGTH, 0x7F, nlm_info.streng_th);
REG_MWR(ISP_NLM_STERNGTH, 0xFF00, nlm_info.texture_dec << 8);
//REG_WR(ISP_NLM_IS_FLAT, nlm_info.is_flat & 0xFF);
REG_MWR(ISP_NLM_ADD_BACK, 0x7F, nlm_info.addback);
REG_MWR(ISP_NLM_ADD_BACK, BIT_7, nlm_info.opt_mode << 7);
REG_MWR(ISP_NLM_DIRECTION_0, BIT_17 | BIT_16, nlm_info.dist_mode << 16);
val = ((nlm_info.w_shift[0] & 0x3) << 4) | ((nlm_info.w_shift[1] & 0x3) << 6) | ((nlm_info.w_shift[2] & 0x3) << 8);
REG_MWR(ISP_NLM_DIRECTION_0, 0x3F0, val);
REG_MWR(ISP_NLM_DIRECTION_0, 0x7, nlm_info.cnt_th);
REG_MWR(ISP_NLM_DIRECTION_1, 0xFFFF0000, nlm_info.tdist_min_th << 16);
REG_MWR(ISP_NLM_DIRECTION_1, 0xFFFF, nlm_info.diff_th);
for (i = 0; i < 24; i++) {
val = (nlm_info.lut_w[i*3+0] & 0x3FF) | ((nlm_info.lut_w[i*3+1] & 0x3FF) << 10)
| ((nlm_info.lut_w[i*3+2] & 0x3FF) << 20);
REG_WR(ISP_NLM_LUT_W_0 + i * 4, val);
}
if(nlm_info.buf_sel) {
buf_addr = ISP_NLM_BUF1_CH0;
memcpy((void *)buf_addr, buff2, ISP_VST_IVST_NUM * sizeof(uint32_t));
} else {
buf_addr = ISP_NLM_BUF0_CH0;
memcpy((void *)buf_addr, buff2, ISP_VST_IVST_NUM * sizeof(uint32_t));
}
if (nlm_info.buf_sel ) {
buf_addr = ISP_VST_BUF1_CH0;
memcpy((void *)buf_addr, buff0, ISP_VST_IVST_NUM * sizeof(uint32_t));
} else {
buf_addr = ISP_VST_BUF0_CH0;
memcpy((void *)buf_addr, buff0, ISP_VST_IVST_NUM * sizeof(uint32_t));
}
if (nlm_info.buf_sel ) {
buf_addr = ISP_IVST_BUF1_CH0;
memcpy((void *)buf_addr, buff1, ISP_VST_IVST_NUM * sizeof(uint32_t));
} else {
buf_addr = ISP_IVST_BUF0_CH0;
memcpy((void *)buf_addr, buff1, ISP_VST_IVST_NUM * sizeof(uint32_t));
}
/*vst ivst follow nlm*/
REG_MWR(ISP_VST_PARA, BIT_1, nlm_info.buf_sel << 1);
REG_MWR(ISP_IVST_PARA, BIT_1, nlm_info.buf_sel << 1);
REG_MWR(ISP_NLM_PARA, BIT_0, nlm_info.bypass);
REG_MWR(ISP_IVST_PARA, BIT_0, nlm_info.bypass);
REG_MWR(ISP_VST_PARA, BIT_0, nlm_info.bypass);
vfree(buff0);
vfree(buff1);
vfree(buff2);
return ret;
}
static int32_t isp_k_edge_block(struct isp_io_param *param)
{
int32_t ret = 0;
struct isp_dev_edge_info_v1 edge_info;
uint32_t val = 0;
memset(&edge_info, 0x00, sizeof(edge_info));
ret = copy_from_user((void *)&edge_info, param->property_param, sizeof(edge_info));
if (0 != ret) {
printk("isp_k_edge_block: copy_from_user error, ret = 0x%x\n", (uint32_t)ret);
return -1;
}
REG_MWR(ISP_EE_CFG0, BIT_29 | BIT_28, edge_info.mode << 28);
val = (edge_info.ee_str_m_n & 0x7F) | ((edge_info.ee_str_m_p & 0x7F) << 7)
| ((edge_info.ee_str_d_n & 0x7F) << 14) | ((edge_info.ee_str_d_p & 0x7F) << 21);
REG_MWR(ISP_EE_CFG0, 0xFFFFFFF, val);
val = ((edge_info.ee_incr_d_p & 0xFF) << 8) | (edge_info.ee_incr_d_n & 0xFF);
REG_MWR(ISP_EE_CFG1, 0xFFFF, val);
val = ((edge_info.ee_thr_d_n & 0xFF) << 16) | ((edge_info.ee_thr_d_p & 0xFF) << 24);
REG_MWR(ISP_EE_CFG1, 0xFFFF0000, val);
val = (edge_info.ee_flat_thr_1 & 0xFF) | ((edge_info.ee_flat_thr_2 & 0xFF) << 8);
REG_MWR(ISP_EE_CFG2, 0xFFFF, val);
val = ((edge_info.ee_incr_m_n & 0xFF) << 16) | ((edge_info.ee_incr_m_p & 0xFF) << 24);
REG_MWR(ISP_EE_CFG2, 0xFFFF0000, val);
val = (edge_info.ee_txt_thr_1 & 0xFF) | ((edge_info.ee_txt_thr_2 & 0xFF) << 8)
| ((edge_info.ee_txt_thr_3 & 0xFF) << 16);
REG_WR(ISP_EE_CFG3, val);
val = ((edge_info.ee_corner_cor & 0x1) << 28) | ((edge_info.ee_corner_th_p & 0x1F) << 23)
| ((edge_info.ee_corner_th_n & 0x1F) << 18) | ((edge_info.ee_corner_gain_p & 0x7F) << 11)
| ((edge_info.ee_corner_gain_n & 0x7F) << 4) | ((edge_info.ee_corner_sm_p & 0x3) << 2)
| (edge_info.ee_corner_sm_n & 0x3);
REG_WR(ISP_EE_CFG4, val);
val = ((edge_info.ee_edge_smooth_mode & 0x3) << 26) | ((edge_info.ee_flat_smooth_mode & 0x3) << 24)
| ((edge_info.ee_smooth_thr & 0xFF) << 8) | (edge_info.ee_smooth_strength & 0xFF);
REG_MWR(ISP_EE_CFG5, 0xF00FFFF, val);
val = (edge_info.sigma & 0xFF) << 16;
REG_MWR(ISP_EE_CFG5, 0xFF0000, val);
val = ((edge_info.ee_str_b_p & 0xFF) << 24) | ((edge_info.ee_str_b_n & 0xFF) << 16)
| ((edge_info.ee_incr_b_p & 0xFF) << 8) | (edge_info.ee_incr_b_n & 0xFF);
REG_WR(ISP_EE_CFG6, val);
val = ((edge_info.ratio[1] & 0xFF) << 8) | (edge_info.ratio[0] & 0xFF);
REG_MWR(ISP_EE_CFG7, 0xFFFF, val);
val = (edge_info.ee_clip_after_smooth_en & 0x1) << 25;
REG_MWR(ISP_EE_CFG7, BIT_25, val);
val = ((edge_info.ipd_bypass & 0x1) << 24) | ((edge_info.ipd_flat_thr & 0xFF) << 16);
REG_MWR(ISP_EE_CFG7, 0x1FF0000, val);
val = (edge_info.ee_t1_cfg & 0x3FF) | ((edge_info.ee_t2_cfg & 0x3FF) << 10)
| ((edge_info.ee_t3_cfg & 0x3FF) << 20);
REG_WR(ISP_EE_ADP_CFG0, val);
val = (edge_info.ee_t4_cfg & 0x3FF) | ((edge_info.ee_cv_clip_n & 0xFF) << 16)
| ((edge_info.ee_cv_clip_p & 0xFF) << 24);
REG_WR(ISP_EE_ADP_CFG1, val);
val = (edge_info.ee_r1_cfg & 0xFF) | ((edge_info.ee_r2_cfg & 0xFF) << 8)
| ((edge_info.ee_r3_cfg & 0xFF) << 16);
REG_WR(ISP_EE_ADP_CFG2, val);
if (edge_info.bypass) {
REG_OWR(ISP_EE_PARAM, BIT_0);
} else {
REG_MWR(ISP_EE_PARAM, BIT_0, 0);
}
return ret;
}
int32_t dcam_start(void)
{
enum dcam_drv_rtn rtn = DCAM_RTN_SUCCESS;
int ret = 0;
DCAM_TRACE("DCAM DRV: dcam_start %x \n", s_dcam_mod.dcam_mode);
#ifdef DCAM_DEBUG
REG_MWR(CAP_CCIR_FRM_CTRL, BIT_5 | BIT_4, 1 << 4);
REG_MWR(CAP_MIPI_FRM_CTRL, BIT_5 | BIT_4, 1 << 4);
#endif
REG_WR(DCAM_INT_CLR, DCAM_IRQ_LINE_MASK);
REG_WR(DCAM_INT_MASK, DCAM_IRQ_LINE_MASK);
ret = request_irq(DCAM_IRQ,
dcam_isr_root,
IRQF_SHARED,
"DCAM",
&g_dcam_irq);
if (ret) {
DCAM_TRACE("dcam_start, error %d \n", ret);
return -DCAM_RTN_MAX;
}
if (s_dcam_mod.dcam_path1.valide) {
rtn = _dcam_path_trim(DCAM_PATH1);
DCAM_RTN_IF_ERR;
rtn = _dcam_path_scaler(DCAM_PATH1);
DCAM_RTN_IF_ERR;
rtn = _dcam_path_set_next_frm(DCAM_PATH1, true);
DCAM_RTN_IF_ERR;
REG_OWR(DCAM_CFG, BIT_0);
}
if (s_dcam_mod.dcam_path2.valide) {
rtn = _dcam_path_trim(DCAM_PATH2);
DCAM_RTN_IF_ERR;
rtn = _dcam_path_scaler(DCAM_PATH2);
DCAM_RTN_IF_ERR;
rtn = _dcam_path_set_next_frm(DCAM_PATH2, true);
DCAM_RTN_IF_ERR;
REG_OWR(DCAM_CFG, BIT_1);
REG_OWR(DCAM_BURST_GAP, BIT_20);
}
_dcam_force_copy();
_dcam_reg_trace();
printk("DCAM S \n");
REG_MWR(DCAM_PATH_CFG, BIT_0, 1);
if (s_dcam_mod.dcam_path1.valide) {
rtn = _dcam_path_set_next_frm(DCAM_PATH1, false);
DCAM_RTN_IF_ERR;
}
if (s_dcam_mod.dcam_path2.valide) {
rtn = _dcam_path_set_next_frm(DCAM_PATH2, false);
DCAM_RTN_IF_ERR;
}
_dcam_auto_copy();
return -rtn;
}
int32_t dcam_cap_cfg(enum dcam_cfg_id id, void *param)
{
enum dcam_drv_rtn rtn = DCAM_RTN_SUCCESS;
struct dcam_cap_desc *cap_desc = &s_dcam_mod.dcam_cap;
switch (id) {
case DCAM_CAP_SYNC_POL:
{
struct dcam_cap_sync_pol *sync_pol = (struct dcam_cap_sync_pol*)param;
DCAM_CHECK_PARAM_ZERO_POINTER(param);
if (DCAM_CAP_IF_CCIR == cap_desc->interface) {
if (sync_pol->vsync_pol > 1 ||
sync_pol->hsync_pol > 1 ||
sync_pol->pclk_pol > 1) {
rtn = DCAM_RTN_CAP_SYNC_POL_ERR;
} else {
REG_MWR(CAP_CCIR_CTRL, BIT_3, sync_pol->hsync_pol << 3);
REG_MWR(CAP_CCIR_CTRL, BIT_4, sync_pol->vsync_pol << 4);
if(0 == sync_pol->pclk_pol){
sci_glb_clr(CLK_DLY_CTRL, BIT_19);
}else{
sci_glb_set(CLK_DLY_CTRL, BIT_19);
}
}
} else {
if (sync_pol->need_href) {
REG_MWR(CAP_MIPI_CTRL, BIT_5, 1 << 5);
} else {
REG_MWR(CAP_MIPI_CTRL, BIT_5, 0 << 5);
}
}
break;
}
case DCAM_CAP_DATA_BITS:
{
enum dcam_cap_data_bits bits = *(enum dcam_cap_data_bits*)param;
DCAM_CHECK_PARAM_ZERO_POINTER(param);
if (DCAM_CAP_IF_CCIR == cap_desc->interface) {
if (DCAM_CAP_8_BITS == bits || DCAM_CAP_10_BITS == bits) {
REG_MWR(CAP_CCIR_CTRL, BIT_10 | BIT_9, 0 << 9);
} else if (DCAM_CAP_4_BITS == bits) {
REG_MWR(CAP_CCIR_CTRL, BIT_10 | BIT_9, 1 << 9);
} else if (DCAM_CAP_2_BITS == bits) {
REG_MWR(CAP_CCIR_CTRL, BIT_10 | BIT_9, 2 << 9);
} else if (DCAM_CAP_1_BITS == bits) {
REG_MWR(CAP_CCIR_CTRL, BIT_10 | BIT_9, 3 << 9);
} else {
rtn = DCAM_RTN_CAP_IN_BITS_ERR;
}
} else {
if (DCAM_CAP_12_BITS == bits) {
REG_MWR(CAP_MIPI_CTRL, BIT_4 | BIT_3, 2 << 3);
} else if (DCAM_CAP_10_BITS == bits) {
REG_MWR(CAP_MIPI_CTRL, BIT_4 | BIT_3, 1 << 3);
} else if (DCAM_CAP_8_BITS == bits) {
REG_MWR(CAP_MIPI_CTRL, BIT_4 | BIT_3, 0 << 3);
} else {
rtn = DCAM_RTN_CAP_IN_BITS_ERR;
}
}
break;
}
case DCAM_CAP_YUV_TYPE:
{
enum dcam_cap_pattern pat = *(enum dcam_cap_pattern*)param;
DCAM_CHECK_PARAM_ZERO_POINTER(param);
if (pat < DCAM_PATTERN_MAX) {
if (DCAM_CAP_IF_CCIR == cap_desc->interface)
REG_MWR(CAP_CCIR_CTRL, BIT_8 | BIT_7, pat << 7);
else
REG_MWR(CAP_MIPI_CTRL, BIT_8 | BIT_7, pat << 7);
} else {
rtn = DCAM_RTN_CAP_IN_YUV_ERR;
}
break;
}
case DCAM_CAP_PRE_SKIP_CNT:
{
uint32_t skip_num = *(uint32_t*)param;
DCAM_CHECK_PARAM_ZERO_POINTER(param);
if (skip_num > DCAM_CAP_SKIP_FRM_MAX) {
rtn = DCAM_RTN_CAP_SKIP_FRAME_ERR;
} else {
if (DCAM_CAP_IF_CCIR == cap_desc->interface)
REG_MWR(CAP_CCIR_FRM_CTRL, BIT_3 | BIT_2 | BIT_1 | BIT_0, skip_num);
else
REG_MWR(CAP_MIPI_FRM_CTRL, BIT_3 | BIT_2 | BIT_1 | BIT_0, skip_num);
}
break;
}
case DCAM_CAP_FRM_DECI:
{
uint32_t deci_factor = *(uint32_t*)param;
DCAM_CHECK_PARAM_ZERO_POINTER(param);
if (deci_factor < DCAM_FRM_DECI_FAC_MAX) {
if (DCAM_CAP_IF_CCIR == cap_desc->interface)
REG_MWR(CAP_CCIR_FRM_CTRL, BIT_5 | BIT_4, deci_factor << 4);
else
REG_MWR(CAP_MIPI_FRM_CTRL, BIT_5 | BIT_4, deci_factor << 4);
} else {
rtn = DCAM_RTN_CAP_FRAME_DECI_ERR;
}
break;
}
case DCAM_CAP_FRM_COUNT_CLR:
if (DCAM_CAP_IF_CCIR == cap_desc->interface)
REG_MWR(CAP_CCIR_FRM_CTRL, BIT_22, 1 << 22);
else
REG_MWR(CAP_MIPI_FRM_CTRL, BIT_22, 1 << 22);
break;
case DCAM_CAP_INPUT_RECT:
{
struct dcam_rect *rect = (struct dcam_rect*)param;
uint32_t tmp = 0;
DCAM_CHECK_PARAM_ZERO_POINTER(param);
if (rect->x > DCAM_CAP_FRAME_WIDTH_MAX ||
rect->y > DCAM_CAP_FRAME_HEIGHT_MAX ||
rect->w > DCAM_CAP_FRAME_WIDTH_MAX ||
rect->h > DCAM_CAP_FRAME_HEIGHT_MAX ) {
rtn = DCAM_RTN_CAP_FRAME_SIZE_ERR;
return -rtn;
}
if (DCAM_CAP_IF_CCIR == cap_desc->interface) {
if (DCAM_CAP_MODE_RAWRGB == cap_desc->input_format) {
tmp = rect->x | (rect->y << 16);
REG_WR(CAP_CCIR_START, tmp);
tmp = (rect->x + rect->w - 1);
tmp |= (rect->y + rect->h - 1) << 16;
REG_WR(CAP_CCIR_END, tmp);
} else {
tmp = (rect->x << 1) | (rect->y << 16);
REG_WR(CAP_CCIR_START, tmp);
tmp = ((rect->x + rect->w) << 1) - 1;
tmp |= (rect->y + rect->h - 1) << 16;
REG_WR(CAP_CCIR_END, tmp);
}
} else {
tmp = rect->x | (rect->y << 16);
REG_WR(CAP_MIPI_START, tmp);
tmp = (rect->x + rect->w - 1);
tmp |= (rect->y + rect->h - 1) << 16;
REG_WR(CAP_MIPI_END, tmp);
}
break;
}
case DCAM_CAP_IMAGE_XY_DECI:
{
struct dcam_cap_dec *cap_dec = (struct dcam_cap_dec*)param;
DCAM_CHECK_PARAM_ZERO_POINTER(param);
if (cap_dec->x_factor > DCAM_CAP_X_DECI_FAC_MAX ||
cap_dec->y_factor > DCAM_CAP_Y_DECI_FAC_MAX ) {
rtn = DCAM_RTN_CAP_XY_DECI_ERR;
} else {
if (DCAM_CAP_MODE_RAWRGB == cap_desc->input_format) {
if (cap_dec->x_factor > 1 ||
cap_dec->y_factor > 1) {
rtn = DCAM_RTN_CAP_XY_DECI_ERR;
}
}
if (DCAM_CAP_IF_CCIR == cap_desc->interface) {
REG_MWR(CAP_CCIR_IMG_DECI, BIT_1 | BIT_0, cap_dec->x_factor);
REG_MWR(CAP_CCIR_IMG_DECI, BIT_3 | BIT_2, cap_dec->y_factor << 2);
} else {
if (DCAM_CAP_MODE_RAWRGB == cap_desc->input_format) {
// REG_MWR(CAP_MIPI_IMG_DECI, BIT_0, cap_dec->x_factor); // for camera path
REG_MWR(CAP_MIPI_IMG_DECI, BIT_1, cap_dec->x_factor << 1);//for ISP
} else {
REG_MWR(CAP_MIPI_IMG_DECI, BIT_1 | BIT_0, cap_dec->x_factor);
REG_MWR(CAP_MIPI_IMG_DECI, BIT_3 | BIT_2, cap_dec->y_factor << 2);
}
}
}
break;
}
case DCAM_CAP_JPEG_SET_BUF_LEN:
{
uint32_t jpg_buf_size = *(uint32_t*)param;
DCAM_CHECK_PARAM_ZERO_POINTER(param);
jpg_buf_size = jpg_buf_size/DCAM_JPG_BUF_UNIT;
if (jpg_buf_size >= DCAM_JPG_UNITS) {
rtn = DCAM_RTN_CAP_JPEG_BUF_LEN_ERR;
} else {
if (DCAM_CAP_IF_CCIR == cap_desc->interface)
REG_WR(CAP_CCIR_JPG_CTRL,jpg_buf_size);
else
REG_WR(CAP_MIPI_JPG_CTRL,jpg_buf_size);
}
break;
}
case DCAM_CAP_TO_ISP:
{
uint32_t need_isp = *(uint32_t*)param;
DCAM_CHECK_PARAM_ZERO_POINTER(param);
if (need_isp) {
REG_MWR(DCAM_CFG, BIT_7, 1 << 7);
} else {
REG_MWR(DCAM_CFG, BIT_7, 0 << 7);
}
break;
}
case DCAM_CAP_DATA_PACKET:
{
uint32_t is_loose = *(uint32_t*)param;
DCAM_CHECK_PARAM_ZERO_POINTER(param);
if (DCAM_CAP_IF_CSI2 == cap_desc->interface &&
DCAM_CAP_MODE_RAWRGB == cap_desc->input_format) {
if (is_loose) {
REG_MWR(CAP_MIPI_CTRL, BIT_0, 1);
} else {
REG_MWR(CAP_MIPI_CTRL, BIT_0, 0);
}
} else {
rtn = DCAM_RTN_MODE_ERR;
}
break;
}
case DCAM_CAP_SAMPLE_MODE:
{
enum dcam_capture_mode samp_mode = *(enum dcam_capture_mode*)param;
DCAM_CHECK_PARAM_ZERO_POINTER(param);
if (samp_mode >= DCAM_CAPTURE_MODE_MAX) {
rtn = DCAM_RTN_MODE_ERR;
} else {
if (DCAM_CAP_IF_CSI2 == cap_desc->interface) {
REG_MWR(CAP_MIPI_CTRL, BIT_6, samp_mode << 6);
} else {
REG_MWR(CAP_CCIR_CTRL, BIT_6, samp_mode << 6);
}
}
break;
}
default:
rtn = DCAM_RTN_IO_ID_ERR;
break;
}
return -rtn;
}
static int32_t isp_k_yiq_block_ygamma(struct isp_io_param *param)
{
int32_t ret = 0;
uint32_t val = 0;
struct isp_dev_yiq_ygamma_info ygamma_info;
memset(&ygamma_info, 0x00, sizeof(ygamma_info));
ret = copy_from_user((void *)&ygamma_info, param->property_param, sizeof(ygamma_info));
if (0 != ret) {
printk("isp_k_yiq_block_ygamma: copy error, ret=0x%x\n", (uint32_t)ret);
return -1;
}
val = (ygamma_info.x_node[0] << 24)
| (ygamma_info.x_node[1] << 16)
| (ygamma_info.x_node[2] << 8)
| ygamma_info.x_node[3];
REG_WR(ISP_YGAMMA_X0, val);
val = (ygamma_info.x_node[4] << 24)
| (ygamma_info.x_node[5] << 16)
| (ygamma_info.x_node[6] << 8)
| ygamma_info.x_node[7];
REG_WR(ISP_YGAMMA_X1, val);
val = (ygamma_info.y_node[0] << 24)
| (ygamma_info.y_node[1] << 16)
| (ygamma_info.y_node[2] << 8)
| ygamma_info.y_node[3];
REG_WR(ISP_YGAMMA_Y0, val);
val = (ygamma_info.y_node[4] << 24)
| (ygamma_info.y_node[5] << 16)
| (ygamma_info.y_node[6] << 8)
| ygamma_info.y_node[7];
REG_WR(ISP_YGAMMA_Y1, val);
val = (ygamma_info.y_node[8] << 24)
| (ygamma_info.y_node[9] << 16);
REG_WR(ISP_YGAMMA_Y2, val);
val = ((ygamma_info.node_index[0] & 0x07) << 24)
| ((ygamma_info.node_index[1] & 0x07) << 21)
| ((ygamma_info.node_index[2] & 0x07) << 18)
| ((ygamma_info.node_index[3] & 0x07) << 15)
| ((ygamma_info.node_index[4] & 0x07) << 12)
| ((ygamma_info.node_index[5] & 0x07) << 9)
| ((ygamma_info.node_index[6] & 0x07) << 6)
| ((ygamma_info.node_index[7] & 0x07) << 3)
| (ygamma_info.node_index[8] & 0x07);
REG_WR(ISP_YGAMMA_NODE_IDX, val);
if (ygamma_info.bypass) {
REG_OWR(ISP_YIQ_PARAM, BIT_0);
} else {
REG_MWR(ISP_YIQ_PARAM, BIT_0, 0);
}
return ret;
}
