#include <soc/iomap.h> #include <soc/pci_devs.h> #include <soc/pmc.h> #include <soc/pm.h> #include <cpu/x86/smm.h> #include <soc/pcr.h> #include <soc/ramstage.h> #if IS_ENABLED(CONFIG_CHROMEOS) #include <vendorcode/google/chromeos/chromeos.h> #include <vendorcode/google/chromeos/vbnv_layout.h> #endif static const struct reg_script pch_pmc_misc_init_script[] = { /* SLP_S4=4s, SLP_S3=50ms, disable SLP_X stretching after SUS loss. */ REG_PCI_RMW16(GEN_PMCON_B, ~(S4MAW_MASK | SLP_S3_MIN_ASST_WDTH_MASK), S4MAW_4S | SLP_S3_MIN_ASST_WDTH_50MS | DIS_SLP_X_STRCH_SUS_UP), /* Enable SCI and clear SLP requests. */ REG_IO_RMW32(ACPI_BASE_ADDRESS + PM1_CNT, ~SLP_TYP, SCI_EN), REG_SCRIPT_END }; static const struct reg_script pmc_write1_to_clear_script[] = { REG_PCI_OR32(GEN_PMCON_A, 0), REG_PCI_OR32(GEN_PMCON_B, 0), REG_PCI_OR32(GEN_PMCON_B, 0), REG_RES_OR32(PWRMBASE, GBLRST_CAUSE0, 0), REG_RES_OR32(PWRMBASE, GBLRST_CAUSE1, 0), REG_SCRIPT_END };
rtc_failed = reg8 & RTC_BATTERY_DEAD; if (rtc_failed) { reg8 &= ~RTC_BATTERY_DEAD; pci_write_config8(dev, GEN_PMCON_3, reg8); printk(BIOS_DEBUG, "rtc_failed = 0x%x\n", rtc_failed); } if (IS_ENABLED(CONFIG_VBOOT_VBNV_CMOS)) init_vbnv_cmos(rtc_failed); else cmos_init(rtc_failed); } static const struct reg_script pch_misc_init_script[] = { /* Setup SLP signal assertion, SLP_S4=4s, SLP_S3=50ms */ REG_PCI_RMW16(GEN_PMCON_3, ~((3 << 4)|(1 << 10)), (1 << 3)|(1 << 11)|(1 << 12)), /* Prepare sleep mode */ REG_IO_RMW32(ACPI_BASE_ADDRESS + PM1_CNT, ~SLP_TYP, SCI_EN), /* Setup NMI on errors, disable SERR */ REG_IO_RMW8(0x61, ~0xf0, (1 << 2)), /* Disable NMI sources */ REG_IO_OR8(0x70, (1 << 7)), /* Indicate DRAM init done for MRC */ REG_PCI_OR8(GEN_PMCON_2, (1 << 7)), /* Enable BIOS updates outside of SMM */ REG_PCI_RMW8(0xdc, ~(1 << 5), 0), /* Clear status bits to prevent unexpected wake */ REG_MMIO_OR32(RCBA_BASE_ADDRESS + 0x3310, 0x0000002f), REG_MMIO_RMW32(RCBA_BASE_ADDRESS + 0x3f02, ~0x0000000f, 0), /* Enable PCIe Releaxed Order */ REG_MMIO_OR32(RCBA_BASE_ADDRESS + 0x2314, (1 << 31) | (1 << 7)),
}; const struct reg_script xhci_init_resume_script[] = { /* Setup USB3 phy */ REG_SCRIPT_NEXT(usb3_phy_script), /* Initialize host controller */ REG_SCRIPT_NEXT(xhci_init_script), /* BAR + 0x80e0[16,9,6]=001b, leave bit 24=0 to prevent HC reset */ REG_RES_RMW32(PCI_BASE_ADDRESS_0, 0x80e0, ~0x01010200, 0x00000040), REG_SCRIPT_END }; const struct reg_script xhci_clock_gating_script[] = { /* ConfigureXhciClockGating() */ /* D20:F0:40[21:19,18,10:8]=000,1,001 (don't write byte 3) */ REG_PCI_RMW16(0x40, ~0x0600, 0x0100), REG_PCI_RMW8(0x42, ~0x38, 0x04), /* D20:F0:44[5:3]=001b */ REG_PCI_RMW16(0x44, ~0x0030, 0x0008), /* D20:F0:A0[19:18]=01b */ REG_PCI_RMW32(0xa0, ~0x00080000, 0x00040000), /* D20:F0:A4[15:0]=0x00 */ REG_PCI_WRITE16(0xa4, 0x0000), /* D20:F0:B0[21:17,14:13]=0000000b */ REG_PCI_RMW32(0xb0, ~0x00376000, 0x00000000), /* D20:F0:50[31:0]=0x0bce6e5f */ REG_PCI_WRITE32(0x50, 0x0bce6e5f), REG_SCRIPT_END }; /* Warm Reset a USB3 port */