#include <soc/romstage.h> #include <soc/reg_access.h> #include <string.h> static const struct reg_script clear_smi_and_wake_events[] = { /* Clear any SMI or wake events */ REG_GPE0_READ(R_QNC_GPE0BLK_GPE0S), REG_GPE0_READ(R_QNC_GPE0BLK_SMIS), REG_GPE0_OR(R_QNC_GPE0BLK_GPE0S, B_QNC_GPE0BLK_GPE0S_ALL), REG_GPE0_OR(R_QNC_GPE0BLK_SMIS, B_QNC_GPE0BLK_SMIS_ALL), REG_SCRIPT_END }; static const struct reg_script legacy_gpio_init[] = { /* Temporarily enable the legacy GPIO controller */ REG_PCI_WRITE32(R_QNC_LPC_GBA_BASE, IO_ADDRESS_VALID | LEGACY_GPIO_BASE_ADDRESS), /* Temporarily enable the GPE controller */ REG_PCI_WRITE32(R_QNC_LPC_GPE0BLK, IO_ADDRESS_VALID | GPE0_BASE_ADDRESS), REG_PCI_OR8(PCI_COMMAND, PCI_COMMAND_IO), REG_SCRIPT_END }; static const struct reg_script i2c_gpio_controller_init[] = { /* Temporarily enable the GPIO controller */ REG_PCI_WRITE32(PCI_BASE_ADDRESS_0, I2C_BASE_ADDRESS), REG_PCI_WRITE32(PCI_BASE_ADDRESS_1, GPIO_BASE_ADDRESS), REG_PCI_OR8(PCI_COMMAND, PCI_COMMAND_MEMORY), REG_SCRIPT_END };
#include <device/device.h> #include <device/pci.h> #include <device/pci_ids.h> #include <reg_script.h> #include <soc/iosf.h> #include <soc/nvs.h> #include <soc/pci_devs.h> #include <soc/ramstage.h> #include "chip.h" static const struct reg_script emmc_ops[] = { /* Enable 2ms card stable feature. */ REG_PCI_OR32(0xa8, (1 << 24)), /* Enable HS200 */ REG_PCI_WRITE32(0xa0, 0x446cc801), REG_PCI_WRITE32(0xa4, 0x80000807), /* cfio_regs_score_special_bits.sdio1_dummy_loopback_en=1 */ REG_IOSF_OR(IOSF_PORT_SCORE, 0x49c0, (1 << 3)), /* CLKGATE_EN_1 . cr_scc_mipihsi_clkgate_en = 1 */ REG_IOSF_RMW(IOSF_PORT_CCU, 0x1c, ~(3 << 26), (1 << 26)), /* Set slew for HS200 */ REG_IOSF_RMW(IOSF_PORT_SCORE, 0x48c0, ~0x3c, 0x3c), REG_IOSF_RMW(IOSF_PORT_SCORE, 0x48c4, ~0x3c, 0x3c), /* Max timeout */ REG_RES_WRITE8(PCI_BASE_ADDRESS_0, 0x002e, 0x0e), REG_SCRIPT_END, }; static void emmc_init(device_t dev) {
* but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. */ #include <arch/io.h> #include <device/pci_def.h> #include <device/early_smbus.h> #include <intelblocks/smbus.h> #include <reg_script.h> #include <soc/pci_devs.h> #include "smbuslib.h" static const struct reg_script smbus_init_script[] = { /* Set SMBus I/O base address */ REG_PCI_WRITE32(PCI_BASE_ADDRESS_4, SMBUS_IO_BASE), /* Set SMBus enable */ REG_PCI_WRITE8(HOSTC, HST_EN), /* Enable I/O access */ REG_PCI_WRITE16(PCI_COMMAND, PCI_COMMAND_IO), /* Disable interrupts */ REG_IO_WRITE8(SMBUS_IO_BASE + SMBHSTCTL, 0), /* Clear errors */ REG_IO_WRITE8(SMBUS_IO_BASE + SMBHSTSTAT, 0xff), /* Indicate the end of this array by REG_SCRIPT_END */ REG_SCRIPT_END, }; u16 smbus_read_word(u32 smbus_dev, u8 addr, u8 offset) { return smbus_read16(SMBUS_IO_BASE, addr, offset);
#include <device/device.h> #include <device/pci_def.h> #include <reg_script.h> #include <soc/iomap.h> #include <soc/lpc.h> #include <soc/pch.h> #include <soc/pci_devs.h> #include <soc/pm.h> #include <soc/rcba.h> #include <soc/romstage.h> #include <soc/smbus.h> #include <soc/intel/broadwell/chip.h> const struct reg_script pch_early_init_script[] = { /* Setup southbridge BARs */ REG_PCI_WRITE32(RCBA, RCBA_BASE_ADDRESS | 1), REG_PCI_WRITE32(PMBASE, ACPI_BASE_ADDRESS | 1), REG_PCI_WRITE8(ACPI_CNTL, ACPI_EN), REG_PCI_WRITE32(GPIO_BASE, GPIO_BASE_ADDRESS | 1), REG_PCI_WRITE8(GPIO_CNTL, GPIO_EN), /* Set COM1/COM2 decode range */ REG_PCI_WRITE16(LPC_IO_DEC, 0x0010), /* Enable legacy decode ranges */ REG_PCI_WRITE16(LPC_EN, CNF1_LPC_EN | CNF2_LPC_EN | GAMEL_LPC_EN | COMA_LPC_EN | KBC_LPC_EN | MC_LPC_EN), /* Enable IOAPIC */ REG_MMIO_WRITE16(RCBA_BASE_ADDRESS + OIC, 0x0100), /* Read back for posted write */ REG_MMIO_READ16(RCBA_BASE_ADDRESS + OIC),
* Foundation, Inc. */ #include <arch/io.h> #include <console/console.h> #include <device/pci_ids.h> #include <device/pci_def.h> #include <reg_script.h> #include <soc/iomap.h> #include <soc/pci_devs.h> #include <soc/smbus.h> #include <soc/romstage.h> static const struct reg_script smbus_init_script[] = { /* Set SMBUS I/O base address */ REG_PCI_WRITE32(SMB_BASE, SMBUS_BASE_ADDRESS | 1), /* Set SMBUS enable */ REG_PCI_WRITE8(HOSTC, HST_EN), /* Enable I/O access */ REG_PCI_WRITE16(PCI_COMMAND, PCI_COMMAND_IO), /* Disable interrupts */ REG_IO_WRITE8(SMBUS_BASE_ADDRESS + SMBHSTCTL, 0), /* Clear errors */ REG_IO_WRITE8(SMBUS_BASE_ADDRESS + SMBHSTSTAT, 0xff), /* Indicate the end of this array by REG_SCRIPT_END */ REG_SCRIPT_END, }; void enable_smbus(void) { reg_script_run_on_dev(PCH_DEV_SMBUS, smbus_init_script);
#include <soc/iosf.h> #include <soc/pci_devs.h> #include <soc/ramstage.h> static const struct reg_script init_ops[] = { /* Enable no snoop traffic. */ REG_PCI_OR16(0x78, 1 << 11), /* Configure HDMI codec connection. */ REG_PCI_OR32(0xc4, 1 << 1), REG_PCI_OR8(0x43, (1 << 3) | (1 << 6)), REG_IOSF_WRITE(IOSF_PORT_PMC, PUNIT_PWRGT_CONTROL, 0xc0), REG_IOSF_WRITE(IOSF_PORT_PMC, PUNIT_PWRGT_CONTROL, 0x00), /* Configure internal settings. */ REG_PCI_OR32(0xc0, 0x7 << 21), REG_PCI_OR32(0xc4, (0x3 << 26) | (1 << 13) | (1 << 10)), REG_PCI_WRITE32(0xc8, 0x82a30000), REG_PCI_RMW32(0xd0, ~(1 << 31), 0x0), /* Disable docking. */ REG_PCI_RMW8(0x4d, ~(1 << 7), 0), REG_SCRIPT_END, }; static const uint32_t hdmi_codec_verb_table[] = { /* coreboot specific header */ 0x80862882, /* vid did for hdmi codec */ 0x00000000, /* subsystem id */ 0x00000003, /* number of jacks */ /* pin widget 5 - port B */ 0x20471c10, 0x20471d00,
const struct reg_script xhci_clock_gating_script[] = { /* ConfigureXhciClockGating() */ /* D20:F0:40[21:19,18,10:8]=000,1,001 (don't write byte 3) */ REG_PCI_RMW16(0x40, ~0x0600, 0x0100), REG_PCI_RMW8(0x42, ~0x38, 0x04), /* D20:F0:44[5:3]=001b */ REG_PCI_RMW16(0x44, ~0x0030, 0x0008), /* D20:F0:A0[19:18]=01b */ REG_PCI_RMW32(0xa0, ~0x00080000, 0x00040000), /* D20:F0:A4[15:0]=0x00 */ REG_PCI_WRITE16(0xa4, 0x0000), /* D20:F0:B0[21:17,14:13]=0000000b */ REG_PCI_RMW32(0xb0, ~0x00376000, 0x00000000), /* D20:F0:50[31:0]=0x0bce6e5f */ REG_PCI_WRITE32(0x50, 0x0bce6e5f), REG_SCRIPT_END }; /* Warm Reset a USB3 port */ static void xhci_reset_port_usb3(device_t dev, int port) { struct reg_script reset_port_usb3_script[] = { /* Issue Warm Port Rest to the port */ REG_RES_OR32(PCI_BASE_ADDRESS_0, XHCI_USB3_PORTSC(port), XHCI_USB3_PORTSC_WPR), /* Wait up to 100ms for it to complete */ REG_RES_POLL32(PCI_BASE_ADDRESS_0, XHCI_USB3_PORTSC(port), XHCI_USB3_PORTSC_WRC, XHCI_USB3_PORTSC_WRC, XHCI_RESET_TIMEOUT), /* Clear change status bits, do not set PED */
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. */ #include <arch/early_variables.h> #include <delay.h> #include <device/pci_def.h> #include <reg_script.h> #include <stdint.h> #include <uart8250.h> #include <soc/iobp.h> #include <soc/serialio.h> const struct reg_script uart_init[] = { /* Set MMIO BAR */ REG_PCI_WRITE32(PCI_BASE_ADDRESS_0, CONFIG_TTYS0_BASE), /* Enable Memory access and Bus Master */ REG_PCI_OR32(PCI_COMMAND, PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER), /* Initialize LTR */ REG_MMIO_RMW32(CONFIG_TTYS0_BASE + SIO_REG_PPR_GEN, ~SIO_REG_PPR_GEN_LTR_MODE_MASK, 0), REG_MMIO_RMW32(CONFIG_TTYS0_BASE + SIO_REG_PPR_RST, ~(SIO_REG_PPR_RST_ASSERT), 0), /* Take UART out of reset */ REG_MMIO_OR32(CONFIG_TTYS0_BASE + SIO_REG_PPR_RST, SIO_REG_PPR_RST_ASSERT), /* Set M and N divisor inputs and enable clock */ REG_MMIO_WRITE32(CONFIG_TTYS0_BASE + SIO_REG_PPR_CLOCK, SIO_REG_PPR_CLOCK_EN | SIO_REG_PPR_CLOCK_UPDATE | (SIO_REG_PPR_CLOCK_N_DIV << 16) | (SIO_REG_PPR_CLOCK_M_DIV << 1)),