/* ************************************************************************* *\ * FUNCTION: mdfld_dsi_tpo_ic_init * * DESCRIPTION: This function is called only by mrst_dsi_mode_set and * restore_display_registers. since this function does not * acquire the mutex, it is important that the calling function * does! \* ************************************************************************* */ static void mdfld_dsi_tpo_ic_init(struct mdfld_dsi_config *dsi_config, u32 pipe) { struct drm_device *dev = dsi_config->dev; u32 dcsChannelNumber = dsi_config->channel_num; u32 gen_data_reg = MIPI_HS_GEN_DATA_REG(pipe); u32 gen_ctrl_reg = MIPI_HS_GEN_CTRL_REG(pipe); u32 gen_ctrl_val = GEN_LONG_WRITE; DRM_INFO("Enter mrst init TPO MIPI display.\n"); gen_ctrl_val |= dcsChannelNumber << DCS_CHANNEL_NUMBER_POS; /* Flip page order */ mdfld_wait_for_HS_DATA_FIFO(dev, pipe); REG_WRITE(gen_data_reg, 0x00008036); mdfld_wait_for_HS_CTRL_FIFO(dev, pipe); REG_WRITE(gen_ctrl_reg, gen_ctrl_val | (0x02 << WORD_COUNTS_POS)); /* 0xF0 */ mdfld_wait_for_HS_DATA_FIFO(dev, pipe); REG_WRITE(gen_data_reg, 0x005a5af0); mdfld_wait_for_HS_CTRL_FIFO(dev, pipe); REG_WRITE(gen_ctrl_reg, gen_ctrl_val | (0x03 << WORD_COUNTS_POS)); /* Write protection key */ mdfld_wait_for_HS_DATA_FIFO(dev, pipe); REG_WRITE(gen_data_reg, 0x005a5af1); mdfld_wait_for_HS_CTRL_FIFO(dev, pipe); REG_WRITE(gen_ctrl_reg, gen_ctrl_val | (0x03 << WORD_COUNTS_POS)); /* 0xFC */ mdfld_wait_for_HS_DATA_FIFO(dev, pipe); REG_WRITE(gen_data_reg, 0x005a5afc); mdfld_wait_for_HS_CTRL_FIFO(dev, pipe); REG_WRITE(gen_ctrl_reg, gen_ctrl_val | (0x03 << WORD_COUNTS_POS)); /* 0xB7 */ mdfld_wait_for_HS_DATA_FIFO(dev, pipe); REG_WRITE(gen_data_reg, 0x770000b7); mdfld_wait_for_HS_DATA_FIFO(dev, pipe); REG_WRITE(gen_data_reg, 0x00000044); mdfld_wait_for_HS_CTRL_FIFO(dev, pipe); REG_WRITE(gen_ctrl_reg, gen_ctrl_val | (0x05 << WORD_COUNTS_POS)); /* 0xB6 */ mdfld_wait_for_HS_DATA_FIFO(dev, pipe); REG_WRITE(gen_data_reg, 0x000a0ab6); mdfld_wait_for_HS_CTRL_FIFO(dev, pipe); REG_WRITE(gen_ctrl_reg, gen_ctrl_val | (0x03 << WORD_COUNTS_POS)); /* 0xF2 */ mdfld_wait_for_HS_DATA_FIFO(dev, pipe); REG_WRITE(gen_data_reg, 0x081010f2); mdfld_wait_for_HS_DATA_FIFO(dev, pipe); REG_WRITE(gen_data_reg, 0x4a070708); mdfld_wait_for_HS_DATA_FIFO(dev, pipe); REG_WRITE(gen_data_reg, 0x000000c5); mdfld_wait_for_HS_CTRL_FIFO(dev, pipe); REG_WRITE(gen_ctrl_reg, gen_ctrl_val | (0x09 << WORD_COUNTS_POS)); /* 0xF8 */ mdfld_wait_for_HS_DATA_FIFO(dev, pipe); REG_WRITE(gen_data_reg, 0x024003f8); mdfld_wait_for_HS_DATA_FIFO(dev, pipe); REG_WRITE(gen_data_reg, 0x01030a04); mdfld_wait_for_HS_DATA_FIFO(dev, pipe); REG_WRITE(gen_data_reg, 0x0e020220); mdfld_wait_for_HS_DATA_FIFO(dev, pipe); REG_WRITE(gen_data_reg, 0x00000004); mdfld_wait_for_HS_CTRL_FIFO(dev, pipe); REG_WRITE(gen_ctrl_reg, gen_ctrl_val | (0x0d << WORD_COUNTS_POS)); /* 0xE2 */ mdfld_wait_for_HS_DATA_FIFO(dev, pipe); REG_WRITE(gen_data_reg, 0x398fc3e2); mdfld_wait_for_HS_DATA_FIFO(dev, pipe); REG_WRITE(gen_data_reg, 0x0000916f); mdfld_wait_for_HS_CTRL_FIFO(dev, pipe); REG_WRITE(gen_ctrl_reg, gen_ctrl_val | (0x06 << WORD_COUNTS_POS)); /* 0xB0 */ mdfld_wait_for_HS_DATA_FIFO(dev, pipe); REG_WRITE(gen_data_reg, 0x000000b0); mdfld_wait_for_HS_CTRL_FIFO(dev, pipe); REG_WRITE(gen_ctrl_reg, gen_ctrl_val | (0x02 << WORD_COUNTS_POS)); /* 0xF4 */ mdfld_wait_for_HS_DATA_FIFO(dev, pipe); REG_WRITE(gen_data_reg, 0x240242f4); mdfld_wait_for_HS_DATA_FIFO(dev, pipe); REG_WRITE(gen_data_reg, 0x78ee2002); mdfld_wait_for_HS_DATA_FIFO(dev, pipe); REG_WRITE(gen_data_reg, 0x2a071050); mdfld_wait_for_HS_DATA_FIFO(dev, pipe); REG_WRITE(gen_data_reg, 0x507fee10); mdfld_wait_for_HS_DATA_FIFO(dev, pipe); REG_WRITE(gen_data_reg, 0x10300710); mdfld_wait_for_HS_CTRL_FIFO(dev, pipe); REG_WRITE(gen_ctrl_reg, gen_ctrl_val | (0x14 << WORD_COUNTS_POS)); /* 0xBA */ mdfld_wait_for_HS_DATA_FIFO(dev, pipe); REG_WRITE(gen_data_reg, 0x19fe07ba); mdfld_wait_for_HS_DATA_FIFO(dev, pipe); REG_WRITE(gen_data_reg, 0x101c0a31); mdfld_wait_for_HS_DATA_FIFO(dev, pipe); REG_WRITE(gen_data_reg, 0x00000010); mdfld_wait_for_HS_CTRL_FIFO(dev, pipe); REG_WRITE(gen_ctrl_reg, gen_ctrl_val | (0x09 << WORD_COUNTS_POS)); /* 0xBB */ mdfld_wait_for_HS_DATA_FIFO(dev, pipe); REG_WRITE(gen_data_reg, 0x28ff07bb); mdfld_wait_for_HS_DATA_FIFO(dev, pipe); REG_WRITE(gen_data_reg, 0x24280a31); mdfld_wait_for_HS_DATA_FIFO(dev, pipe); REG_WRITE(gen_data_reg, 0x00000034); mdfld_wait_for_HS_CTRL_FIFO(dev, pipe); REG_WRITE(gen_ctrl_reg, gen_ctrl_val | (0x09 << WORD_COUNTS_POS)); /* 0xFB */ mdfld_wait_for_HS_DATA_FIFO(dev, pipe); REG_WRITE(gen_data_reg, 0x535d05fb); mdfld_wait_for_HS_DATA_FIFO(dev, pipe); REG_WRITE(gen_data_reg, 0x1b1a2130); mdfld_wait_for_HS_DATA_FIFO(dev, pipe); REG_WRITE(gen_data_reg, 0x221e180e); mdfld_wait_for_HS_DATA_FIFO(dev, pipe); REG_WRITE(gen_data_reg, 0x131d2120); mdfld_wait_for_HS_DATA_FIFO(dev, pipe); REG_WRITE(gen_data_reg, 0x535d0508); mdfld_wait_for_HS_DATA_FIFO(dev, pipe); REG_WRITE(gen_data_reg, 0x1c1a2131); mdfld_wait_for_HS_DATA_FIFO(dev, pipe); REG_WRITE(gen_data_reg, 0x231f160d); mdfld_wait_for_HS_DATA_FIFO(dev, pipe); REG_WRITE(gen_data_reg, 0x111b2220); mdfld_wait_for_HS_DATA_FIFO(dev, pipe); REG_WRITE(gen_data_reg, 0x535c2008); mdfld_wait_for_HS_DATA_FIFO(dev, pipe); REG_WRITE(gen_data_reg, 0x1f1d2433); mdfld_wait_for_HS_DATA_FIFO(dev, pipe); REG_WRITE(gen_data_reg, 0x2c251a10); mdfld_wait_for_HS_DATA_FIFO(dev, pipe); REG_WRITE(gen_data_reg, 0x2c34372d); mdfld_wait_for_HS_DATA_FIFO(dev, pipe); REG_WRITE(gen_data_reg, 0x00000023); mdfld_wait_for_HS_CTRL_FIFO(dev, pipe); REG_WRITE(gen_ctrl_reg, gen_ctrl_val | (0x31 << WORD_COUNTS_POS)); /* 0xFA */ mdfld_wait_for_HS_DATA_FIFO(dev, pipe); REG_WRITE(gen_data_reg, 0x525c0bfa); mdfld_wait_for_HS_DATA_FIFO(dev, pipe); REG_WRITE(gen_data_reg, 0x1c1c232f); mdfld_wait_for_HS_DATA_FIFO(dev, pipe); REG_WRITE(gen_data_reg, 0x2623190e); mdfld_wait_for_HS_DATA_FIFO(dev, pipe); REG_WRITE(gen_data_reg, 0x18212625); mdfld_wait_for_HS_DATA_FIFO(dev, pipe); REG_WRITE(gen_data_reg, 0x545d0d0e); mdfld_wait_for_HS_DATA_FIFO(dev, pipe); REG_WRITE(gen_data_reg, 0x1e1d2333); mdfld_wait_for_HS_DATA_FIFO(dev, pipe); REG_WRITE(gen_data_reg, 0x26231a10); mdfld_wait_for_HS_DATA_FIFO(dev, pipe); REG_WRITE(gen_data_reg, 0x1a222725); mdfld_wait_for_HS_DATA_FIFO(dev, pipe); REG_WRITE(gen_data_reg, 0x545d280f); mdfld_wait_for_HS_DATA_FIFO(dev, pipe); REG_WRITE(gen_data_reg, 0x21202635); mdfld_wait_for_HS_DATA_FIFO(dev, pipe); REG_WRITE(gen_data_reg, 0x31292013); mdfld_wait_for_HS_DATA_FIFO(dev, pipe); REG_WRITE(gen_data_reg, 0x31393d33); mdfld_wait_for_HS_DATA_FIFO(dev, pipe); REG_WRITE(gen_data_reg, 0x00000029); mdfld_wait_for_HS_CTRL_FIFO(dev, pipe); REG_WRITE(gen_ctrl_reg, gen_ctrl_val | (0x31 << WORD_COUNTS_POS)); /* Set DM */ mdfld_wait_for_HS_DATA_FIFO(dev, pipe); REG_WRITE(gen_data_reg, 0x000100f7); mdfld_wait_for_HS_CTRL_FIFO(dev, pipe); REG_WRITE(gen_ctrl_reg, gen_ctrl_val | (0x03 << WORD_COUNTS_POS)); }
bool ath_hw_keyreset(struct ath_common *common, u16 entry) { u32 keyType; void *ah = common->ah; if (entry >= common->keymax) { ath_err(common, "keycache entry %u out of range\n", entry); return false; } keyType = REG_READ(ah, AR_KEYTABLE_TYPE(entry)); REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), 0); REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), 0); REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), 0); REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), 0); REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), 0); REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), AR_KEYTABLE_TYPE_CLR); REG_WRITE(ah, AR_KEYTABLE_MAC0(entry), 0); REG_WRITE(ah, AR_KEYTABLE_MAC1(entry), 0); if (keyType == AR_KEYTABLE_TYPE_TKIP) { u16 micentry = entry + 64; REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), 0); REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), 0); REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), 0); REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), 0); if (common->crypt_caps & ATH_CRYPT_CAP_MIC_COMBINED) { REG_WRITE(ah, AR_KEYTABLE_KEY4(micentry), 0); REG_WRITE(ah, AR_KEYTABLE_TYPE(micentry), AR_KEYTABLE_TYPE_CLR); } } return true; }
bool ath9k_hw_resettxqueue(struct ath_hw *ah, u32 q) { struct ath_common *common = ath9k_hw_common(ah); struct ath9k_channel *chan = ah->curchan; struct ath9k_tx_queue_info *qi; u32 cwMin, chanCwMin, value; qi = &ah->txq[q]; if (qi->tqi_type == ATH9K_TX_QUEUE_INACTIVE) { ath_dbg(common, ATH_DBG_QUEUE, "Reset TXQ, inactive queue: %u\n", q); return true; } ath_dbg(common, ATH_DBG_QUEUE, "Reset TX queue: %u\n", q); if (qi->tqi_cwmin == ATH9K_TXQ_USEDEFAULT) { if (chan && IS_CHAN_B(chan)) chanCwMin = INIT_CWMIN_11B; else chanCwMin = INIT_CWMIN; for (cwMin = 1; cwMin < chanCwMin; cwMin = (cwMin << 1) | 1); } else cwMin = qi->tqi_cwmin; ENABLE_REGWRITE_BUFFER(ah); REG_WRITE(ah, AR_DLCL_IFS(q), SM(cwMin, AR_D_LCL_IFS_CWMIN) | SM(qi->tqi_cwmax, AR_D_LCL_IFS_CWMAX) | SM(qi->tqi_aifs, AR_D_LCL_IFS_AIFS)); REG_WRITE(ah, AR_DRETRY_LIMIT(q), SM(INIT_SSH_RETRY, AR_D_RETRY_LIMIT_STA_SH) | SM(INIT_SLG_RETRY, AR_D_RETRY_LIMIT_STA_LG) | SM(qi->tqi_shretry, AR_D_RETRY_LIMIT_FR_SH)); REG_WRITE(ah, AR_QMISC(q), AR_Q_MISC_DCU_EARLY_TERM_REQ); if (AR_SREV_9340(ah)) REG_WRITE(ah, AR_DMISC(q), AR_D_MISC_CW_BKOFF_EN | AR_D_MISC_FRAG_WAIT_EN | 0x1); else REG_WRITE(ah, AR_DMISC(q), AR_D_MISC_CW_BKOFF_EN | AR_D_MISC_FRAG_WAIT_EN | 0x2); if (qi->tqi_cbrPeriod) { REG_WRITE(ah, AR_QCBRCFG(q), SM(qi->tqi_cbrPeriod, AR_Q_CBRCFG_INTERVAL) | SM(qi->tqi_cbrOverflowLimit, AR_Q_CBRCFG_OVF_THRESH)); REG_SET_BIT(ah, AR_QMISC(q), AR_Q_MISC_FSP_CBR | (qi->tqi_cbrOverflowLimit ? AR_Q_MISC_CBR_EXP_CNTR_LIMIT_EN : 0)); } if (qi->tqi_readyTime && (qi->tqi_type != ATH9K_TX_QUEUE_CAB)) { REG_WRITE(ah, AR_QRDYTIMECFG(q), SM(qi->tqi_readyTime, AR_Q_RDYTIMECFG_DURATION) | AR_Q_RDYTIMECFG_EN); } REG_WRITE(ah, AR_DCHNTIME(q), SM(qi->tqi_burstTime, AR_D_CHNTIME_DUR) | (qi->tqi_burstTime ? AR_D_CHNTIME_EN : 0)); if (qi->tqi_burstTime && (qi->tqi_qflags & TXQ_FLAG_RDYTIME_EXP_POLICY_ENABLE)) REG_SET_BIT(ah, AR_QMISC(q), AR_Q_MISC_RDYTIME_EXP_POLICY); if (qi->tqi_qflags & TXQ_FLAG_BACKOFF_DISABLE) REG_SET_BIT(ah, AR_DMISC(q), AR_D_MISC_POST_FR_BKOFF_DIS); REGWRITE_BUFFER_FLUSH(ah); if (qi->tqi_qflags & TXQ_FLAG_FRAG_BURST_BACKOFF_ENABLE) REG_SET_BIT(ah, AR_DMISC(q), AR_D_MISC_FRAG_BKOFF_EN); switch (qi->tqi_type) { case ATH9K_TX_QUEUE_BEACON: ENABLE_REGWRITE_BUFFER(ah); REG_SET_BIT(ah, AR_QMISC(q), AR_Q_MISC_FSP_DBA_GATED | AR_Q_MISC_BEACON_USE | AR_Q_MISC_CBR_INCR_DIS1); REG_SET_BIT(ah, AR_DMISC(q), (AR_D_MISC_ARB_LOCKOUT_CNTRL_GLOBAL << AR_D_MISC_ARB_LOCKOUT_CNTRL_S) | AR_D_MISC_BEACON_USE | AR_D_MISC_POST_FR_BKOFF_DIS); REGWRITE_BUFFER_FLUSH(ah); /* * cwmin and cwmax should be 0 for beacon queue * but not for IBSS as we would create an imbalance * on beaconing fairness for participating nodes. */ if (AR_SREV_9300_20_OR_LATER(ah) && ah->opmode != NL80211_IFTYPE_ADHOC) { REG_WRITE(ah, AR_DLCL_IFS(q), SM(0, AR_D_LCL_IFS_CWMIN) | SM(0, AR_D_LCL_IFS_CWMAX) | SM(qi->tqi_aifs, AR_D_LCL_IFS_AIFS)); } break; case ATH9K_TX_QUEUE_CAB: ENABLE_REGWRITE_BUFFER(ah); REG_SET_BIT(ah, AR_QMISC(q), AR_Q_MISC_FSP_DBA_GATED | AR_Q_MISC_CBR_INCR_DIS1 | AR_Q_MISC_CBR_INCR_DIS0); value = (qi->tqi_readyTime - (ah->config.sw_beacon_response_time - ah->config.dma_beacon_response_time) - ah->config.additional_swba_backoff) * 1024; REG_WRITE(ah, AR_QRDYTIMECFG(q), value | AR_Q_RDYTIMECFG_EN); REG_SET_BIT(ah, AR_DMISC(q), (AR_D_MISC_ARB_LOCKOUT_CNTRL_GLOBAL << AR_D_MISC_ARB_LOCKOUT_CNTRL_S)); REGWRITE_BUFFER_FLUSH(ah); break; case ATH9K_TX_QUEUE_PSPOLL: REG_SET_BIT(ah, AR_QMISC(q), AR_Q_MISC_CBR_INCR_DIS1); break; case ATH9K_TX_QUEUE_UAPSD: REG_SET_BIT(ah, AR_DMISC(q), AR_D_MISC_POST_FR_BKOFF_DIS); break; default: break; } if (qi->tqi_intFlags & ATH9K_TXQ_USE_LOCKOUT_BKOFF_DIS) { REG_SET_BIT(ah, AR_DMISC(q), SM(AR_D_MISC_ARB_LOCKOUT_CNTRL_GLOBAL, AR_D_MISC_ARB_LOCKOUT_CNTRL) | AR_D_MISC_POST_FR_BKOFF_DIS); } if (AR_SREV_9300_20_OR_LATER(ah)) REG_WRITE(ah, AR_Q_DESC_CRCCHK, AR_Q_DESC_CRCCHK_EN); if (qi->tqi_qflags & TXQ_FLAG_TXOKINT_ENABLE) ah->txok_interrupt_mask |= 1 << q; else ah->txok_interrupt_mask &= ~(1 << q); if (qi->tqi_qflags & TXQ_FLAG_TXERRINT_ENABLE) ah->txerr_interrupt_mask |= 1 << q; else ah->txerr_interrupt_mask &= ~(1 << q); if (qi->tqi_qflags & TXQ_FLAG_TXDESCINT_ENABLE) ah->txdesc_interrupt_mask |= 1 << q; else ah->txdesc_interrupt_mask &= ~(1 << q); if (qi->tqi_qflags & TXQ_FLAG_TXEOLINT_ENABLE) ah->txeol_interrupt_mask |= 1 << q; else ah->txeol_interrupt_mask &= ~(1 << q); if (qi->tqi_qflags & TXQ_FLAG_TXURNINT_ENABLE) ah->txurn_interrupt_mask |= 1 << q; else ah->txurn_interrupt_mask &= ~(1 << q); ath9k_hw_set_txq_interrupts(ah, qi); return true; }
bool ath9k_hw_set_channel(struct ath_hw *ah, struct ath9k_channel *chan) { u32 channelSel = 0; u32 bModeSynth = 0; u32 aModeRefSel = 0; u32 reg32 = 0; u16 freq; struct chan_centers centers; ath9k_hw_get_channel_centers(ah, chan, ¢ers); freq = centers.synth_center; if (freq < 4800) { u32 txctl; if (((freq - 2192) % 5) == 0) { channelSel = ((freq - 672) * 2 - 3040) / 10; bModeSynth = 0; } else if (((freq - 2224) % 5) == 0) { channelSel = ((freq - 704) * 2 - 3040) / 10; bModeSynth = 1; } else { DPRINTF(ah->ah_sc, ATH_DBG_CHANNEL, "Invalid channel %u MHz\n", freq); return false; } channelSel = (channelSel << 2) & 0xff; channelSel = ath9k_hw_reverse_bits(channelSel, 8); txctl = REG_READ(ah, AR_PHY_CCK_TX_CTRL); if (freq == 2484) { REG_WRITE(ah, AR_PHY_CCK_TX_CTRL, txctl | AR_PHY_CCK_TX_CTRL_JAPAN); } else { REG_WRITE(ah, AR_PHY_CCK_TX_CTRL, txctl & ~AR_PHY_CCK_TX_CTRL_JAPAN); } } else if ((freq % 20) == 0 && freq >= 5120) { channelSel = ath9k_hw_reverse_bits(((freq - 4800) / 20 << 2), 8); aModeRefSel = ath9k_hw_reverse_bits(1, 2); } else if ((freq % 10) == 0) { channelSel = ath9k_hw_reverse_bits(((freq - 4800) / 10 << 1), 8); if (AR_SREV_9100(ah) || AR_SREV_9160_10_OR_LATER(ah)) aModeRefSel = ath9k_hw_reverse_bits(2, 2); else aModeRefSel = ath9k_hw_reverse_bits(1, 2); } else if ((freq % 5) == 0) { channelSel = ath9k_hw_reverse_bits((freq - 4800) / 5, 8); aModeRefSel = ath9k_hw_reverse_bits(1, 2); } else { DPRINTF(ah->ah_sc, ATH_DBG_CHANNEL, "Invalid channel %u MHz\n", freq); return false; } reg32 = (channelSel << 8) | (aModeRefSel << 2) | (bModeSynth << 1) | (1 << 5) | 0x1; REG_WRITE(ah, AR_PHY(0x37), reg32); ah->curchan = chan; ah->curchan_rad_index = -1; return true; }
static int mv88e6123_61_65_setup_port(struct dsa_switch *ds, int p) { int addr = REG_PORT(p); u16 val; if (dsa_is_cpu_port(ds, p) || ds->dsa_port_mask & (1 << p)) REG_WRITE(addr, 0x01, 0x003e); else REG_WRITE(addr, 0x01, 0x0003); REG_WRITE(addr, 0x02, 0x0000); val = 0x0433; if (dsa_is_cpu_port(ds, p)) { if (ds->dst->tag_protocol == htons(ETH_P_EDSA)) val |= 0x3300; else val |= 0x0100; } if (ds->dsa_port_mask & (1 << p)) val |= 0x0100; if (p == dsa_upstream_port(ds)) val |= 0x000c; REG_WRITE(addr, 0x04, val); REG_WRITE(addr, 0x05, dsa_is_cpu_port(ds, p) ? 0x8000 : 0x0000); val = (p & 0xf) << 12; if (dsa_is_cpu_port(ds, p)) val |= ds->phys_port_mask; else val |= 1 << dsa_upstream_port(ds); REG_WRITE(addr, 0x06, val); REG_WRITE(addr, 0x07, 0x0000); REG_WRITE(addr, 0x08, 0x2080); REG_WRITE(addr, 0x09, 0x0001); REG_WRITE(addr, 0x0a, 0x0000); REG_WRITE(addr, 0x0b, 1 << p); REG_WRITE(addr, 0x0c, 0x0000); REG_WRITE(addr, 0x0d, 0x0000); REG_WRITE(addr, 0x0f, ETH_P_EDSA); REG_WRITE(addr, 0x18, 0x3210); REG_WRITE(addr, 0x19, 0x7654); return 0; }
static void ath9k_ani_reset_old(struct ath_hw *ah, bool is_scanning) { struct ar5416AniState *aniState; struct ath9k_channel *chan = ah->curchan; struct ath_common *common = ath9k_hw_common(ah); if (!DO_ANI(ah)) return; aniState = &ah->curchan->ani; if (ah->opmode != NL80211_IFTYPE_STATION && ah->opmode != NL80211_IFTYPE_ADHOC) { ath_dbg(common, ANI, "Reset ANI state opmode %u\n", ah->opmode); ah->stats.ast_ani_reset++; if (ah->opmode == NL80211_IFTYPE_AP) { /* * ath9k_hw_ani_control() will only process items set on * ah->ani_function */ if (IS_CHAN_2GHZ(chan)) ah->ani_function = (ATH9K_ANI_SPUR_IMMUNITY_LEVEL | ATH9K_ANI_FIRSTEP_LEVEL); else ah->ani_function = 0; } ath9k_hw_ani_control(ah, ATH9K_ANI_NOISE_IMMUNITY_LEVEL, 0); ath9k_hw_ani_control(ah, ATH9K_ANI_SPUR_IMMUNITY_LEVEL, 0); ath9k_hw_ani_control(ah, ATH9K_ANI_FIRSTEP_LEVEL, 0); ath9k_hw_ani_control(ah, ATH9K_ANI_OFDM_WEAK_SIGNAL_DETECTION, !ATH9K_ANI_USE_OFDM_WEAK_SIG); ath9k_hw_ani_control(ah, ATH9K_ANI_CCK_WEAK_SIGNAL_THR, ATH9K_ANI_CCK_WEAK_SIG_THR); ath9k_ani_restart(ah); return; } if (aniState->noiseImmunityLevel != 0) ath9k_hw_ani_control(ah, ATH9K_ANI_NOISE_IMMUNITY_LEVEL, aniState->noiseImmunityLevel); if (aniState->spurImmunityLevel != 0) ath9k_hw_ani_control(ah, ATH9K_ANI_SPUR_IMMUNITY_LEVEL, aniState->spurImmunityLevel); if (aniState->ofdmWeakSigDetectOff) ath9k_hw_ani_control(ah, ATH9K_ANI_OFDM_WEAK_SIGNAL_DETECTION, !aniState->ofdmWeakSigDetectOff); if (aniState->cckWeakSigThreshold) ath9k_hw_ani_control(ah, ATH9K_ANI_CCK_WEAK_SIGNAL_THR, aniState->cckWeakSigThreshold); if (aniState->firstepLevel != 0) ath9k_hw_ani_control(ah, ATH9K_ANI_FIRSTEP_LEVEL, aniState->firstepLevel); ath9k_ani_restart(ah); ENABLE_REGWRITE_BUFFER(ah); REG_WRITE(ah, AR_PHY_ERR_MASK_1, AR_PHY_ERR_OFDM_TIMING); REG_WRITE(ah, AR_PHY_ERR_MASK_2, AR_PHY_ERR_CCK_TIMING); REGWRITE_BUFFER_FLUSH(ah); }
static bool ath9k_hw_ani_read_counters(struct ath_hw *ah) { struct ath_common *common = ath9k_hw_common(ah); struct ar5416AniState *aniState = &ah->curchan->ani; u32 ofdm_base = 0; u32 cck_base = 0; u32 ofdmPhyErrCnt, cckPhyErrCnt; u32 phyCnt1, phyCnt2; int32_t listenTime; ath_hw_cycle_counters_update(common); listenTime = ath_hw_get_listen_time(common); if (listenTime <= 0) { ah->stats.ast_ani_lneg_or_lzero++; ath9k_ani_restart(ah); return false; } if (!use_new_ani(ah)) { ofdm_base = AR_PHY_COUNTMAX - ah->config.ofdm_trig_high; cck_base = AR_PHY_COUNTMAX - ah->config.cck_trig_high; } aniState->listenTime += listenTime; ath9k_hw_update_mibstats(ah, &ah->ah_mibStats); phyCnt1 = REG_READ(ah, AR_PHY_ERR_1); phyCnt2 = REG_READ(ah, AR_PHY_ERR_2); if (!use_new_ani(ah) && (phyCnt1 < ofdm_base || phyCnt2 < cck_base)) { if (phyCnt1 < ofdm_base) { ath_dbg(common, ANI, "phyCnt1 0x%x, resetting counter value to 0x%x\n", phyCnt1, ofdm_base); REG_WRITE(ah, AR_PHY_ERR_1, ofdm_base); REG_WRITE(ah, AR_PHY_ERR_MASK_1, AR_PHY_ERR_OFDM_TIMING); } if (phyCnt2 < cck_base) { ath_dbg(common, ANI, "phyCnt2 0x%x, resetting counter value to 0x%x\n", phyCnt2, cck_base); REG_WRITE(ah, AR_PHY_ERR_2, cck_base); REG_WRITE(ah, AR_PHY_ERR_MASK_2, AR_PHY_ERR_CCK_TIMING); } return false; } ofdmPhyErrCnt = phyCnt1 - ofdm_base; ah->stats.ast_ani_ofdmerrs += ofdmPhyErrCnt - aniState->ofdmPhyErrCount; aniState->ofdmPhyErrCount = ofdmPhyErrCnt; cckPhyErrCnt = phyCnt2 - cck_base; ah->stats.ast_ani_cckerrs += cckPhyErrCnt - aniState->cckPhyErrCount; aniState->cckPhyErrCount = cckPhyErrCnt; return true; }
void cmd_loop() { while(1) { /* Wait for a command */ while(ub.command == NULL) { } esp_command_req_t *command = ub.command; ub.command = NULL; /* provide easy access for 32-bit data words */ uint32_t *data_words = (uint32_t *)command->data_buf; /* Send command response header */ esp_command_response_t resp = { .resp = 1, .op_ret = command->op, .len_ret = 0, /* esptool.py ignores this value */ .value = 0, }; /* ESP_READ_REG is the only command that needs to write into the 'resp' structure before we send it back. */ if (command->op == ESP_READ_REG && command->data_len == 4) { resp.value = REG_READ(data_words[0]); } /* Send the command response. */ SLIP_send_frame_delimiter(); SLIP_send_frame_data_buf(&resp, sizeof(esp_command_response_t)); if(command->data_len > MAX_WRITE_BLOCK+16) { SLIP_send_frame_data(ESP_BAD_DATA_LEN); SLIP_send_frame_data(0xEE); SLIP_send_frame_delimiter(); continue; } /* ... some commands will insert in-frame response data between here and when we send the end of the frame */ esp_command_error error = ESP_CMD_NOT_IMPLEMENTED; int status = 0; /* First stage of command processing - before sending error/status */ switch (command->op) { case ESP_ERASE_FLASH: error = verify_data_len(command, 0) || SPIEraseChip(); break; case ESP_ERASE_REGION: /* Params for ERASE_REGION are addr, len */ error = verify_data_len(command, 8) || handle_flash_erase(data_words[0], data_words[1]); break; case ESP_SET_BAUD: /* ESP_SET_BAUD sends two args, we ignore the second one */ error = verify_data_len(command, 8); /* actual baud setting happens after we send the reply */ break; case ESP_READ_FLASH: error = verify_data_len(command, 16); /* actual data is sent after we send the reply */ break; case ESP_FLASH_VERIFY_MD5: /* unsure why the MD5 command has 4 params but we only pass 2 of them, but this is in ESP32 ROM so we can't mess with it. */ error = verify_data_len(command, 16) || handle_flash_get_md5sum(data_words[0], data_words[1]); break; case ESP_FLASH_BEGIN: /* parameters (interpreted differently to ROM flasher): 0 - erase_size (used as total size to write) 1 - num_blocks (ignored) 2 - block_size (should be MAX_WRITE_BLOCK, relies on num_blocks * block_size >= erase_size) 3 - offset (used as-is) */ if (command->data_len == 16 && data_words[2] != MAX_WRITE_BLOCK) { error = ESP_BAD_BLOCKSIZE; } else { error = verify_data_len(command, 16) || handle_flash_begin(data_words[0], data_words[3]); } break; case ESP_FLASH_DEFLATED_BEGIN: /* parameters: 0 - uncompressed size 1 - num_blocks (based on compressed size) 2 - block_size (should be MAX_WRITE_BLOCK, total bytes over serial = num_blocks * block_size) 3 - offset (used as-is) */ if (command->data_len == 16 && data_words[2] != MAX_WRITE_BLOCK) { error = ESP_BAD_BLOCKSIZE; } else { error = verify_data_len(command, 16) || handle_flash_deflated_begin(data_words[0], data_words[1] * data_words[2], data_words[3]); } break; case ESP_FLASH_DATA: case ESP_FLASH_DEFLATED_DATA: /* ACK DATA commands immediately, then process them a few lines down, allowing next command to buffer */ if(is_in_flash_mode()) { error = get_flash_error(); int payload_len = command->data_len - 16; if (data_words[0] != payload_len) { /* First byte of data payload header is length (repeated) as a word */ error = ESP_BAD_DATA_LEN; } uint8_t data_checksum = calculate_checksum(command->data_buf + 16, payload_len); if (data_checksum != command->checksum) { error = ESP_BAD_DATA_CHECKSUM; } } else { error = ESP_NOT_IN_FLASH_MODE; } break; case ESP_FLASH_END: case ESP_FLASH_DEFLATED_END: error = handle_flash_end(); break; case ESP_SPI_SET_PARAMS: /* data params: fl_id, total_size, block_size, sector_Size, page_size, status_mask */ error = verify_data_len(command, 24) || handle_spi_set_params(data_words, &status); break; case ESP_SPI_ATTACH: /* parameter is 'hspi mode' (0, 1 or a pin mask for ESP32. Ignored on ESP8266.) */ error = verify_data_len(command, 4) || handle_spi_attach(data_words[0]); break; case ESP_WRITE_REG: /* params are addr, value, mask (ignored), delay_us (ignored) */ error = verify_data_len(command, 16); if (error == ESP_OK) { REG_WRITE(data_words[0], data_words[1]); } break; case ESP_READ_REG: /* actual READ_REG operation happens higher up */ error = verify_data_len(command, 4); break; case ESP_MEM_BEGIN: error = verify_data_len(command, 16) || handle_mem_begin(data_words[0], data_words[3]); break; case ESP_MEM_DATA: error = handle_mem_data(command->data_buf + 16, command->data_len - 16); break; case ESP_MEM_END: error = verify_data_len(command, 8) || handle_mem_finish(); break; case ESP_RUN_USER_CODE: /* Returning from here will run user code, ie standard boot process This command does not send a response. */ return; } SLIP_send_frame_data(error); SLIP_send_frame_data(status); SLIP_send_frame_delimiter(); /* Some commands need to do things after after sending this response */ if (error == ESP_OK) { switch(command->op) { case ESP_SET_BAUD: ets_delay_us(10000); uart_div_modify(0, baud_rate_to_divider(data_words[0])); ets_delay_us(1000); break; case ESP_READ_FLASH: /* args are: offset, length, block_size, max_in_flight */ handle_flash_read(data_words[0], data_words[1], data_words[2], data_words[3]); break; case ESP_FLASH_DATA: /* drop into flashing mode, discard 16 byte payload header */ handle_flash_data(command->data_buf + 16, command->data_len - 16); break; case ESP_FLASH_DEFLATED_DATA: handle_flash_deflated_data(command->data_buf + 16, command->data_len - 16); break; case ESP_FLASH_DEFLATED_END: case ESP_FLASH_END: /* passing 0 as parameter for ESP_FLASH_END means reboot now */ if (data_words[0] == 0) { /* Flush the FLASH_END response before rebooting */ #ifdef ESP32 uart_tx_flush(0); #endif ets_delay_us(10000); software_reset(); } break; case ESP_MEM_END: if (data_words[1] != 0) { void (*entrypoint_fn)(void) = (void (*))data_words[1]; /* this is a little different from the ROM loader, which exits the loader routine and _then_ calls this function. But for our purposes so far, having a bit of extra stuff on the stack doesn't really matter. */ entrypoint_fn(); } break; } } } } extern uint32_t _bss_start; extern uint32_t _bss_end; void __attribute__((used)) stub_main(); #ifdef ESP8266 __asm__ ( ".global stub_main_8266\n" ".literal_position\n" ".align 4\n" "stub_main_8266:\n" /* ESP8266 wrapper for "stub_main()" manipulates the return address in * a0, so 'return' from here runs user code. * * After setting a0, we jump directly to stub_main_inner() which is a * normal C function * * Adapted from similar approach used by Cesanta Software for ESP8266 * flasher stub. * */ "movi a0, 0x400010a8;" "j stub_main;"); #endif /* This function is called from stub_main, with return address reset to point to user code. */ void stub_main() { const uint32_t greeting = 0x4941484f; /* OHAI */ /* this points to stub_main now, clear for next boot */ ets_set_user_start(0); /* zero bss */ for(uint32_t *p = &_bss_start; p < &_bss_end; p++) { *p = 0; } SLIP_send(&greeting, 4); /* All UART reads come via uart_isr */ ub.reading_buf = ub.buf_a; ets_isr_attach(ETS_UART0_INUM, uart_isr, NULL); SET_PERI_REG_MASK(UART_INT_ENA(0), UART_RX_INTS); ets_isr_unmask(1 << ETS_UART0_INUM); /* Configure default SPI flash functionality. Can be overriden later by esptool.py. */ #ifdef ESP8266 SelectSpiFunction(); #else uint32_t spiconfig = ets_efuse_get_spiconfig(); uint32_t strapping = REG_READ(GPIO_STRAP_REG); /* If GPIO1 (U0TXD) is pulled low and no other boot mode is set in efuse, assume HSPI flash mode (same as normal boot) */ if (spiconfig == 0 && (strapping & 0x1c) == 0x08) { spiconfig = 1; /* HSPI flash mode */ } spi_flash_attach(spiconfig, 0); #endif SPIParamCfg(0, 16*1024*1024, FLASH_BLOCK_SIZE, FLASH_SECTOR_SIZE, FLASH_PAGE_SIZE, FLASH_STATUS_MASK); cmd_loop(); /* if cmd_loop returns, it's due to ESP_RUN_USER_CODE command. */ return; }
static int ahb_enable_wmac(u_int16_t devid, u_int16_t wlanNum) { u_int32_t reset; u_int32_t enable; if (((devid & AR5315_REV_MAJ_M) == AR5315_REV_MAJ) || ((devid & AR5315_REV_MAJ_M) == AR5317_REV_MAJ)) { u_int32_t reg; u_int32_t *en = (u_int32_t *) AR5315_AHB_ARB_CTL; KASSERT(wlanNum == 0, ("invalid wlan # %d", wlanNum)); /* Enable Arbitration for WLAN */ *en |= AR5315_ARB_WLAN; /* Enable global swapping so this looks like a normal BE system */ reg = REG_READ(AR5315_ENDIAN_CTL); reg |= AR5315_CONFIG_WLAN; REG_WRITE(AR5315_ENDIAN_CTL, reg); /* wake up the MAC */ /* NOTE: for the following write to succeed the * RST_AHB_ARB_CTL should be set to 0. This driver * assumes that the register has been set to 0 by boot loader */ reg = REG_READ(AR5315_PCI_MAC_SCR); reg = (reg & ~AR5315_PCI_MAC_SCR_SLMODE_M) | (AR5315_PCI_MAC_SCR_SLM_FWAKE << AR5315_PCI_MAC_SCR_SLMODE_S); REG_WRITE(AR5315_PCI_MAC_SCR, reg); /* wait for the MAC to wakeup */ while (REG_READ(AR5315_PCI_MAC_PCICFG) & AR5315_PCI_MAC_PCICFG_SPWR_DN); } else { switch (wlanNum) { case AR531X_WLAN0_NUM: reset = (AR531X_RESET_WLAN0 | AR531X_RESET_WARM_WLAN0_MAC | AR531X_RESET_WARM_WLAN0_BB); enable = AR531X_ENABLE_WLAN0; break; case AR531X_WLAN1_NUM: reset = (AR531X_RESET_WLAN1 | AR531X_RESET_WARM_WLAN1_MAC | AR531X_RESET_WARM_WLAN1_BB); enable = AR531X_ENABLE_WLAN1; break; default: return -ENODEV; } /* reset the MAC or suffer lots of AHB PROC errors */ REG_WRITE(AR531X_RESETCTL, REG_READ(AR531X_RESETCTL) | reset); mdelay(15); /* take it out of reset */ REG_WRITE(AR531X_RESETCTL, REG_READ(AR531X_RESETCTL) & ~reset); udelay(25); /* enable it */ REG_WRITE(AR531X_ENABLE, REG_READ(AR531X_ENABLE) | enable); } return 0; }
static u16 get_reg(struct eth_device *dev, int regno) { struct cs8900_priv *priv = (struct cs8900_priv *)(dev->priv); REG_WRITE(regno, &priv->regs->pptr); return REG_READ(&priv->regs->pdata); }
static void put_reg(struct eth_device *dev, int regno, u16 val) { struct cs8900_priv *priv = (struct cs8900_priv *)(dev->priv); REG_WRITE(regno, &priv->regs->pptr); REG_WRITE(val, &priv->regs->pdata); }
void mdfld_dsi_dpi_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode, struct drm_display_mode *adjusted_mode) { struct mdfld_dsi_encoder *dsi_encoder = mdfld_dsi_encoder(encoder); struct mdfld_dsi_dpi_output *dpi_output = MDFLD_DSI_DPI_OUTPUT(dsi_encoder); struct mdfld_dsi_config *dsi_config = mdfld_dsi_encoder_get_config(dsi_encoder); struct drm_device *dev = dsi_config->dev; struct drm_psb_private *dev_priv = dev->dev_private; int pipe = mdfld_dsi_encoder_get_pipe(dsi_encoder); u32 pipeconf_reg = PIPEACONF; u32 dspcntr_reg = DSPACNTR; u32 pipeconf = dev_priv->pipeconf[pipe]; u32 dspcntr = dev_priv->dspcntr[pipe]; u32 mipi = MIPI_PORT_EN | PASS_FROM_SPHY_TO_AFE | SEL_FLOPPED_HSTX; if (pipe) { pipeconf_reg = PIPECCONF; dspcntr_reg = DSPCCNTR; } else { if (mdfld_get_panel_type(dev, pipe) == TC35876X) mipi &= (~0x03); /* Use all four lanes */ else mipi |= 2; } /*start up display island if it was shutdown*/ if (!gma_power_begin(dev, true)) return; if (mdfld_get_panel_type(dev, pipe) == TC35876X) { /* * The following logic is required to reset the bridge and * configure. This also starts the DSI clock at 200MHz. */ tc35876x_set_bridge_reset_state(dev, 0); /*Pull High Reset */ tc35876x_toshiba_bridge_panel_on(dev); udelay(100); /* Now start the DSI clock */ REG_WRITE(MRST_DPLL_A, 0x00); REG_WRITE(MRST_FPA0, 0xC1); REG_WRITE(MRST_DPLL_A, 0x00800000); udelay(500); REG_WRITE(MRST_DPLL_A, 0x80800000); if (REG_BIT_WAIT(pipeconf_reg, 1, 29)) dev_err(&dev->pdev->dev, "%s: DSI PLL lock timeout\n", __func__); REG_WRITE(MIPI_DPHY_PARAM_REG(pipe), 0x2A0c6008); mipi_set_properties(dsi_config, pipe); mdfld_mipi_config(dsi_config, pipe); mdfld_set_pipe_timing(dsi_config, pipe); REG_WRITE(DSPABASE, 0x00); REG_WRITE(DSPASTRIDE, (mode->hdisplay * 4)); REG_WRITE(DSPASIZE, ((mode->vdisplay - 1) << 16) | (mode->hdisplay - 1)); REG_WRITE(DSPACNTR, 0x98000000); REG_WRITE(DSPASURF, 0x00); REG_WRITE(VGACNTRL, 0x80000000); REG_WRITE(DEVICE_READY_REG, 0x00000001); REG_WRITE(MIPI_PORT_CONTROL(pipe), 0x80810000); } else { /*set up mipi port FIXME: do at init time */ REG_WRITE(MIPI_PORT_CONTROL(pipe), mipi); } REG_READ(MIPI_PORT_CONTROL(pipe)); if (mdfld_get_panel_type(dev, pipe) == TMD_VID) { /* NOP */ } else if (mdfld_get_panel_type(dev, pipe) == TC35876X) { /* set up DSI controller DPI interface */ mdfld_dsi_dpi_controller_init(dsi_config, pipe); /* Configure MIPI Bridge and Panel */ tc35876x_configure_lvds_bridge(dev); dev_priv->dpi_panel_on[pipe] = true; } else { /*turn on DPI interface*/ mdfld_dsi_dpi_turn_on(dpi_output, pipe); } /*set up pipe*/ REG_WRITE(pipeconf_reg, pipeconf); REG_READ(pipeconf_reg); /*set up display plane*/ REG_WRITE(dspcntr_reg, dspcntr); REG_READ(dspcntr_reg); msleep(20); /* FIXME: this should wait for vblank */ if (mdfld_get_panel_type(dev, pipe) == TMD_VID) { /* NOP */ } else if (mdfld_get_panel_type(dev, pipe) == TC35876X) { mdfld_dsi_dpi_turn_on(dpi_output, pipe); } else { /* init driver ic */ mdfld_dsi_tpo_ic_init(dsi_config, pipe); /*init backlight*/ mdfld_dsi_brightness_init(dsi_config, pipe); } gma_power_end(dev); }
/* But removed in DV0 and later. So need to add here. */ static void mipi_set_properties(struct mdfld_dsi_config *dsi_config, int pipe) { struct drm_device *dev = dsi_config->dev; REG_WRITE(MIPI_CTRL_REG(pipe), 0x00000018); REG_WRITE(MIPI_INTR_EN_REG(pipe), 0xffffffff); REG_WRITE(MIPI_HS_TX_TIMEOUT_REG(pipe), 0xffffff); REG_WRITE(MIPI_LP_RX_TIMEOUT_REG(pipe), 0xffffff); REG_WRITE(MIPI_TURN_AROUND_TIMEOUT_REG(pipe), 0x14); REG_WRITE(MIPI_DEVICE_RESET_TIMER_REG(pipe), 0xff); REG_WRITE(MIPI_HIGH_LOW_SWITCH_COUNT_REG(pipe), 0x25); REG_WRITE(MIPI_INIT_COUNT_REG(pipe), 0xf0); REG_WRITE(MIPI_EOT_DISABLE_REG(pipe), 0x00000000); REG_WRITE(MIPI_LP_BYTECLK_REG(pipe), 0x00000004); REG_WRITE(MIPI_DBI_BW_CTRL_REG(pipe), 0x00000820); REG_WRITE(MIPI_CLK_LANE_SWITCH_TIME_CNT_REG(pipe), (0xa << 16) | 0x14); }
void mdfld_dsi_dpi_controller_init(struct mdfld_dsi_config *dsi_config, int pipe) { struct drm_device *dev = dsi_config->dev; int lane_count = dsi_config->lane_count; struct mdfld_dsi_dpi_timing dpi_timing; struct drm_display_mode *mode = dsi_config->mode; u32 val; /*un-ready device*/ REG_FLD_MOD(MIPI_DEVICE_READY_REG(pipe), 0, 0, 0); /*init dsi adapter before kicking off*/ REG_WRITE(MIPI_CTRL_REG(pipe), 0x00000018); /*enable all interrupts*/ REG_WRITE(MIPI_INTR_EN_REG(pipe), 0xffffffff); /*set up func_prg*/ val = lane_count; val |= dsi_config->channel_num << DSI_DPI_VIRT_CHANNEL_OFFSET; switch (dsi_config->bpp) { case 16: val |= DSI_DPI_COLOR_FORMAT_RGB565; break; case 18: val |= DSI_DPI_COLOR_FORMAT_RGB666; break; case 24: val |= DSI_DPI_COLOR_FORMAT_RGB888; break; default: DRM_ERROR("unsupported color format, bpp = %d\n", dsi_config->bpp); } REG_WRITE(MIPI_DSI_FUNC_PRG_REG(pipe), val); REG_WRITE(MIPI_HS_TX_TIMEOUT_REG(pipe), (mode->vtotal * mode->htotal * dsi_config->bpp / (8 * lane_count)) & DSI_HS_TX_TIMEOUT_MASK); REG_WRITE(MIPI_LP_RX_TIMEOUT_REG(pipe), 0xffff & DSI_LP_RX_TIMEOUT_MASK); /*max value: 20 clock cycles of txclkesc*/ REG_WRITE(MIPI_TURN_AROUND_TIMEOUT_REG(pipe), 0x14 & DSI_TURN_AROUND_TIMEOUT_MASK); /*min 21 txclkesc, max: ffffh*/ REG_WRITE(MIPI_DEVICE_RESET_TIMER_REG(pipe), 0xffff & DSI_RESET_TIMER_MASK); REG_WRITE(MIPI_DPI_RESOLUTION_REG(pipe), mode->vdisplay << 16 | mode->hdisplay); /*set DPI timing registers*/ mdfld_dsi_dpi_timing_calculation(mode, &dpi_timing, dsi_config->lane_count, dsi_config->bpp); REG_WRITE(MIPI_HSYNC_COUNT_REG(pipe), dpi_timing.hsync_count & DSI_DPI_TIMING_MASK); REG_WRITE(MIPI_HBP_COUNT_REG(pipe), dpi_timing.hbp_count & DSI_DPI_TIMING_MASK); REG_WRITE(MIPI_HFP_COUNT_REG(pipe), dpi_timing.hfp_count & DSI_DPI_TIMING_MASK); REG_WRITE(MIPI_HACTIVE_COUNT_REG(pipe), dpi_timing.hactive_count & DSI_DPI_TIMING_MASK); REG_WRITE(MIPI_VSYNC_COUNT_REG(pipe), dpi_timing.vsync_count & DSI_DPI_TIMING_MASK); REG_WRITE(MIPI_VBP_COUNT_REG(pipe), dpi_timing.vbp_count & DSI_DPI_TIMING_MASK); REG_WRITE(MIPI_VFP_COUNT_REG(pipe), dpi_timing.vfp_count & DSI_DPI_TIMING_MASK); REG_WRITE(MIPI_HIGH_LOW_SWITCH_COUNT_REG(pipe), 0x46); /*min: 7d0 max: 4e20*/ REG_WRITE(MIPI_INIT_COUNT_REG(pipe), 0x000007d0); /*set up video mode*/ val = dsi_config->video_mode | DSI_DPI_COMPLETE_LAST_LINE; REG_WRITE(MIPI_VIDEO_MODE_FORMAT_REG(pipe), val); REG_WRITE(MIPI_EOT_DISABLE_REG(pipe), 0x00000000); REG_WRITE(MIPI_LP_BYTECLK_REG(pipe), 0x00000004); /*TODO: figure out how to setup these registers*/ if (mdfld_get_panel_type(dev, pipe) == TC35876X) REG_WRITE(MIPI_DPHY_PARAM_REG(pipe), 0x2A0c6008); else REG_WRITE(MIPI_DPHY_PARAM_REG(pipe), 0x150c3408); REG_WRITE(MIPI_CLK_LANE_SWITCH_TIME_CNT_REG(pipe), (0xa << 16) | 0x14); if (mdfld_get_panel_type(dev, pipe) == TC35876X) tc35876x_set_bridge_reset_state(dev, 0); /*Pull High Reset */ /*set device ready*/ REG_FLD_MOD(MIPI_DEVICE_READY_REG(pipe), 1, 0, 0); }
/* Unlike most Intel display engines, on Cedarview the DPLL registers * are behind this sideband bus. They must be programmed while the * DPLL reference clock is on in the DPLL control register, but before * the DPLL is enabled in the DPLL control register. */ int psb_dpll_set_clock_cdv(struct drm_device *dev, struct drm_crtc *crtc, struct psb_intel_clock_t *clock, bool is_lvds, u32 ddi_select) { struct psb_intel_crtc *psb_crtc = to_psb_intel_crtc(crtc); int pipe = psb_crtc->pipe; u32 m, n_vco, p; int ret = 0; int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B; int ref_sfr = (pipe == 0) ? SB_REF_DPLLA : SB_REF_DPLLB; u32 ref_value; u32 lane_reg, lane_value; psb_print_clock(clock); psb_sb_reset(dev); REG_WRITE(dpll_reg, DPLL_SYNCLOCK_ENABLE | DPLL_VGA_MODE_DIS); udelay(100); /* Follow the BIOS and write the REF/SFR Register. Hardcoded value */ psb_sb_read(dev, SB_REF_SFR(pipe), &ref_value); ref_value = 0x68A701; psb_sb_write(dev, SB_REF_SFR(pipe), ref_value); /* We don't know what the other fields of these regs are, so * leave them in place. */ /* * The BIT 14:13 of 0x8010/0x8030 is used to select the ref clk * for the pipe A/B. Display spec 1.06 has wrong definition. * Correct definition is like below: * * refclka mean use clock from same PLL * * if DPLLA sets 01 and DPLLB sets 01, they use clock from their pll * * if DPLLA sets 01 and DPLLB sets 02, both use clk from DPLLA * */ ret = psb_sb_read(dev, ref_sfr, &ref_value); if (ret) return ret; ref_value &= ~(REF_CLK_MASK); /* use DPLL_A for pipeB on CRT/HDMI */ if (pipe == 1 && !is_lvds && !(ddi_select & DP_MASK)) { DRM_DEBUG_KMS("use DPLLA for pipe B\n"); ref_value |= REF_CLK_DPLLA; } else { DRM_DEBUG_KMS("use their DPLL for pipe A/B\n"); ref_value |= REF_CLK_DPLL; } ret = psb_sb_write(dev, ref_sfr, ref_value); if (ret) return ret; ret = psb_sb_read(dev, SB_M(pipe), &m); if (ret) return ret; m &= ~SB_M_DIVIDER_MASK; m |= ((clock->m2) << SB_M_DIVIDER_SHIFT); ret = psb_sb_write(dev, SB_M(pipe), m); if (ret) return ret; ret = psb_sb_read(dev, SB_N_VCO(pipe), &n_vco); if (ret) return ret; /* Follow the BIOS to program the N_DIVIDER REG */ n_vco &= 0xFFFF; n_vco |= 0x107; n_vco &= ~(SB_N_VCO_SEL_MASK | SB_N_DIVIDER_MASK | SB_N_CB_TUNE_MASK); n_vco |= ((clock->n) << SB_N_DIVIDER_SHIFT); if (clock->vco < 2250000) { n_vco |= (2 << SB_N_CB_TUNE_SHIFT); n_vco |= (0 << SB_N_VCO_SEL_SHIFT); } else if (clock->vco < 2750000) { n_vco |= (1 << SB_N_CB_TUNE_SHIFT); n_vco |= (1 << SB_N_VCO_SEL_SHIFT); } else if (clock->vco < 3300000) { n_vco |= (0 << SB_N_CB_TUNE_SHIFT); n_vco |= (2 << SB_N_VCO_SEL_SHIFT); } else { n_vco |= (0 << SB_N_CB_TUNE_SHIFT); n_vco |= (3 << SB_N_VCO_SEL_SHIFT); } ret = psb_sb_write(dev, SB_N_VCO(pipe), n_vco); if (ret) return ret; ret = psb_sb_read(dev, SB_P(pipe), &p); if (ret) return ret; p &= ~(SB_P2_DIVIDER_MASK | SB_P1_DIVIDER_MASK); p |= SET_FIELD(clock->p1, SB_P1_DIVIDER); switch (clock->p2) { case 5: p |= SET_FIELD(SB_P2_5, SB_P2_DIVIDER); break; case 10: p |= SET_FIELD(SB_P2_10, SB_P2_DIVIDER); break; case 14: p |= SET_FIELD(SB_P2_14, SB_P2_DIVIDER); break; case 7: p |= SET_FIELD(SB_P2_7, SB_P2_DIVIDER); break; default: DRM_ERROR("Bad P2 clock: %d\n", clock->p2); return -EINVAL; } ret = psb_sb_write(dev, SB_P(pipe), p); if (ret) return ret; /* Issue Title: * DP/HDMI lanes were dead during cold temperature. * * Reason for this failure: * Reference Clk required to power these lanes were not sufficient enough * and hence in cold temperature the lanes were failing. Now EV team came * up with a work around which utilizes a different alt ref path and to * disable Op Amp (which was previously generating reference clk) and * enable Alt_Ref Path. */ ref_value = 0x14100300; ret = psb_sb_write(dev, SB_ALT_REF(pipe), ref_value); if (ret) return ret; ref_value = 0x1FFB0010; ret = psb_sb_write(dev, SB_MISC_DFX(pipe), ref_value); if (ret) return ret; ref_value = 0x10100300; ret = psb_sb_write(dev, SB_ALT_REF(pipe), ref_value); if (ret) return ret; if (ddi_select) { if ((ddi_select & DDI_MASK) == DDI0_SELECT) { lane_reg = PSB_LANE0; psb_sb_read(dev, lane_reg, &lane_value); lane_value &= ~(LANE_PLL_MASK); lane_value |= LANE_PLL_ENABLE | LANE_PLL_PIPE(pipe); psb_sb_write(dev, lane_reg, lane_value); lane_reg = PSB_LANE1; psb_sb_read(dev, lane_reg, &lane_value); lane_value &= ~(LANE_PLL_MASK); lane_value |= LANE_PLL_ENABLE | LANE_PLL_PIPE(pipe); psb_sb_write(dev, lane_reg, lane_value); } else { lane_reg = PSB_LANE2; psb_sb_read(dev, lane_reg, &lane_value); lane_value &= ~(LANE_PLL_MASK); lane_value |= LANE_PLL_ENABLE | LANE_PLL_PIPE(pipe); psb_sb_write(dev, lane_reg, lane_value); lane_reg = PSB_LANE3; psb_sb_read(dev, lane_reg, &lane_value); lane_value &= ~(LANE_PLL_MASK); lane_value |= LANE_PLL_ENABLE | LANE_PLL_PIPE(pipe); psb_sb_write(dev, lane_reg, lane_value); } } return 0; }
/** * ar9002_hw_set_channel - set channel on single-chip device * @ah: atheros hardware structure * @chan: * * This is the function to change channel on single-chip devices, that is * all devices after ar9280. * * This function takes the channel value in MHz and sets * hardware channel value. Assumes writes have been enabled to analog bus. * * Actual Expression, * * For 2GHz channel, * Channel Frequency = (3/4) * freq_ref * (chansel[8:0] + chanfrac[16:0]/2^17) * (freq_ref = 40MHz) * * For 5GHz channel, * Channel Frequency = (3/2) * freq_ref * (chansel[8:0] + chanfrac[16:0]/2^10) * (freq_ref = 40MHz/(24>>amodeRefSel)) */ static int ar9002_hw_set_channel(struct ath_hw *ah, struct ath9k_channel *chan) { u16 bMode, fracMode, aModeRefSel = 0; u32 freq, ndiv, channelSel = 0, channelFrac = 0, reg32 = 0; struct chan_centers centers; u32 refDivA = 24; ath9k_hw_get_channel_centers(ah, chan, ¢ers); freq = centers.synth_center; reg32 = REG_READ(ah, AR_PHY_SYNTH_CONTROL); reg32 &= 0xc0000000; if (freq < 4800) { /* 2 GHz, fractional mode */ u32 txctl; int regWrites = 0; bMode = 1; fracMode = 1; aModeRefSel = 0; channelSel = CHANSEL_2G(freq); if (AR_SREV_9287_11_OR_LATER(ah)) { if (freq == 2484) { /* Enable channel spreading for channel 14 */ REG_WRITE_ARRAY(&ah->iniCckfirJapan2484, 1, regWrites); } else { REG_WRITE_ARRAY(&ah->iniCckfirNormal, 1, regWrites); } } else { txctl = REG_READ(ah, AR_PHY_CCK_TX_CTRL); if (freq == 2484) { /* Enable channel spreading for channel 14 */ REG_WRITE(ah, AR_PHY_CCK_TX_CTRL, txctl | AR_PHY_CCK_TX_CTRL_JAPAN); } else { REG_WRITE(ah, AR_PHY_CCK_TX_CTRL, txctl & ~AR_PHY_CCK_TX_CTRL_JAPAN); } } } else { bMode = 0; fracMode = 0; switch (ah->eep_ops->get_eeprom(ah, EEP_FRAC_N_5G)) { case 0: if ((freq % 20) == 0) aModeRefSel = 3; else if ((freq % 10) == 0) aModeRefSel = 2; if (aModeRefSel) break; case 1: default: aModeRefSel = 0; /* * Enable 2G (fractional) mode for channels * which are 5MHz spaced. */ fracMode = 1; refDivA = 1; channelSel = CHANSEL_5G(freq); /* RefDivA setting */ REG_RMW_FIELD(ah, AR_AN_SYNTH9, AR_AN_SYNTH9_REFDIVA, refDivA); } if (!fracMode) { ndiv = (freq * (refDivA >> aModeRefSel)) / 60; channelSel = ndiv & 0x1ff; channelFrac = (ndiv & 0xfffffe00) * 2; channelSel = (channelSel << 17) | channelFrac; } }
static void mdfld_dsi_dbi_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode, struct drm_display_mode *adjusted_mode) { int ret = 0; struct drm_device *dev = encoder->dev; struct drm_psb_private *dev_priv = dev->dev_private; struct mdfld_dsi_encoder *dsi_encoder = MDFLD_DSI_ENCODER(encoder); struct mdfld_dsi_dbi_output *dsi_output = MDFLD_DSI_DBI_OUTPUT(dsi_encoder); struct mdfld_dsi_config *dsi_config = mdfld_dsi_encoder_get_config(dsi_encoder); struct mdfld_dsi_connector *dsi_connector = dsi_config->connector; int pipe = dsi_connector->pipe; u8 param = 0; /* Regs */ u32 mipi_reg = MIPI; u32 dspcntr_reg = DSPACNTR; u32 pipeconf_reg = PIPEACONF; u32 reg_offset = 0; /* Values */ u32 dspcntr_val = dev_priv->dspcntr; u32 pipeconf_val = dev_priv->pipeconf; u32 h_active_area = mode->hdisplay; u32 v_active_area = mode->vdisplay; u32 mipi_val; mipi_val = (PASS_FROM_SPHY_TO_AFE | SEL_FLOPPED_HSTX | TE_TRIGGER_GPIO_PIN); dev_dbg(dev->dev, "mipi_val =0x%x\n", mipi_val); dev_dbg(dev->dev, "type %s\n", (pipe == 2) ? "MIPI2" : "MIPI"); dev_dbg(dev->dev, "h %d v %d\n", mode->hdisplay, mode->vdisplay); if (pipe == 2) { mipi_reg = MIPI_C; dspcntr_reg = DSPCCNTR; pipeconf_reg = PIPECCONF; reg_offset = MIPIC_REG_OFFSET; dspcntr_val = dev_priv->dspcntr2; pipeconf_val = dev_priv->pipeconf2; } else { mipi_val |= 0x2; /*two lanes for port A and C respectively*/ } if (!gma_power_begin(dev, true)) { dev_err(dev->dev, "hw begin failed\n"); return; } REG_WRITE(dspcntr_reg, dspcntr_val); REG_READ(dspcntr_reg); /* 20ms delay before sending exit_sleep_mode */ msleep(20); /* Send exit_sleep_mode DCS */ ret = mdfld_dsi_dbi_send_dcs(dsi_output, DCS_EXIT_SLEEP_MODE, NULL, 0, CMD_DATA_SRC_SYSTEM_MEM); if (ret) { dev_err(dev->dev, "sent exit_sleep_mode faild\n"); goto out_err; } /* Send set_tear_on DCS */ ret = mdfld_dsi_dbi_send_dcs(dsi_output, DCS_SET_TEAR_ON, ¶m, 1, CMD_DATA_SRC_SYSTEM_MEM); if (ret) { dev_err(dev->dev, "%s - sent set_tear_on faild\n", __func__); goto out_err; } /* Do some init stuff */ REG_WRITE(pipeconf_reg, pipeconf_val | PIPEACONF_DSR); REG_READ(pipeconf_reg); /* TODO: this looks ugly, try to move it to CRTC mode setting*/ if (pipe == 2) dev_priv->pipeconf2 |= PIPEACONF_DSR; else dev_priv->pipeconf |= PIPEACONF_DSR; dev_dbg(dev->dev, "pipeconf %x\n", REG_READ(pipeconf_reg)); ret = mdfld_dsi_dbi_update_area(dsi_output, 0, 0, h_active_area - 1, v_active_area - 1); if (ret) { dev_err(dev->dev, "update area failed\n"); goto out_err; } out_err: gma_power_end(dev); if (ret) dev_err(dev->dev, "mode set failed\n"); }
void ath9k_ani_reset(struct ath_hal *ah) { struct ath_hal_5416 *ahp = AH5416(ah); struct ar5416AniState *aniState; struct ath9k_channel *chan = ah->ah_curchan; int index; if (!DO_ANI(ah)) return; index = ath9k_hw_get_ani_channel_idx(ah, chan); aniState = &ahp->ah_ani[index]; ahp->ah_curani = aniState; if (DO_ANI(ah) && ah->ah_opmode != NL80211_IFTYPE_STATION && ah->ah_opmode != NL80211_IFTYPE_ADHOC) { DPRINTF(ah->ah_sc, ATH_DBG_ANI, "Reset ANI state opmode %u\n", ah->ah_opmode); ahp->ah_stats.ast_ani_reset++; ath9k_hw_ani_control(ah, ATH9K_ANI_NOISE_IMMUNITY_LEVEL, 0); ath9k_hw_ani_control(ah, ATH9K_ANI_SPUR_IMMUNITY_LEVEL, 0); ath9k_hw_ani_control(ah, ATH9K_ANI_FIRSTEP_LEVEL, 0); ath9k_hw_ani_control(ah, ATH9K_ANI_OFDM_WEAK_SIGNAL_DETECTION, !ATH9K_ANI_USE_OFDM_WEAK_SIG); ath9k_hw_ani_control(ah, ATH9K_ANI_CCK_WEAK_SIGNAL_THR, ATH9K_ANI_CCK_WEAK_SIG_THR); ath9k_hw_setrxfilter(ah, ath9k_hw_getrxfilter(ah) | ATH9K_RX_FILTER_PHYERR); if (ah->ah_opmode == NL80211_IFTYPE_AP) { ahp->ah_curani->ofdmTrigHigh = ah->ah_config.ofdm_trig_high; ahp->ah_curani->ofdmTrigLow = ah->ah_config.ofdm_trig_low; ahp->ah_curani->cckTrigHigh = ah->ah_config.cck_trig_high; ahp->ah_curani->cckTrigLow = ah->ah_config.cck_trig_low; } ath9k_ani_restart(ah); return; } if (aniState->noiseImmunityLevel != 0) ath9k_hw_ani_control(ah, ATH9K_ANI_NOISE_IMMUNITY_LEVEL, aniState->noiseImmunityLevel); if (aniState->spurImmunityLevel != 0) ath9k_hw_ani_control(ah, ATH9K_ANI_SPUR_IMMUNITY_LEVEL, aniState->spurImmunityLevel); if (aniState->ofdmWeakSigDetectOff) ath9k_hw_ani_control(ah, ATH9K_ANI_OFDM_WEAK_SIGNAL_DETECTION, !aniState->ofdmWeakSigDetectOff); if (aniState->cckWeakSigThreshold) ath9k_hw_ani_control(ah, ATH9K_ANI_CCK_WEAK_SIGNAL_THR, aniState->cckWeakSigThreshold); if (aniState->firstepLevel != 0) ath9k_hw_ani_control(ah, ATH9K_ANI_FIRSTEP_LEVEL, aniState->firstepLevel); if (ahp->ah_hasHwPhyCounters) { ath9k_hw_setrxfilter(ah, ath9k_hw_getrxfilter(ah) & ~ATH9K_RX_FILTER_PHYERR); ath9k_ani_restart(ah); REG_WRITE(ah, AR_PHY_ERR_MASK_1, AR_PHY_ERR_OFDM_TIMING); REG_WRITE(ah, AR_PHY_ERR_MASK_2, AR_PHY_ERR_CCK_TIMING); } else { ath9k_ani_restart(ah); ath9k_hw_setrxfilter(ah, ath9k_hw_getrxfilter(ah) | ATH9K_RX_FILTER_PHYERR); } }
/* * Restore the ANI parameters in the HAL and reset the statistics. * This routine should be called for every hardware reset and for * every channel change. */ void ath9k_ani_reset(struct ath_hw *ah, bool is_scanning) { struct ar5416AniState *aniState = &ah->curchan->ani; struct ath9k_channel *chan = ah->curchan; struct ath_common *common = ath9k_hw_common(ah); if (!DO_ANI(ah)) return; if (!use_new_ani(ah)) return ath9k_ani_reset_old(ah, is_scanning); BUG_ON(aniState == NULL); ah->stats.ast_ani_reset++; /* only allow a subset of functions in AP mode */ if (ah->opmode == NL80211_IFTYPE_AP) { if (IS_CHAN_2GHZ(chan)) { ah->ani_function = (ATH9K_ANI_SPUR_IMMUNITY_LEVEL | ATH9K_ANI_FIRSTEP_LEVEL); if (AR_SREV_9300_20_OR_LATER(ah)) ah->ani_function |= ATH9K_ANI_MRC_CCK; } else ah->ani_function = 0; } /* always allow mode (on/off) to be controlled */ ah->ani_function |= ATH9K_ANI_MODE; if (is_scanning || (ah->opmode != NL80211_IFTYPE_STATION && ah->opmode != NL80211_IFTYPE_ADHOC)) { /* * If we're scanning or in AP mode, the defaults (ini) * should be in place. For an AP we assume the historical * levels for this channel are probably outdated so start * from defaults instead. */ if (aniState->ofdmNoiseImmunityLevel != ATH9K_ANI_OFDM_DEF_LEVEL || aniState->cckNoiseImmunityLevel != ATH9K_ANI_CCK_DEF_LEVEL) { ath_dbg(common, ANI, "Restore defaults: opmode %u chan %d Mhz/0x%x is_scanning=%d ofdm:%d cck:%d\n", ah->opmode, chan->channel, chan->channelFlags, is_scanning, aniState->ofdmNoiseImmunityLevel, aniState->cckNoiseImmunityLevel); aniState->update_ani = false; ath9k_hw_set_ofdm_nil(ah, ATH9K_ANI_OFDM_DEF_LEVEL); ath9k_hw_set_cck_nil(ah, ATH9K_ANI_CCK_DEF_LEVEL); } } else { /* * restore historical levels for this channel */ ath_dbg(common, ANI, "Restore history: opmode %u chan %d Mhz/0x%x is_scanning=%d ofdm:%d cck:%d\n", ah->opmode, chan->channel, chan->channelFlags, is_scanning, aniState->ofdmNoiseImmunityLevel, aniState->cckNoiseImmunityLevel); aniState->update_ani = true; ath9k_hw_set_ofdm_nil(ah, aniState->ofdmNoiseImmunityLevel); ath9k_hw_set_cck_nil(ah, aniState->cckNoiseImmunityLevel); } /* * enable phy counters if hw supports or if not, enable phy * interrupts (so we can count each one) */ ath9k_ani_restart(ah); ENABLE_REGWRITE_BUFFER(ah); REG_WRITE(ah, AR_PHY_ERR_MASK_1, AR_PHY_ERR_OFDM_TIMING); REG_WRITE(ah, AR_PHY_ERR_MASK_2, AR_PHY_ERR_CCK_TIMING); REGWRITE_BUFFER_FLUSH(ah); }
void ath9k_hw_ani_monitor(struct ath_hal *ah, const struct ath9k_node_stats *stats, struct ath9k_channel *chan) { struct ath_hal_5416 *ahp = AH5416(ah); struct ar5416AniState *aniState; int32_t listenTime; aniState = ahp->ah_curani; ahp->ah_stats.ast_nodestats = *stats; listenTime = ath9k_hw_ani_get_listen_time(ah); if (listenTime < 0) { ahp->ah_stats.ast_ani_lneg++; ath9k_ani_restart(ah); return; } aniState->listenTime += listenTime; if (ahp->ah_hasHwPhyCounters) { u32 phyCnt1, phyCnt2; u32 ofdmPhyErrCnt, cckPhyErrCnt; ath9k_hw_update_mibstats(ah, &ahp->ah_mibStats); phyCnt1 = REG_READ(ah, AR_PHY_ERR_1); phyCnt2 = REG_READ(ah, AR_PHY_ERR_2); if (phyCnt1 < aniState->ofdmPhyErrBase || phyCnt2 < aniState->cckPhyErrBase) { if (phyCnt1 < aniState->ofdmPhyErrBase) { DPRINTF(ah->ah_sc, ATH_DBG_ANI, "phyCnt1 0x%x, resetting " "counter value to 0x%x\n", phyCnt1, aniState->ofdmPhyErrBase); REG_WRITE(ah, AR_PHY_ERR_1, aniState->ofdmPhyErrBase); REG_WRITE(ah, AR_PHY_ERR_MASK_1, AR_PHY_ERR_OFDM_TIMING); } if (phyCnt2 < aniState->cckPhyErrBase) { DPRINTF(ah->ah_sc, ATH_DBG_ANI, "phyCnt2 0x%x, resetting " "counter value to 0x%x\n", phyCnt2, aniState->cckPhyErrBase); REG_WRITE(ah, AR_PHY_ERR_2, aniState->cckPhyErrBase); REG_WRITE(ah, AR_PHY_ERR_MASK_2, AR_PHY_ERR_CCK_TIMING); } return; } ofdmPhyErrCnt = phyCnt1 - aniState->ofdmPhyErrBase; ahp->ah_stats.ast_ani_ofdmerrs += ofdmPhyErrCnt - aniState->ofdmPhyErrCount; aniState->ofdmPhyErrCount = ofdmPhyErrCnt; cckPhyErrCnt = phyCnt2 - aniState->cckPhyErrBase; ahp->ah_stats.ast_ani_cckerrs += cckPhyErrCnt - aniState->cckPhyErrCount; aniState->cckPhyErrCount = cckPhyErrCnt; } if (!DO_ANI(ah)) return; if (aniState->listenTime > 5 * ahp->ah_aniPeriod) { if (aniState->ofdmPhyErrCount <= aniState->listenTime * aniState->ofdmTrigLow / 1000 && aniState->cckPhyErrCount <= aniState->listenTime * aniState->cckTrigLow / 1000) ath9k_hw_ani_lower_immunity(ah); ath9k_ani_restart(ah); } else if (aniState->listenTime > ahp->ah_aniPeriod) { if (aniState->ofdmPhyErrCount > aniState->listenTime * aniState->ofdmTrigHigh / 1000) { ath9k_hw_ani_ofdm_err_trigger(ah); ath9k_ani_restart(ah); } else if (aniState->cckPhyErrCount > aniState->listenTime * aniState->cckTrigHigh / 1000) { ath9k_hw_ani_cck_err_trigger(ah); ath9k_ani_restart(ah); } } }
/** * cdv_restore_display_registers - restore lost register state * @dev: our DRM device * * Restore register state that was lost during suspend and resume. * * FIXME: review */ static int cdv_restore_display_registers(struct drm_device *dev) { struct drm_psb_private *dev_priv = dev->dev_private; struct psb_save_area *regs = &dev_priv->regs; struct drm_connector *connector; u32 temp; pci_write_config_byte(dev->pdev, 0xF4, regs->cdv.saveLBB); REG_WRITE(DSPCLK_GATE_D, regs->cdv.saveDSPCLK_GATE_D); REG_WRITE(RAMCLK_GATE_D, regs->cdv.saveRAMCLK_GATE_D); /* BIOS does below anyway */ REG_WRITE(DPIO_CFG, 0); REG_WRITE(DPIO_CFG, DPIO_MODE_SELECT_0 | DPIO_CMN_RESET_N); temp = REG_READ(DPLL_A); if ((temp & DPLL_SYNCLOCK_ENABLE) == 0) { REG_WRITE(DPLL_A, temp | DPLL_SYNCLOCK_ENABLE); REG_READ(DPLL_A); } temp = REG_READ(DPLL_B); if ((temp & DPLL_SYNCLOCK_ENABLE) == 0) { REG_WRITE(DPLL_B, temp | DPLL_SYNCLOCK_ENABLE); REG_READ(DPLL_B); } udelay(500); REG_WRITE(DSPFW1, regs->cdv.saveDSPFW[0]); REG_WRITE(DSPFW2, regs->cdv.saveDSPFW[1]); REG_WRITE(DSPFW3, regs->cdv.saveDSPFW[2]); REG_WRITE(DSPFW4, regs->cdv.saveDSPFW[3]); REG_WRITE(DSPFW5, regs->cdv.saveDSPFW[4]); REG_WRITE(DSPFW6, regs->cdv.saveDSPFW[5]); REG_WRITE(DSPARB, regs->cdv.saveDSPARB); REG_WRITE(ADPA, regs->cdv.saveADPA); REG_WRITE(BLC_PWM_CTL2, regs->saveBLC_PWM_CTL2); REG_WRITE(LVDS, regs->cdv.saveLVDS); REG_WRITE(PFIT_CONTROL, regs->cdv.savePFIT_CONTROL); REG_WRITE(PFIT_PGM_RATIOS, regs->cdv.savePFIT_PGM_RATIOS); REG_WRITE(BLC_PWM_CTL, regs->saveBLC_PWM_CTL); REG_WRITE(PP_ON_DELAYS, regs->cdv.savePP_ON_DELAYS); REG_WRITE(PP_OFF_DELAYS, regs->cdv.savePP_OFF_DELAYS); REG_WRITE(PP_CYCLE, regs->cdv.savePP_CYCLE); REG_WRITE(PP_CONTROL, regs->cdv.savePP_CONTROL); REG_WRITE(VGACNTRL, regs->cdv.saveVGACNTRL); REG_WRITE(PSB_INT_ENABLE_R, regs->cdv.saveIER); REG_WRITE(PSB_INT_MASK_R, regs->cdv.saveIMR); /* Fix arbitration bug */ cdv_errata(dev); drm_mode_config_reset(dev); list_for_each_entry(connector, &dev->mode_config.connector_list, head) connector->funcs->dpms(connector, DRM_MODE_DPMS_ON); /* Resume the modeset for every activated CRTC */ drm_helper_resume_force_mode(dev); return 0; }
void ar9003_hw_rtt_disable(struct ath_hw *ah) { REG_WRITE(ah, AR_PHY_RTT_CTRL, 0); }
bool ath9k_hw_ar9280_set_channel(struct ath_hw *ah, struct ath9k_channel *chan) { u16 bMode, fracMode, aModeRefSel = 0; u32 freq, ndiv, channelSel = 0, channelFrac = 0, reg32 = 0; struct chan_centers centers; u32 refDivA = 24; ath9k_hw_get_channel_centers(ah, chan, ¢ers); freq = centers.synth_center; reg32 = REG_READ(ah, AR_PHY_SYNTH_CONTROL); reg32 &= 0xc0000000; if (freq < 4800) { u32 txctl; bMode = 1; fracMode = 1; aModeRefSel = 0; channelSel = (freq * 0x10000) / 15; txctl = REG_READ(ah, AR_PHY_CCK_TX_CTRL); if (freq == 2484) { REG_WRITE(ah, AR_PHY_CCK_TX_CTRL, txctl | AR_PHY_CCK_TX_CTRL_JAPAN); } else { REG_WRITE(ah, AR_PHY_CCK_TX_CTRL, txctl & ~AR_PHY_CCK_TX_CTRL_JAPAN); } } else { bMode = 0; fracMode = 0; switch(ah->eep_ops->get_eeprom(ah, EEP_FRAC_N_5G)) { case 0: if ((freq % 20) == 0) { aModeRefSel = 3; } else if ((freq % 10) == 0) { aModeRefSel = 2; } if (aModeRefSel) break; case 1: default: aModeRefSel = 0; fracMode = 1; refDivA = 1; channelSel = (freq * 0x8000) / 15; REG_RMW_FIELD(ah, AR_AN_SYNTH9, AR_AN_SYNTH9_REFDIVA, refDivA); } if (!fracMode) { ndiv = (freq * (refDivA >> aModeRefSel)) / 60; channelSel = ndiv & 0x1ff; channelFrac = (ndiv & 0xfffffe00) * 2; channelSel = (channelSel << 17) | channelFrac; } }
static void mdfld_h8c7_dpi_controller_init(struct mdfld_dsi_config *dsi_config, int pipe, int update) { struct mdfld_dsi_hw_context *hw_ctx = &dsi_config->dsi_hw_context; struct drm_device *dev = dsi_config->dev; int lane_count = dsi_config->lane_count; u32 mipi_control_reg = dsi_config->regs.mipi_control_reg; u32 intr_en_reg = dsi_config->regs.intr_en_reg; u32 hs_tx_timeout_reg = dsi_config->regs.hs_tx_timeout_reg; u32 lp_rx_timeout_reg = dsi_config->regs.lp_rx_timeout_reg; u32 turn_around_timeout_reg = dsi_config->regs.turn_around_timeout_reg; u32 device_reset_timer_reg = dsi_config->regs.device_reset_timer_reg; u32 high_low_switch_count_reg = dsi_config->regs.high_low_switch_count_reg; u32 init_count_reg = dsi_config->regs.init_count_reg; u32 eot_disable_reg = dsi_config->regs.eot_disable_reg; u32 lp_byteclk_reg = dsi_config->regs.lp_byteclk_reg; u32 clk_lane_switch_time_cnt_reg = dsi_config->regs.clk_lane_switch_time_cnt_reg; u32 video_mode_format_reg = dsi_config->regs.video_mode_format_reg; u32 dphy_param_reg = dsi_config->regs.dphy_param_reg; u32 dsi_func_prg_reg = dsi_config->regs.dsi_func_prg_reg; PSB_DEBUG_ENTRY("%s: initializing dsi controller on pipe %d\n", __func__, pipe); hw_ctx->mipi_control = 0x18; hw_ctx->intr_en = 0xffffffff; hw_ctx->hs_tx_timeout = 0xffffff; hw_ctx->lp_rx_timeout = 0xffffff; hw_ctx->turn_around_timeout = 0x14; hw_ctx->device_reset_timer = 0xff; hw_ctx->high_low_switch_count = 0x25; hw_ctx->init_count = 0xf0; hw_ctx->eot_disable = 0x0; hw_ctx->lp_byteclk = 0x4; hw_ctx->clk_lane_switch_time_cnt = 0xa0014; hw_ctx->dphy_param = 0x150a600f; /*setup video mode format*/ hw_ctx->video_mode_format = 0xf; /*set up func_prg*/ hw_ctx->dsi_func_prg = (0x200 | lane_count); if (update) { REG_WRITE(dphy_param_reg, hw_ctx->dphy_param); REG_WRITE(mipi_control_reg, hw_ctx->mipi_control); REG_WRITE(intr_en_reg, hw_ctx->intr_en); REG_WRITE(hs_tx_timeout_reg, hw_ctx->hs_tx_timeout); REG_WRITE(lp_rx_timeout_reg, hw_ctx->lp_rx_timeout); REG_WRITE(turn_around_timeout_reg, hw_ctx->turn_around_timeout); REG_WRITE(device_reset_timer_reg, hw_ctx->device_reset_timer); REG_WRITE(high_low_switch_count_reg, hw_ctx->high_low_switch_count); REG_WRITE(init_count_reg, hw_ctx->init_count); REG_WRITE(eot_disable_reg, hw_ctx->eot_disable); REG_WRITE(lp_byteclk_reg, hw_ctx->lp_byteclk); REG_WRITE(clk_lane_switch_time_cnt_reg, hw_ctx->clk_lane_switch_time_cnt); REG_WRITE(video_mode_format_reg, hw_ctx->video_mode_format); REG_WRITE(dsi_func_prg_reg, hw_ctx->dsi_func_prg); } }
static int mv88e6123_61_65_setup_global(struct dsa_switch *ds) { int ret; int i; REG_WRITE(REG_GLOBAL, 0x04, 0x0000); REG_WRITE(REG_GLOBAL, 0x0a, 0x0148); ret = mv88e6xxx_config_prio(ds); if (ret < 0) return ret; REG_WRITE(REG_GLOBAL, 0x1a, (dsa_upstream_port(ds) * 0x1110)); REG_WRITE(REG_GLOBAL, 0x1c, ds->index & 0x1f); REG_WRITE(REG_GLOBAL2, 0x02, 0xffff); REG_WRITE(REG_GLOBAL2, 0x03, 0xffff); REG_WRITE(REG_GLOBAL2, 0x05, 0x00ff); for (i = 0; i < 32; i++) { int nexthop; nexthop = 0x1f; if (i != ds->index && i < ds->dst->pd->nr_chips) nexthop = ds->pd->rtable[i] & 0x1f; REG_WRITE(REG_GLOBAL2, 0x06, 0x8000 | (i << 8) | nexthop); } for (i = 0; i < 8; i++) REG_WRITE(REG_GLOBAL2, 0x07, 0x8000 | (i << 12) | 0xff); for (i = 0; i < 16; i++) REG_WRITE(REG_GLOBAL2, 0x08, 0x8000 | (i << 11)); for (i = 0; i < 6; i++) REG_WRITE(REG_GLOBAL2, 0x09, 0x9000 | (i << 8)); REG_WRITE(REG_GLOBAL2, 0x0b, 0x9000); for (i = 0; i < 16; i++) REG_WRITE(REG_GLOBAL2, 0x0f, 0x8000 | (i << 8)); return 0; }
static ssize_t read_file_dma(struct file *file, char __user *user_buf, size_t count, loff_t *ppos) { struct ath_softc *sc = file->private_data; struct ath_hw *ah = sc->sc_ah; char buf[1024]; unsigned int len = 0; u32 val[ATH9K_NUM_DMA_DEBUG_REGS]; int i, qcuOffset = 0, dcuOffset = 0; u32 *qcuBase = &val[0], *dcuBase = &val[4]; REG_WRITE(ah, AR_MACMISC, ((AR_MACMISC_DMA_OBS_LINE_8 << AR_MACMISC_DMA_OBS_S) | (AR_MACMISC_MISC_OBS_BUS_1 << AR_MACMISC_MISC_OBS_BUS_MSB_S))); len += snprintf(buf + len, sizeof(buf) - len, "Raw DMA Debug values:\n"); for (i = 0; i < ATH9K_NUM_DMA_DEBUG_REGS; i++) { if (i % 4 == 0) len += snprintf(buf + len, sizeof(buf) - len, "\n"); val[i] = REG_READ(ah, AR_DMADBG_0 + (i * sizeof(u32))); len += snprintf(buf + len, sizeof(buf) - len, "%d: %08x ", i, val[i]); } len += snprintf(buf + len, sizeof(buf) - len, "\n\n"); len += snprintf(buf + len, sizeof(buf) - len, "Num QCU: chain_st fsp_ok fsp_st DCU: chain_st\n"); for (i = 0; i < ATH9K_NUM_QUEUES; i++, qcuOffset += 4, dcuOffset += 5) { if (i == 8) { qcuOffset = 0; qcuBase++; } if (i == 6) { dcuOffset = 0; dcuBase++; } len += snprintf(buf + len, sizeof(buf) - len, "%2d %2x %1x %2x %2x\n", i, (*qcuBase & (0x7 << qcuOffset)) >> qcuOffset, (*qcuBase & (0x8 << qcuOffset)) >> (qcuOffset + 3), val[2] & (0x7 << (i * 3)) >> (i * 3), (*dcuBase & (0x1f << dcuOffset)) >> dcuOffset); } len += snprintf(buf + len, sizeof(buf) - len, "\n"); len += snprintf(buf + len, sizeof(buf) - len, "qcu_stitch state: %2x qcu_fetch state: %2x\n", (val[3] & 0x003c0000) >> 18, (val[3] & 0x03c00000) >> 22); len += snprintf(buf + len, sizeof(buf) - len, "qcu_complete state: %2x dcu_complete state: %2x\n", (val[3] & 0x1c000000) >> 26, (val[6] & 0x3)); len += snprintf(buf + len, sizeof(buf) - len, "dcu_arb state: %2x dcu_fp state: %2x\n", (val[5] & 0x06000000) >> 25, (val[5] & 0x38000000) >> 27); len += snprintf(buf + len, sizeof(buf) - len, "chan_idle_dur: %3d chan_idle_dur_valid: %1d\n", (val[6] & 0x000003fc) >> 2, (val[6] & 0x00000400) >> 10); len += snprintf(buf + len, sizeof(buf) - len, "txfifo_valid_0: %1d txfifo_valid_1: %1d\n", (val[6] & 0x00000800) >> 11, (val[6] & 0x00001000) >> 12); len += snprintf(buf + len, sizeof(buf) - len, "txfifo_dcu_num_0: %2d txfifo_dcu_num_1: %2d\n", (val[6] & 0x0001e000) >> 13, (val[6] & 0x001e0000) >> 17); len += snprintf(buf + len, sizeof(buf) - len, "pcu observe: 0x%x \n", REG_READ(ah, AR_OBS_BUS_1)); len += snprintf(buf + len, sizeof(buf) - len, "AR_CR: 0x%x \n", REG_READ(ah, AR_CR)); return simple_read_from_buffer(user_buf, count, ppos, buf, len); }
nt5cb256m8fn_di_cs0_freq333_cl5_bl8() { // configuration for nt5cb256m8fn_di, frequency is 333, // cl is 5, bl is 8, cs0 is enable REG_WRITE(DDR_BASE_ADDR + 0x0, 0x00000600); REG_WRITE(DDR_BASE_ADDR + 0x8, 0x00000004); REG_WRITE(DDR_BASE_ADDR + 0x18, 0x0001046b); REG_WRITE(DDR_BASE_ADDR + 0x1c, 0x00028b0b); REG_WRITE(DDR_BASE_ADDR + 0x20, 0x0404050a); REG_WRITE(DDR_BASE_ADDR + 0x24, 0x040c1104); REG_WRITE(DDR_BASE_ADDR + 0x28, 0x0c040405); REG_WRITE(DDR_BASE_ADDR + 0x2c, 0x03005b68); REG_WRITE(DDR_BASE_ADDR + 0x30, 0x01000004); REG_WRITE(DDR_BASE_ADDR + 0x34, 0x0a050501); REG_WRITE(DDR_BASE_ADDR + 0x38, 0x050a0300); REG_WRITE(DDR_BASE_ADDR + 0x40, 0x00003601); REG_WRITE(DDR_BASE_ADDR + 0x44, 0x00000a20); REG_WRITE(DDR_BASE_ADDR + 0x48, 0x000a0003); REG_WRITE(DDR_BASE_ADDR + 0x4c, 0x00390200); REG_WRITE(DDR_BASE_ADDR + 0x50, 0x00010000); REG_WRITE(DDR_BASE_ADDR + 0x54, 0x00050500); REG_WRITE(DDR_BASE_ADDR + 0x78, 0x00460210); REG_WRITE(DDR_BASE_ADDR + 0x84, 0x00021000); REG_WRITE(DDR_BASE_ADDR + 0x88, 0x00000046); REG_WRITE(DDR_BASE_ADDR + 0x94, 0x01010000); REG_WRITE(DDR_BASE_ADDR + 0xa4, 0x01000200); REG_WRITE(DDR_BASE_ADDR + 0xa8, 0x02000040); REG_WRITE(DDR_BASE_ADDR + 0xb0, 0x00000100); REG_WRITE(DDR_BASE_ADDR + 0xb4, 0xffff0a00); REG_WRITE(DDR_BASE_ADDR + 0xb8, 0x01010101); REG_WRITE(DDR_BASE_ADDR + 0xbc, 0x01010101); REG_WRITE(DDR_BASE_ADDR + 0xc0, 0x00000303); REG_WRITE(DDR_BASE_ADDR + 0xc4, 0x00000c01); //redefined REG_WRITE(DDR_BASE_ADDR + 0xcc, 0x00000100); REG_WRITE(DDR_BASE_ADDR + 0x104, 0x00000100); //redefined REG_WRITE(DDR_BASE_ADDR + 0x108, 0x02020001); REG_WRITE(DDR_BASE_ADDR + 0x10c, 0x01020201); REG_WRITE(DDR_BASE_ADDR + 0x110, 0x00000200); REG_WRITE(DDR_BASE_ADDR + 0x114, 0x00000101); REG_WRITE(DDR_BASE_ADDR + 0x120, 0x281a0000); REG_WRITE(DDR_BASE_ADDR + 0x12c, 0x00010001); REG_WRITE(DDR_BASE_ADDR + 0x130, 0x00010001); REG_WRITE(DDR_BASE_ADDR + 0x144, 0x00202000); REG_WRITE(DDR_BASE_ADDR + 0x148, 0x00000001); REG_WRITE(DDR_BASE_ADDR + 0x154, 0x00012020); REG_WRITE(DDR_BASE_ADDR + 0x160, 0x00202000); REG_WRITE(DDR_BASE_ADDR + 0x164, 0x00000001); REG_WRITE(DDR_BASE_ADDR + 0x170, 0x00012020); REG_WRITE(DDR_BASE_ADDR + 0x174, 0x08085555); REG_WRITE(DDR_BASE_ADDR + 0x180, 0x00000700); REG_WRITE(DDR_BASE_ADDR + 0x184, 0x000a2000); REG_WRITE(DDR_BASE_ADDR + 0x188, 0x02000200); REG_WRITE(DDR_BASE_ADDR + 0x18c, 0x02000200); REG_WRITE(DDR_BASE_ADDR + 0x190, 0x00000a20); REG_WRITE(DDR_BASE_ADDR + 0x194, 0x000032a0); REG_WRITE(DDR_BASE_ADDR + 0x198, 0x00020505); REG_WRITE(DDR_BASE_ADDR + 0x19c, 0x03800001); REG_WRITE(DDR_BASE_ADDR + 0x1a0, 0x00040703); REG_WRITE(DDR_BASE_ADDR + 0x1a4, 0x0000000a); REG_WRITE(DDR_BASE_ADDR + 0x1b0, 0x0010ffff); REG_WRITE(DDR_BASE_ADDR + 0x1b4, 0x11070303); REG_WRITE(DDR_BASE_ADDR + 0x1b8, 0x0000000f); REG_WRITE(DDR_BASE_ADDR + 0x1d0, 0x00000204); REG_WRITE(DDR_BASE_ADDR + 0x1dc, 0x00000001); REG_WRITE(DDR_BASE_ADDR + 0x1e0, 0x00000040); REG_WRITE(DDR_BASE_ADDR + 0x1e4, 0x01010100); REG_WRITE(DDR_BASE_ADDR + 0x1e8, 0x00000004); REG_WRITE(DDR_BASE_ADDR + 0x200, 0x26122612); REG_WRITE(DDR_BASE_ADDR + 0x204, 0x26142614); REG_WRITE(DDR_BASE_ADDR + 0x208, 0x00d90060); REG_WRITE(DDR_BASE_ADDR + 0x20c, 0x01121e25); REG_WRITE(DDR_BASE_ADDR + 0x210, 0x20202020); REG_WRITE(DDR_BASE_ADDR + 0x240, 0x26122612); REG_WRITE(DDR_BASE_ADDR + 0x244, 0x26142614); REG_WRITE(DDR_BASE_ADDR + 0x248, 0x00d90060); REG_WRITE(DDR_BASE_ADDR + 0x24c, 0x01121e25); REG_WRITE(DDR_BASE_ADDR + 0x250, 0x20202020); REG_WRITE(DDR_BASE_ADDR + 0x280, 0x26122612); REG_WRITE(DDR_BASE_ADDR + 0x284, 0x26142614); REG_WRITE(DDR_BASE_ADDR + 0x288, 0x00d90060); REG_WRITE(DDR_BASE_ADDR + 0x28c, 0x01121e25); REG_WRITE(DDR_BASE_ADDR + 0x290, 0x20202020); REG_WRITE(DDR_BASE_ADDR + 0x2c0, 0x26122612); REG_WRITE(DDR_BASE_ADDR + 0x2c4, 0x26142614); REG_WRITE(DDR_BASE_ADDR + 0x2c8, 0x00d90060); REG_WRITE(DDR_BASE_ADDR + 0x2cc, 0x01121e25); REG_WRITE(DDR_BASE_ADDR + 0x2d0, 0x20202020); REG_WRITE(DDR_BASE_ADDR + 0x300, 0x26122612); REG_WRITE(DDR_BASE_ADDR + 0x304, 0x26142614); REG_WRITE(DDR_BASE_ADDR + 0x308, 0x00d90060); REG_WRITE(DDR_BASE_ADDR + 0x30c, 0x01121e25); REG_WRITE(DDR_BASE_ADDR + 0x310, 0x20202020); REG_WRITE(DDR_BASE_ADDR + 0x344, 0x00005004); REG_WRITE(DDR_BASE_ADDR + 0x348, 0x40004000); REG_WRITE(DDR_BASE_ADDR + 0x34c, 0x7fff7fff); REG_WRITE(DDR_BASE_ADDR + 0x350, 0x7fff7fff); REG_WRITE(DDR_BASE_ADDR + 0x354, 0x7fff7fff); REG_WRITE(DDR_BASE_ADDR + 0x358, 0x40004000); REG_WRITE(DDR_BASE_ADDR + 0x35c, 0x40004000); REG_WRITE(DDR_BASE_ADDR + 0x360, 0x40004000); REG_WRITE(DDR_BASE_ADDR + 0x364, 0x7fff7fff); REG_WRITE(DDR_BASE_ADDR + 0x368, 0x7fff7fff); REG_WRITE(DDR_BASE_ADDR + 0x36c, 0x7fff7fff); REG_WRITE(DDR_BASE_ADDR + 0x370, 0x40004000); REG_WRITE(DDR_BASE_ADDR + 0x374, 0x40004000); REG_WRITE(DDR_BASE_ADDR + 0x378, 0x40004000); }
/* * mdfld_restore_display_registers * * Description: We are going to resume so restore display register state. * * Notes: FIXME_JLIU7 need to add the support for DPI MIPI & HDMI audio */ static int mdfld_restore_display_registers(struct drm_device *dev, int pipenum) { /* To get panel out of ULPS mode. */ u32 temp = 0; u32 device_ready_reg = DEVICE_READY_REG; struct drm_psb_private *dev_priv = dev->dev_private; struct mdfld_dsi_config *dsi_config = NULL; struct medfield_state *regs = &dev_priv->regs.mdfld; struct psb_pipe *pipe = &dev_priv->regs.pipe[pipenum]; const struct psb_offset *map = &dev_priv->regmap[pipenum]; u32 i; u32 dpll; u32 timeout = 0; /* register */ u32 mipi_reg = MIPI; /* values */ u32 dpll_val = pipe->dpll; u32 mipi_val = regs->saveMIPI; switch (pipenum) { case 0: dpll_val &= ~DPLL_VCO_ENABLE; dsi_config = dev_priv->dsi_configs[0]; break; case 1: dpll_val &= ~DPLL_VCO_ENABLE; break; case 2: mipi_reg = MIPI_C; mipi_val = regs->saveMIPI_C; dsi_config = dev_priv->dsi_configs[1]; break; default: DRM_ERROR("%s, invalid pipe number.\n", __func__); return -EINVAL; } /*make sure VGA plane is off. it initializes to on after reset!*/ PSB_WVDC32(0x80000000, VGACNTRL); if (pipenum == 1) { PSB_WVDC32(dpll_val & ~DPLL_VCO_ENABLE, map->dpll); PSB_RVDC32(map->dpll); PSB_WVDC32(pipe->fp0, map->fp0); } else { dpll = PSB_RVDC32(map->dpll); if (!(dpll & DPLL_VCO_ENABLE)) { /* When ungating power of DPLL, needs to wait 0.5us before enable the VCO */ if (dpll & MDFLD_PWR_GATE_EN) { dpll &= ~MDFLD_PWR_GATE_EN; PSB_WVDC32(dpll, map->dpll); /* FIXME_MDFLD PO - change 500 to 1 after PO */ udelay(500); } PSB_WVDC32(pipe->fp0, map->fp0); PSB_WVDC32(dpll_val, map->dpll); /* FIXME_MDFLD PO - change 500 to 1 after PO */ udelay(500); dpll_val |= DPLL_VCO_ENABLE; PSB_WVDC32(dpll_val, map->dpll); PSB_RVDC32(map->dpll); /* wait for DSI PLL to lock */ while (timeout < 20000 && !(PSB_RVDC32(map->conf) & PIPECONF_DSIPLL_LOCK)) { udelay(150); timeout++; } if (timeout == 20000) { DRM_ERROR("%s, can't lock DSIPLL.\n", __func__); return -EINVAL; } } } /* Restore mode */ PSB_WVDC32(pipe->htotal, map->htotal); PSB_WVDC32(pipe->hblank, map->hblank); PSB_WVDC32(pipe->hsync, map->hsync); PSB_WVDC32(pipe->vtotal, map->vtotal); PSB_WVDC32(pipe->vblank, map->vblank); PSB_WVDC32(pipe->vsync, map->vsync); PSB_WVDC32(pipe->src, map->src); PSB_WVDC32(pipe->status, map->status); /*set up the plane*/ PSB_WVDC32(pipe->stride, map->stride); PSB_WVDC32(pipe->linoff, map->linoff); PSB_WVDC32(pipe->tileoff, map->tileoff); PSB_WVDC32(pipe->size, map->size); PSB_WVDC32(pipe->pos, map->pos); PSB_WVDC32(pipe->surf, map->surf); if (pipenum == 1) { /* restore palette (gamma) */ /*DRM_UDELAY(50000); */ for (i = 0; i < 256; i++) PSB_WVDC32(pipe->palette[i], map->palette + (i << 2)); PSB_WVDC32(regs->savePFIT_CONTROL, PFIT_CONTROL); PSB_WVDC32(regs->savePFIT_PGM_RATIOS, PFIT_PGM_RATIOS); /*TODO: resume HDMI port */ /*TODO: resume pipe*/ /*enable the plane*/ PSB_WVDC32(pipe->cntr & ~DISPLAY_PLANE_ENABLE, map->cntr); return 0; } /*set up pipe related registers*/ PSB_WVDC32(mipi_val, mipi_reg); /*setup MIPI adapter + MIPI IP registers*/ if (dsi_config) mdfld_dsi_controller_init(dsi_config, pipenum); if (in_atomic() || in_interrupt()) mdelay(20); else msleep(20); /*enable the plane*/ PSB_WVDC32(pipe->cntr, map->cntr); if (in_atomic() || in_interrupt()) mdelay(20); else msleep(20); /* LP Hold Release */ temp = REG_READ(mipi_reg); temp |= LP_OUTPUT_HOLD_RELEASE; REG_WRITE(mipi_reg, temp); mdelay(1); /* Set DSI host to exit from Utra Low Power State */ temp = REG_READ(device_ready_reg); temp &= ~ULPS_MASK; temp |= 0x3; temp |= EXIT_ULPS_DEV_READY; REG_WRITE(device_ready_reg, temp); mdelay(1); temp = REG_READ(device_ready_reg); temp &= ~ULPS_MASK; temp |= EXITING_ULPS; REG_WRITE(device_ready_reg, temp); mdelay(1); /*enable the pipe*/ PSB_WVDC32(pipe->conf, map->conf); /* restore palette (gamma) */ /*DRM_UDELAY(50000); */ for (i = 0; i < 256; i++) PSB_WVDC32(pipe->palette[i], map->palette + (i << 2)); return 0; }
void ath9k_hw_puttxbuf(struct ath_hw *ah, u32 q, u32 txdp) { REG_WRITE(ah, AR_QTXDP(q), txdp); }
UINT32 FlashInit (PFLASH_SSD_CONFIG PSSDConfig) { #if (DEBLOCK_SIZE != 0) UINT8 EEEDataSetSize; /* store EEE Data Set Size */ UINT8 DEPartitionCode; /* store D/E-Flash Partition Code */ #endif UINT32 returnCode; /* return code variable */ /* set the default return code as FTFx_OK */ returnCode = FTFx_OK; #if (DEBLOCK_SIZE != 0) /* check CCIF bit of the flash status register */ while(FALSE == (REG_BIT_TEST(PSSDConfig->ftfxRegBase + FTFx_SSD_FSTAT_OFFSET, FTFx_SSD_FSTAT_CCIF))) { /* wait till CCIF bit is set */ } /* clear RDCOLERR & ACCERR & FPVIOL flag in flash status register */ REG_WRITE(PSSDConfig->ftfxRegBase + FTFx_SSD_FSTAT_OFFSET, \ (FTFx_SSD_FSTAT_RDCOLERR | FTFx_SSD_FSTAT_ACCERR | FTFx_SSD_FSTAT_FPVIOL)); /* Write Command Code to FCCOB0 */ REG_WRITE(PSSDConfig->ftfxRegBase + FTFx_SSD_FCCOB0_OFFSET, FTFx_READ_RESOURCE); /* Write address to FCCOB1/2/3 */ REG_WRITE(PSSDConfig->ftfxRegBase + FTFx_SSD_FCCOB1_OFFSET, ((UINT8)(DFLASH_IFR_READRESOURCE_ADDRESS >> 16))); REG_WRITE(PSSDConfig->ftfxRegBase + FTFx_SSD_FCCOB2_OFFSET, ((UINT8)((DFLASH_IFR_READRESOURCE_ADDRESS >> 8) & 0xFF))); REG_WRITE(PSSDConfig->ftfxRegBase + FTFx_SSD_FCCOB3_OFFSET, ((UINT8)(DFLASH_IFR_READRESOURCE_ADDRESS & 0xFF))); /* Write Resource Select Code of 0 to FCCOB8 to select IFR. Without this, */ /* an access error may occur if the register contains data from a previous command. */ #if ((FTFx_KX_512K_512K_16K_4K_4K == FLASH_DERIVATIVE) || (FTFx_KX_1024K_256K_4K_4K_4K == FLASH_DERIVATIVE)) REG_WRITE(PSSDConfig->ftfxRegBase + FTFx_SSD_FCCOB4_OFFSET, 0); #else REG_WRITE(PSSDConfig->ftfxRegBase + FTFx_SSD_FCCOB8_OFFSET, 0); #endif /* clear CCIF bit */ REG_WRITE(PSSDConfig->ftfxRegBase + FTFx_SSD_FSTAT_OFFSET, FTFx_SSD_FSTAT_CCIF); /* check CCIF bit */ while((REG_BIT_TEST(PSSDConfig->ftfxRegBase + FTFx_SSD_FSTAT_OFFSET, FTFx_SSD_FSTAT_CCIF)) == FALSE) { /* wait till CCIF bit is set */ } /* Read returned value of FCCOB6/7 or FCCOBA,B to the variables */ #if ((FTFx_KX_512K_512K_16K_4K_4K == FLASH_DERIVATIVE) || (FTFx_KX_1024K_256K_4K_4K_4K == FLASH_DERIVATIVE)) EEEDataSetSize = REG_READ(PSSDConfig->ftfxRegBase + FTFx_SSD_FCCOBA_OFFSET); DEPartitionCode = REG_READ(PSSDConfig->ftfxRegBase + FTFx_SSD_FCCOBB_OFFSET); #else EEEDataSetSize = REG_READ(PSSDConfig->ftfxRegBase + FTFx_SSD_FCCOB6_OFFSET); DEPartitionCode = REG_READ(PSSDConfig->ftfxRegBase + FTFx_SSD_FCCOB7_OFFSET); #endif /* Calculate D-Flash size and EEE size */ switch (DEPartitionCode & 0x0F) { case 0: PSSDConfig->DFlashBlockSize = DEPART_0000; break; case 1: PSSDConfig->DFlashBlockSize = DEPART_0001; break; case 2: PSSDConfig->DFlashBlockSize = DEPART_0010; break; case 3: PSSDConfig->DFlashBlockSize = DEPART_0011; break; case 4: PSSDConfig->DFlashBlockSize = DEPART_0100; break; case 5: PSSDConfig->DFlashBlockSize = DEPART_0101; break; case 6: PSSDConfig->DFlashBlockSize = DEPART_0110; break; case 7: PSSDConfig->DFlashBlockSize = DEPART_0111; break; case 8: PSSDConfig->DFlashBlockSize = DEPART_1000; break; case 9: PSSDConfig->DFlashBlockSize = DEPART_1001; break; case 10: PSSDConfig->DFlashBlockSize = DEPART_1010; break; case 11: PSSDConfig->DFlashBlockSize = DEPART_1011; break; case 12: PSSDConfig->DFlashBlockSize = DEPART_1100; break; case 13: PSSDConfig->DFlashBlockSize = DEPART_1101; break; case 14: PSSDConfig->DFlashBlockSize = DEPART_1110; break; case 15: PSSDConfig->DFlashBlockSize = DEPART_1111; break; default: break; } switch (EEEDataSetSize & 0x0F) { case 0: PSSDConfig->EEEBlockSize = EEESIZE_0000; break; case 1: PSSDConfig->EEEBlockSize = EEESIZE_0001; break; case 2: PSSDConfig->EEEBlockSize = EEESIZE_0010; break; case 3: PSSDConfig->EEEBlockSize = EEESIZE_0011; break; case 4: PSSDConfig->EEEBlockSize = EEESIZE_0100; break; case 5: PSSDConfig->EEEBlockSize = EEESIZE_0101; break; case 6: PSSDConfig->EEEBlockSize = EEESIZE_0110; break; case 7: PSSDConfig->EEEBlockSize = EEESIZE_0111; break; case 8: PSSDConfig->EEEBlockSize = EEESIZE_1000; break; case 9: PSSDConfig->EEEBlockSize = EEESIZE_1001; break; case 10: PSSDConfig->EEEBlockSize = EEESIZE_1010; break; case 11: PSSDConfig->EEEBlockSize = EEESIZE_1011; break; case 12: PSSDConfig->EEEBlockSize = EEESIZE_1100; break; case 13: PSSDConfig->EEEBlockSize = EEESIZE_1101; break; case 14: PSSDConfig->EEEBlockSize = EEESIZE_1110; break; case 15: PSSDConfig->EEEBlockSize = EEESIZE_1111; break; default: break; } #else /* DEBLOCK_SIZE == 0 */ /* If size of D/E-Flash = 0 */ PSSDConfig->DFlashBlockSize = 0; PSSDConfig->EEEBlockSize = 0; #endif /* of DEBLOCK_SIZE */ /* Enter Debug state if enabled */ if (TRUE == (PSSDConfig->DebugEnable)) { #if ((CPU_CORE == ARM_CM4) && (COMPILER == IAR)) /* Kx Products */ asm ( " BKPT #0 \n " /* enter Debug state */ ); #endif } return(returnCode); }