void rkclk_configure_sdmmc(DwmciHost *host, unsigned int freq)
{
int src_clk_div;
dwmci_writel(host, DWMCI_CLKDIV, 0);
src_clk_div = ALIGN_UP(host->src_hz / 2, freq) / freq;
if (src_clk_div > 0x3f) {
src_clk_div = (24000000 / 2 + freq - 1) / freq;
writel(RK_CLRSETBITS(0x7ff, 5 << 8 | (src_clk_div - 1)),
&cru_ptr->clksel_con[16]);
} else
writel(RK_CLRSETBITS(0x7ff, 1 << 8 | (src_clk_div - 1)),
&cru_ptr->clksel_con[16]);
}
static void __gpio_input(gpio_t gpio, u32 pull)
{
clrbits_le32(&gpio_port[gpio.port]->swporta_ddr, 1 << gpio.num);
if (gpio.port == PMU_GPIO_PORT)
clrsetbits_le32(&rk3288_pmu->gpio0pull[gpio.bank],
3 << (gpio.idx * 2), pull << (gpio.idx * 2));
else
write32(&rk3288_grf->gpio1_p[(gpio.port - 1)][gpio.bank],
RK_CLRSETBITS(3 << (gpio.idx * 2),
pull << (gpio.idx * 2)));
}
static void configure_emmc(void)
{
/* Host controller does not support programmable clock generator.
* If we don't do this setting, when we use phy to control the
* emmc clock(when clock exceed 50MHz), it will get wrong clock.
*
* Refer to TRM V0.3 Part 1 Chapter 15 PAGE 782 for this register.
* Please search "_CON11[7:0]" to locate register description.
*/
write32(&rk3399_grf->emmccore_con[11], RK_CLRSETBITS(0xff, 0));
rkclk_configure_emmc();
}
