/*-------------------------------------------------------------------*/
void Map109_Init()
{
/* Initialize Mapper */
MapperInit = Map109_Init;
/* Write to Mapper */
MapperWrite = Map0_Write;
/* Write to SRAM */
MapperSram = Map0_Sram;
/* Write to APU */
MapperApu = Map109_Apu;
/* Read from APU */
MapperReadApu = Map0_ReadApu;
/* Callback at VSync */
MapperVSync = Map0_VSync;
/* Callback at HSync */
MapperHSync = Map0_HSync;
/* Callback at PPU */
MapperPPU = Map0_PPU;
/* Callback at Rendering Screen ( 1:BG, 0:Sprite ) */
MapperRenderScreen = Map0_RenderScreen;
/* Set SRAM Banks */
SRAMBANK = SRAM;
/* Set ROM Banks */
ROMBANK0 = ROMPAGE( 0 );
ROMBANK1 = ROMPAGE( 1 );
ROMBANK2 = ROMPAGE( 2 );
ROMBANK3 = ROMPAGE( 3 );
/* Initialize Registers */
Map109_Reg = 0;
Map109_Chr0 = 0;
Map109_Chr1 = 0;
Map109_Chr2 = 0;
Map109_Chr3 = 0;
Map109_Chrmode0 = 0;
Map109_Chrmode1 = 0;
/* Set PPU Banks */
Map109_Set_PPU_Banks();
/* Set up wiring of the interrupt pin */
K6502_Set_Int_Wiring( 1, 1 );
}
/*-------------------------------------------------------------------*/
void Map43_Init()
{
/* Initialize Mapper */
MapperInit = Map43_Init;
/* Write to Mapper */
MapperWrite = Map43_Write;
/* Write to SRAM */
MapperSram = Map0_Sram;
/* Write to APU */
MapperApu = Map43_Apu;
/* Read from APU */
MapperReadApu = Map43_ReadApu;
/* Callback at VSync */
MapperVSync = Map0_VSync;
/* Callback at HSync */
MapperHSync = Map43_HSync;
/* Callback at PPU */
MapperPPU = Map0_PPU;
/* Callback at Rendering Screen ( 1:BG, 0:Sprite ) */
MapperRenderScreen = Map0_RenderScreen;
/* Set SRAM Banks */
SRAMBANK = ROMPAGE( 2 );
/* Set ROM Banks */
ROMBANK0 = ROMPAGE( 1 );
ROMBANK1 = ROMPAGE( 0 );
ROMBANK2 = ROMPAGE( 4 );
ROMBANK3 = ROMPAGE( 9 );
/* Initialize State Registers */
Map43_IRQ_Enable = 1;
Map43_IRQ_Cnt = 0;
/* Set PPU Banks */
if ( NesHeader.byVRomSize > 0 )
{
for ( int nPage = 0; nPage < 8; ++nPage )
PPUBANK[ nPage ] = VROMPAGE( nPage );
InfoNES_SetupChr();
}
/* Set up wiring of the interrupt pin */
K6502_Set_Int_Wiring( 1, 1 );
}
void Map45_Init()
{
MapperInit = Map45_Init;
MapperWrite = Map45_Write;
MapperSram = Map45_Sram;
MapperApu = Map0_Apu;
MapperReadApu = Map0_ReadApu;
MapperVSync = Map0_VSync;
MapperHSync = Map45_HSync;
MapperPPU = Map0_PPU;
/* Callback at Rendering Screen ( 1:BG, 0:Sprite ) */
MapperRenderScreen = Map0_RenderScreen;
/* Set SRAM Banks */
W.SRAMBANK = S.SRAM;
/* Set ROM Banks */
Map45_Prg0 = 0;
Map45_Prg1 = 1;
Map45_Prg2 = S.NesHeader.ROMSize * 2 - 2;
Map45_Prg3 = S.NesHeader.ROMSize * 2 - 1;
W.ROMBANK0 = ROMPAGE( Map45_Prg0 ); Map45_P[0] = Map45_Prg0;
W.ROMBANK1 = ROMPAGE( Map45_Prg1 ); Map45_P[1] = Map45_Prg1;
W.ROMBANK2 = ROMPAGE( Map45_Prg2 ); Map45_P[2] = Map45_Prg2;
W.ROMBANK3 = ROMPAGE( Map45_Prg3 ); Map45_P[3] = Map45_Prg3;
/* Set PPU Banks */
Map45_Chr0 = 0; Map45_C[0] = Map45_Chr0;
Map45_Chr1 = 1; Map45_C[1] = Map45_Chr1;
Map45_Chr2 = 2; Map45_C[2] = Map45_Chr2;
Map45_Chr3 = 3; Map45_C[3] = Map45_Chr3;
Map45_Chr4 = 4; Map45_C[4] = Map45_Chr4;
Map45_Chr5 = 5; Map45_C[5] = Map45_Chr5;
Map45_Chr6 = 6; Map45_C[6] = Map45_Chr6;
Map45_Chr7 = 7; Map45_C[7] = Map45_Chr7;
int nPage ;
for (nPage = 0; nPage < 8; ++nPage ) {
W.PPUBANK[ nPage ] = VROMPAGE( nPage );
}
NESCore_Develop_Character_Data();
/* Initialize IRQ Registers */
Map45_IRQ_Enable = 0;
Map45_IRQ_Cnt = 0;
Map45_IRQ_Latch = 0;
Map45_Regs[0] = Map45_Regs[1] = Map45_Regs[2] = Map45_Regs[3] = 0;
Map45_Regs[4] = Map45_Regs[5] = Map45_Regs[6] = 0;
}
void Map32_Init()
{
/* Initialize Mapper */
MapperInit = Map32_Init;
/* Write to Mapper */
MapperWrite = Map32_Write;
/* Write to SRAM */
MapperSram = Map0_Sram;
/* Write to APU */
MapperApu = Map0_Apu;
/* Read from APU */
MapperReadApu = Map0_ReadApu;
/* Callback at VSync */
MapperVSync = Map0_VSync;
/* Callback at HSync */
MapperHSync = Map0_HSync;
/* Callback at PPU */
MapperPPU = Map0_PPU;
/* Callback at Rendering Screen ( 1:BG, 0:Sprite ) */
MapperRenderScreen = Map0_RenderScreen;
/* Initialize state flag */
Map32_Saved = 0x00;
/* Set SRAM Banks */
W.SRAMBANK = S.SRAM;
/* Set ROM Banks */
W.ROMBANK0 = ROMPAGE( 0 );
W.ROMBANK1 = ROMPAGE( 1 );
W.ROMBANK2 = ROMLASTPAGE( 1 );
W.ROMBANK3 = ROMLASTPAGE( 0 );
/* Set PPU Banks */
if ( S.NesHeader.VROMSize > 0 )
{
int nPage ;
for (nPage = 0; nPage < 8; ++nPage )
W.PPUBANK[ nPage ] = VROMPAGE( nPage );
NESCore_Develop_Character_Data();
}
}
/*-------------------------------------------------------------------*/
void Map18_Init()
{
/* Initialize Mapper */
MapperInit = Map18_Init;
/* Write to Mapper */
MapperWrite = Map18_Write;
/* Write to SRAM */
MapperSram = Map0_Sram;
/* Write to APU */
MapperApu = Map0_Apu;
/* Read from APU */
MapperReadApu = Map0_ReadApu;
/* Callback at VSync */
MapperVSync = Map0_VSync;
/* Callback at HSync */
MapperHSync = Map18_HSync;
/* Callback at PPU */
MapperPPU = Map0_PPU;
/* Callback at Rendering Screen ( 1:BG, 0:Sprite ) */
MapperRenderScreen = Map0_RenderScreen;
/* Set SRAM Banks */
SRAMBANK = SRAM;
/* Set ROM Banks */
ROMBANK0 = ROMPAGE( 0 );
ROMBANK1 = ROMPAGE( 1 );
ROMBANK2 = ROMLASTPAGE( 1 );
ROMBANK3 = ROMLASTPAGE( 0 );
/* Initialize Regs */
int i ;
for (i = 0; i < sizeof( Map18_Regs ); i++ )
{
Map18_Regs[ i ] = 0;
}
Map18_IRQ_Enable = 0;
Map18_IRQ_Latch = 0;
Map18_IRQ_Cnt = 0;
/* Set up wiring of the interrupt pin */
K6502_Set_Int_Wiring( 1, 1 );
}
/*-------------------------------------------------------------------*/
void Map135_Apu( word wAddr, byte byData )
{
switch( wAddr & 0x4101 ) {
case 0x4100:
Map135_Cmd = byData & 0x07;
break;
case 0x4101:
switch( Map135_Cmd ) {
case 0:
Map135_Chr0l = byData & 0x07;
Map135_Set_PPU_Banks();
break;
case 1:
Map135_Chr0h = byData & 0x07;
Map135_Set_PPU_Banks();
break;
case 2:
Map135_Chr1l = byData & 0x07;
Map135_Set_PPU_Banks();
break;
case 3:
Map135_Chr1h = byData & 0x07;
Map135_Set_PPU_Banks();
break;
case 4:
Map135_Chrch = byData & 0x07;
Map135_Set_PPU_Banks();
break;
case 5:
/* Set ROM Banks */
W.ROMBANK0 = ROMPAGE( (((byData%0x07)<<2) + 0 ) % (S.NesHeader.ROMSize << 1) );
W.ROMBANK1 = ROMPAGE( (((byData%0x07)<<2) + 1 ) % (S.NesHeader.ROMSize << 1) );
W.ROMBANK2 = ROMPAGE( (((byData%0x07)<<2) + 2 ) % (S.NesHeader.ROMSize << 1) );
W.ROMBANK3 = ROMPAGE( (((byData%0x07)<<2) + 3 ) % (S.NesHeader.ROMSize << 1) );
break;
case 6:
break;
case 7:
switch( (byData>>1)&0x03 ) {
case 0: NESCore_Mirroring( 2 ); break;
case 1: NESCore_Mirroring( 0 ); break;
case 2: NESCore_Mirroring( 1 ); break;
case 3: NESCore_Mirroring( 2 ); break;
}
break;
}
break;
}
//Map135_Wram[ wAddr & 0x1fff ] = byData;
}
/*-------------------------------------------------------------------*/
void Map243_Apu( word wAddr, byte byData )
{
if ( wAddr == 0x4100 )
{
Map243_Regs[0] = byData;
}
else if ( wAddr == 0x4101 )
{
switch ( Map243_Regs[0] & 0x07 )
{
case 0x02:
Map243_Regs[1] = byData & 0x01;
break;
case 0x00:
case 0x04:
case 0x07:
Map243_Regs[2] = ( byData & 0x01 ) << 1;
break;
/* Set ROM Banks */
case 0x05:
W.ROMBANK0 = ROMPAGE( ( byData * 4 + 0 ) % ( S.NesHeader.ROMSize << 1 ) );
W.ROMBANK1 = ROMPAGE( ( byData * 4 + 1 ) % ( S.NesHeader.ROMSize << 1 ) );
W.ROMBANK2 = ROMPAGE( ( byData * 4 + 2 ) % ( S.NesHeader.ROMSize << 1 ) );
W.ROMBANK3 = ROMPAGE( ( byData * 4 + 3 ) % ( S.NesHeader.ROMSize << 1 ) );
break;
case 0x06:
Map243_Regs[3] = ( byData & 0x03 ) << 2;
break;
}
/* Set PPU Banks */
if ( ( S.NesHeader.VROMSize << 3 ) <= 64 )
{
byte chr_bank = ( Map243_Regs[2] + Map243_Regs[3] ) >> 1;
W.PPUBANK[0] = VROMPAGE( ( chr_bank * 8 + 0 ) % ( S.NesHeader.VROMSize << 3 ) );
W.PPUBANK[1] = VROMPAGE( ( chr_bank * 8 + 1 ) % ( S.NesHeader.VROMSize << 3 ) );
W.PPUBANK[2] = VROMPAGE( ( chr_bank * 8 + 2 ) % ( S.NesHeader.VROMSize << 3 ) );
W.PPUBANK[3] = VROMPAGE( ( chr_bank * 8 + 3 ) % ( S.NesHeader.VROMSize << 3 ) );
W.PPUBANK[4] = VROMPAGE( ( chr_bank * 8 + 4 ) % ( S.NesHeader.VROMSize << 3 ) );
W.PPUBANK[5] = VROMPAGE( ( chr_bank * 8 + 5 ) % ( S.NesHeader.VROMSize << 3 ) );
W.PPUBANK[6] = VROMPAGE( ( chr_bank * 8 + 6 ) % ( S.NesHeader.VROMSize << 3 ) );
W.PPUBANK[7] = VROMPAGE( ( chr_bank * 8 + 7 ) % ( S.NesHeader.VROMSize << 3 ) );
NESCore_Develop_Character_Data();
}
else
{
/*-------------------------------------------------------------------*/
void Map193_Init()
{
int nPage;
/* Initialize Mapper */
MapperInit = Map193_Init;
/* Write to Mapper */
MapperWrite = Map0_Write;
/* Write to SRAM */
MapperSram = Map193_Sram;
/* Write to APU */
MapperApu = Map0_Apu;
/* Read from APU */
MapperReadApu = Map0_ReadApu;
/* Callback at VSync */
MapperVSync = Map0_VSync;
/* Callback at HSync */
MapperHSync = Map0_HSync;
/* Callback at PPU */
MapperPPU = Map0_PPU;
/* Callback at Rendering Screen ( 1:BG, 0:Sprite ) */
MapperRenderScreen = Map0_RenderScreen;
/* Set SRAM Banks */
SRAMBANK = SRAM;
/* Set ROM Banks */
ROMBANK0 = ROMPAGE( (NesHeader.byRomSize<<1) - 4 );
ROMBANK1 = ROMPAGE( (NesHeader.byRomSize<<1) - 3 );
ROMBANK2 = ROMPAGE( (NesHeader.byRomSize<<1) - 2 );
ROMBANK3 = ROMPAGE( (NesHeader.byRomSize<<1) - 1 );
/* Set PPU Banks */
if ( NesHeader.byVRomSize > 0 ) {
for ( nPage = 0; nPage < 8; ++nPage )
PPUBANK[ nPage ] = VROMPAGE( nPage );
InfoNES_SetupChr();
}
/* Set up wiring of the interrupt pin */
K6502_Set_Int_Wiring( 1, 1 );
}
/*-------------------------------------------------------------------*/
void Map134_Apu( word wAddr, byte byData )
{
switch( wAddr & 0x4101 ) {
case 0x4100:
Map134_Cmd = byData & 0x07;
break;
case 0x4101:
switch( Map134_Cmd ) {
case 0:
Map134_Prg = 0;
Map134_Chr = 3;
break;
case 4:
Map134_Chr &= 0x3;
Map134_Chr |= (byData & 0x07) << 2;
break;
case 5:
Map134_Prg = byData & 0x07;
break;
case 6:
Map134_Chr &= 0x1C;
Map134_Chr |= byData & 0x3;
break;
case 7:
if( byData & 0x01 ) NESCore_Mirroring( 0 );
else NESCore_Mirroring( 1 );
break;
}
break;
}
/* Set ROM Banks */
W.ROMBANK0 = ROMPAGE( ((Map134_Prg<<2) + 0 ) % (S.NesHeader.ROMSize << 1) );
W.ROMBANK1 = ROMPAGE( ((Map134_Prg<<2) + 1 ) % (S.NesHeader.ROMSize << 1) );
W.ROMBANK2 = ROMPAGE( ((Map134_Prg<<2) + 2 ) % (S.NesHeader.ROMSize << 1) );
W.ROMBANK3 = ROMPAGE( ((Map134_Prg<<2) + 3 ) % (S.NesHeader.ROMSize << 1) );
/* Set PPU Banks */
W.PPUBANK[0] = VROMPAGE( ((Map134_Chr<<3) + 0) % (S.NesHeader.VROMSize << 3) );
W.PPUBANK[1] = VROMPAGE( ((Map134_Chr<<3) + 1) % (S.NesHeader.VROMSize << 3) );
W.PPUBANK[2] = VROMPAGE( ((Map134_Chr<<3) + 2) % (S.NesHeader.VROMSize << 3) );
W.PPUBANK[3] = VROMPAGE( ((Map134_Chr<<3) + 3) % (S.NesHeader.VROMSize << 3) );
W.PPUBANK[4] = VROMPAGE( ((Map134_Chr<<3) + 4) % (S.NesHeader.VROMSize << 3) );
W.PPUBANK[5] = VROMPAGE( ((Map134_Chr<<3) + 5) % (S.NesHeader.VROMSize << 3) );
W.PPUBANK[6] = VROMPAGE( ((Map134_Chr<<3) + 6) % (S.NesHeader.VROMSize << 3) );
W.PPUBANK[7] = VROMPAGE( ((Map134_Chr<<3) + 7) % (S.NesHeader.VROMSize << 3) );
NESCore_Develop_Character_Data();
//Map134_Wram[wAddr & 0x1fff] = byData;
}
/*-------------------------------------------------------------------*/
void Map248_Set_CPU_Banks()
{
if( Map248_Reg[0] & 0x40 ) {
ROMBANK0 = ROMLASTPAGE( 1 );
ROMBANK1 = ROMPAGE(Map248_Prg1 % (NesHeader.byRomSize<<1));
ROMBANK2 = ROMPAGE(Map248_Prg0 % (NesHeader.byRomSize<<1));
ROMBANK3 = ROMLASTPAGE( 0 );
} else {
ROMBANK0 = ROMPAGE(Map248_Prg0 % (NesHeader.byRomSize<<1));
ROMBANK1 = ROMPAGE(Map248_Prg1 % (NesHeader.byRomSize<<1));
ROMBANK2 = ROMLASTPAGE( 1 );
ROMBANK3 = ROMLASTPAGE( 0 );
}
}
/*-------------------------------------------------------------------*/
void Map248_Set_CPU_Banks()
{
if( Map248_Reg[0] & 0x40 ) {
W.ROMBANK0 = ROMLASTPAGE( 1 );
W.ROMBANK1 = ROMPAGE(Map248_Prg1 % (S.NesHeader.ROMSize<<1));
W.ROMBANK2 = ROMPAGE(Map248_Prg0 % (S.NesHeader.ROMSize<<1));
W.ROMBANK3 = ROMLASTPAGE( 0 );
} else {
W.ROMBANK0 = ROMPAGE(Map248_Prg0 % (S.NesHeader.ROMSize<<1));
W.ROMBANK1 = ROMPAGE(Map248_Prg1 % (S.NesHeader.ROMSize<<1));
W.ROMBANK2 = ROMLASTPAGE( 1 );
W.ROMBANK3 = ROMLASTPAGE( 0 );
}
}
/*-------------------------------------------------------------------*/
void Map251_Init()
{
/* Initialize Mapper */
MapperInit = Map251_Init;
/* Write to Mapper */
MapperWrite = Map251_Write;
/* Write to SRAM */
MapperSram = Map251_Sram;
/* Write to APU */
MapperApu = Map0_Apu;
/* Read from APU */
MapperReadApu = Map0_ReadApu;
/* Callback at VSync */
MapperVSync = Map0_VSync;
/* Callback at HSync */
MapperHSync = Map0_HSync;
/* Callback at PPU */
MapperPPU = Map0_PPU;
/* Callback at Rendering Screen ( 1:BG, 0:Sprite ) */
MapperRenderScreen = Map0_RenderScreen;
/* Set SRAM Banks */
SRAMBANK = SRAM;
/* Set ROM Banks */
ROMBANK0 = ROMPAGE( 0 );
ROMBANK1 = ROMPAGE( 1 );
ROMBANK2 = ROMLASTPAGE( 1 );
ROMBANK3 = ROMLASTPAGE( 0 );
/* Set Registers */
InfoNES_Mirroring( 1 );
int i;
for( i = 0; i < 11; i++ )
Map251_Reg[i] = 0;
for( i = 0; i < 4; i++ )
Map251_Breg[i] = 0;
/* Set up wiring of the interrupt pin */
K6502_Set_Int_Wiring( 1, 1 );
}
/*-------------------------------------------------------------------*/
void Map134_Apu( WORD wAddr, BYTE byData )
{
switch( wAddr & 0x4101 ) {
case 0x4100:
Map134_Cmd = byData & 0x07;
break;
case 0x4101:
switch( Map134_Cmd ) {
case 0:
Map134_Prg = 0;
Map134_Chr = 3;
break;
case 4:
Map134_Chr &= 0x3;
Map134_Chr |= (byData & 0x07) << 2;
break;
case 5:
Map134_Prg = byData & 0x07;
break;
case 6:
Map134_Chr &= 0x1C;
Map134_Chr |= byData & 0x3;
break;
case 7:
if( byData & 0x01 ) InfoNES_Mirroring( 0 );
else InfoNES_Mirroring( 1 );
break;
}
break;
}
/* Set ROM Banks */
ROMBANK0 = ROMPAGE( ((Map134_Prg<<2) + 0 ) % (NesHeader.byRomSize << 1) );
ROMBANK1 = ROMPAGE( ((Map134_Prg<<2) + 1 ) % (NesHeader.byRomSize << 1) );
ROMBANK2 = ROMPAGE( ((Map134_Prg<<2) + 2 ) % (NesHeader.byRomSize << 1) );
ROMBANK3 = ROMPAGE( ((Map134_Prg<<2) + 3 ) % (NesHeader.byRomSize << 1) );
/* Set PPU Banks */
PPUBANK[ 0 ] = VROMPAGE( ((Map134_Chr<<3) + 0) % (NesHeader.byVRomSize << 3) );
PPUBANK[ 1 ] = VROMPAGE( ((Map134_Chr<<3) + 1) % (NesHeader.byVRomSize << 3) );
PPUBANK[ 2 ] = VROMPAGE( ((Map134_Chr<<3) + 2) % (NesHeader.byVRomSize << 3) );
PPUBANK[ 3 ] = VROMPAGE( ((Map134_Chr<<3) + 3) % (NesHeader.byVRomSize << 3) );
PPUBANK[ 4 ] = VROMPAGE( ((Map134_Chr<<3) + 4) % (NesHeader.byVRomSize << 3) );
PPUBANK[ 5 ] = VROMPAGE( ((Map134_Chr<<3) + 5) % (NesHeader.byVRomSize << 3) );
PPUBANK[ 6 ] = VROMPAGE( ((Map134_Chr<<3) + 6) % (NesHeader.byVRomSize << 3) );
PPUBANK[ 7 ] = VROMPAGE( ((Map134_Chr<<3) + 7) % (NesHeader.byVRomSize << 3) );
InfoNES_SetupChr();
//Map134_Wram[ wAddr & 0x1fff ] = byData;
}
/*-------------------------------------------------------------------*/
void Map243_Apu( WORD wAddr, BYTE byData )
{
if ( wAddr == 0x4100 )
{
Map243_Regs[0] = byData;
}
else if ( wAddr == 0x4101 )
{
switch ( Map243_Regs[0] & 0x07 )
{
case 0x02:
Map243_Regs[1] = byData & 0x01;
break;
case 0x00:
case 0x04:
case 0x07:
Map243_Regs[2] = ( byData & 0x01 ) << 1;
break;
/* Set ROM Banks */
case 0x05:
ROMBANK0 = ROMPAGE( ( byData * 4 + 0 ) % ( NesHeader.byRomSize << 1 ) );
ROMBANK1 = ROMPAGE( ( byData * 4 + 1 ) % ( NesHeader.byRomSize << 1 ) );
ROMBANK2 = ROMPAGE( ( byData * 4 + 2 ) % ( NesHeader.byRomSize << 1 ) );
ROMBANK3 = ROMPAGE( ( byData * 4 + 3 ) % ( NesHeader.byRomSize << 1 ) );
break;
case 0x06:
Map243_Regs[3] = ( byData & 0x03 ) << 2;
break;
}
/* Set PPU Banks */
if ( ( NesHeader.byVRomSize << 3 ) <= 64 )
{
BYTE chr_bank = ( Map243_Regs[2] + Map243_Regs[3] ) >> 1;
PPUBANK[ 0 ] = VROMPAGE( ( chr_bank * 8 + 0 ) % ( NesHeader.byVRomSize << 3 ) );
PPUBANK[ 1 ] = VROMPAGE( ( chr_bank * 8 + 1 ) % ( NesHeader.byVRomSize << 3 ) );
PPUBANK[ 2 ] = VROMPAGE( ( chr_bank * 8 + 2 ) % ( NesHeader.byVRomSize << 3 ) );
PPUBANK[ 3 ] = VROMPAGE( ( chr_bank * 8 + 3 ) % ( NesHeader.byVRomSize << 3 ) );
PPUBANK[ 4 ] = VROMPAGE( ( chr_bank * 8 + 4 ) % ( NesHeader.byVRomSize << 3 ) );
PPUBANK[ 5 ] = VROMPAGE( ( chr_bank * 8 + 5 ) % ( NesHeader.byVRomSize << 3 ) );
PPUBANK[ 6 ] = VROMPAGE( ( chr_bank * 8 + 6 ) % ( NesHeader.byVRomSize << 3 ) );
PPUBANK[ 7 ] = VROMPAGE( ( chr_bank * 8 + 7 ) % ( NesHeader.byVRomSize << 3 ) );
InfoNES_SetupChr();
}
else
{
/*-------------------------------------------------------------------*/
void Map188_Write( WORD wAddr, BYTE byData )
{
/* Set ROM Banks */
if ( byData )
{
if ( byData & 0x10 )
{
byData = ( byData & 0x07 ) << 1;
ROMBANK0 = ROMPAGE( ( byData + 0 ) % ( NesHeader.byRomSize << 1 ) );
ROMBANK1 = ROMPAGE( ( byData + 1 ) % ( NesHeader.byRomSize << 1 ) );
} else {
byData <<= 1;
ROMBANK0 = ROMPAGE( ( byData + 16 ) % ( NesHeader.byRomSize << 1 ) );
ROMBANK1 = ROMPAGE( ( byData + 17 ) % ( NesHeader.byRomSize << 1 ) );
}
}
else
{
if ( ( NesHeader.byRomSize << 1 ) == 0x10 )
{
ROMBANK0 = ROMPAGE( 14 );
ROMBANK1 = ROMPAGE( 15 );
} else {
ROMBANK0 = ROMPAGE( 16 );
ROMBANK1 = ROMPAGE( 17 );
}
}
}
/*-------------------------------------------------------------------*/
void Map185_Init()
{
int nPage;
/* Initialize Mapper */
MapperInit = Map185_Init;
/* Write to Mapper */
MapperWrite = Map185_Write;
/* Write to SRAM */
MapperSram = Map0_Sram;
/* Write to APU */
MapperApu = Map0_Apu;
/* Read from APU */
MapperReadApu = Map0_ReadApu;
/* Callback at VSync */
MapperVSync = Map0_VSync;
/* Callback at HSync */
MapperHSync = Map0_HSync;
/* Callback at PPU */
MapperPPU = Map0_PPU;
/* Callback at Rendering Screen ( 1:BG, 0:Sprite ) */
MapperRenderScreen = Map0_RenderScreen;
/* Set SRAM Banks */
SRAMBANK = SRAM;
/* Set ROM Banks */
ROMBANK0 = ROMPAGE( 0 );
ROMBANK1 = ROMPAGE( 1 );
ROMBANK2 = ROMPAGE( 2 );
ROMBANK3 = ROMPAGE( 3 );
/* Initialize Dummy VROM */
for ( nPage = 0; nPage < 0x400; nPage++ )
{
Map185_Dummy_Chr_Rom[ nPage ] = 0xff;
}
/* Set up wiring of the interrupt pin */
K6502_Set_Int_Wiring( 1, 1 );
}
/*-------------------------------------------------------------------*/
void Map114_Set_CPU_Banks()
{
if ( Map114_Prg_Swap() )
{
ROMBANK0 = ROMLASTPAGE( 1 );
ROMBANK1 = ROMPAGE( Map114_Prg1 % ( NesHeader.byRomSize << 1 ) );
ROMBANK2 = ROMPAGE( Map114_Prg0 % ( NesHeader.byRomSize << 1 ) );
ROMBANK3 = ROMLASTPAGE( 0 );
} else {
ROMBANK0 = ROMPAGE( Map114_Prg0 % ( NesHeader.byRomSize << 1 ) );
ROMBANK1 = ROMPAGE( Map114_Prg1 % ( NesHeader.byRomSize << 1 ) );
ROMBANK2 = ROMLASTPAGE( 1 );
ROMBANK3 = ROMLASTPAGE( 0 );
}
}
void Map7_Write( word wAddr, byte bData )
{
byte byBank;
/* Set ROM Banks */
byBank = ( bData & 0x07 ) << 2;
byBank %= ( S.NesHeader.ROMSize << 1 );
W.ROMBANK0 = ROMPAGE( byBank );
W.ROMBANK1 = ROMPAGE( byBank + 1 );
W.ROMBANK2 = ROMPAGE( byBank + 2 );
W.ROMBANK3 = ROMPAGE( byBank + 3 );
NESCore_Mirroring( bData & 0x10 ? 2 : 3 );
}
/*-------------------------------------------------------------------*/
void Map235_Init()
{
int i;
/* Initialize Mapper */
MapperInit = Map235_Init;
/* Write to Mapper */
MapperWrite = Map235_Write;
/* Write to SRAM */
MapperSram = Map0_Sram;
/* Write to APU */
MapperApu = Map0_Apu;
/* Read from APU */
MapperReadApu = Map0_ReadApu;
/* Callback at VSync */
MapperVSync = Map0_VSync;
/* Callback at HSync */
MapperHSync = Map0_HSync;
/* Callback at PPU */
MapperPPU = Map0_PPU;
/* Callback at Rendering Screen ( 1:BG, 0:Sprite ) */
MapperRenderScreen = Map0_RenderScreen;
/* Set SRAM Banks */
SRAMBANK = SRAM;
/* Set Registers */
for( i = 0; i < 0x2000; i++ ) {
DRAM[i] = 0xFF;
}
/* Set ROM Banks */
ROMBANK0 = ROMPAGE( 0 );
ROMBANK1 = ROMPAGE( 1 );
ROMBANK2 = ROMPAGE( 2 );
ROMBANK3 = ROMPAGE( 3 );
/* Set up wiring of the interrupt pin */
K6502_Set_Int_Wiring( 1, 1 );
}
/*-------------------------------------------------------------------*/
void Map135_Init()
{
/* Initialize Mapper */
MapperInit = Map135_Init;
/* Write to Mapper */
MapperWrite = Map0_Write;
/* Write to SRAM */
MapperSram = Map0_Sram;
/* Write to APU */
MapperApu = Map135_Apu;
/* Read from APU */
MapperReadApu = Map0_ReadApu;
/* Callback at VSync */
MapperVSync = Map0_VSync;
/* Callback at HSync */
MapperHSync = Map0_HSync;
/* Callback at PPU */
MapperPPU = Map0_PPU;
/* Callback at Rendering Screen ( 1:BG, 0:Sprite ) */
MapperRenderScreen = Map0_RenderScreen;
/* Set SRAM Banks */
W.SRAMBANK = S.SRAM;
/* Initialize Registers */
Map135_Cmd = 0;
Map135_Chr0l = Map135_Chr1l = Map135_Chr0h = Map135_Chr1h = Map135_Chrch = 0;
/* Set ROM Banks */
W.ROMBANK0 = ROMPAGE( 0 );
W.ROMBANK1 = ROMPAGE( 1 );
W.ROMBANK2 = ROMPAGE( 2 );
W.ROMBANK3 = ROMPAGE( 3 );
/* Set PPU Banks */
Map135_Set_PPU_Banks();
}
/*-------------------------------------------------------------------*/
void Map7_Write( WORD wAddr, BYTE byData )
{
BYTE byBank;
/* Set ROM Banks */
byBank = ( byData & 0x07 ) << 2;
byBank %= ( NesHeader.byRomSize << 1 );
ROMBANK0 = ROMPAGE( byBank );
ROMBANK1 = ROMPAGE( byBank + 1 );
ROMBANK2 = ROMPAGE( byBank + 2 );
ROMBANK3 = ROMPAGE( byBank + 3 );
/* Name Table Mirroring */
InfoNES_Mirroring( byData & 0x10 ? 2 : 3 );
}
void Map4_Set_CPU_Banks()
{
if (Map4_Prg_Swap())
{
W.ROMBANK0 = ROMLASTPAGE( 1 );
W.ROMBANK1 = ROMPAGE( MS4.Prg1 % ( S.NesHeader.ROMSize << 1 ) );
W.ROMBANK2 = ROMPAGE( MS4.Prg0 % ( S.NesHeader.ROMSize << 1 ) );
W.ROMBANK3 = ROMLASTPAGE( 0 );
} else {
W.ROMBANK0 = ROMPAGE( MS4.Prg0 % ( S.NesHeader.ROMSize << 1 ) );
W.ROMBANK1 = ROMPAGE( MS4.Prg1 % ( S.NesHeader.ROMSize << 1 ) );
W.ROMBANK2 = ROMLASTPAGE( 1 );
W.ROMBANK3 = ROMLASTPAGE( 0 );
}
}
void Map42_Write( word wAddr, byte byData )
{
switch ( wAddr & 0xe003 )
{
/* Set ROM Banks */
case 0xe000:
W.SRAMBANK = ROMPAGE( ( byData & 0x0f ) % ( S.NesHeader.ROMSize << 1 ) );
break;
case 0xe001:
if ( byData & 0x08 )
{
NESCore_Mirroring( 0 );
} else {
NESCore_Mirroring( 1 );
}
break;
case 0xe002:
if ( byData & 0x02 )
{
Map42_IRQ_Enable = 1;
} else {
Map42_IRQ_Enable = 0;
Map42_IRQ_Cnt = 0;
}
break;
}
}
void Map42_Init()
{
MapperInit = Map42_Init;
MapperWrite = Map42_Write;
MapperSram = Map0_Sram;
MapperApu = Map0_Apu;
MapperReadApu = Map0_ReadApu;
MapperVSync = Map0_VSync;
MapperHSync = Map42_HSync;
MapperPPU = Map0_PPU;
/* Callback at Rendering Screen ( 1:BG, 0:Sprite ) */
MapperRenderScreen = Map0_RenderScreen;
W.SRAMBANK = ROMPAGE( 0 );
W.ROMBANK0 = ROMLASTPAGE( 3 );
W.ROMBANK1 = ROMLASTPAGE( 2 );
W.ROMBANK2 = ROMLASTPAGE( 1 );
W.ROMBANK3 = ROMLASTPAGE( 0 );
/* Set PPU Banks */
if ( S.NesHeader.VROMSize > 0 )
{
int nPage ;
for (nPage = 0; nPage < 8; ++nPage )
W.PPUBANK[nPage] = VROMPAGE( nPage );
NESCore_Develop_Character_Data();
}
}
/*-------------------------------------------------------------------*/
void Map42_Write( WORD wAddr, BYTE byData )
{
switch ( wAddr & 0xe003 )
{
/* Set ROM Banks */
case 0xe000:
SRAMBANK = ROMPAGE( ( byData & 0x0f ) % ( NesHeader.byRomSize << 1 ) );
break;
case 0xe001:
if ( byData & 0x08 )
{
InfoNES_Mirroring( 0 );
} else {
InfoNES_Mirroring( 1 );
}
break;
case 0xe002:
if ( byData & 0x02 )
{
Map42_IRQ_Enable = 1;
} else {
Map42_IRQ_Enable = 0;
Map42_IRQ_Cnt = 0;
}
break;
}
}
/*-------------------------------------------------------------------*/
void Map109_Apu( WORD wAddr, BYTE byData )
{
switch( wAddr ) {
case 0x4100:
Map109_Reg = byData;
break;
case 0x4101:
switch( Map109_Reg ) {
case 0:
Map109_Chr0 = byData;
Map109_Set_PPU_Banks();
break;
case 1:
Map109_Chr1 = byData;
Map109_Set_PPU_Banks();
break;
case 2:
Map109_Chr2 = byData;
Map109_Set_PPU_Banks();
break;
case 3:
Map109_Chr3 = byData;
Map109_Set_PPU_Banks();
break;
case 4:
Map109_Chrmode0 = byData & 0x01;
Map109_Set_PPU_Banks();
break;
case 5:
ROMBANK0 = ROMPAGE( ( ( byData & 0x07 ) + 0 ) % ( NesHeader.byRomSize << 1 ) );
ROMBANK1 = ROMPAGE( ( ( byData & 0x07 ) + 1 ) % ( NesHeader.byRomSize << 1 ) );
ROMBANK2 = ROMPAGE( ( ( byData & 0x07 ) + 2 ) % ( NesHeader.byRomSize << 1 ) );
ROMBANK3 = ROMPAGE( ( ( byData & 0x07 ) + 3 ) % ( NesHeader.byRomSize << 1 ) );
break;
case 6:
Map109_Chrmode1 = byData & 0x07;
Map109_Set_PPU_Banks();
break;
case 7:
if( byData & 0x01 ) InfoNES_Mirroring( 0 );
else InfoNES_Mirroring( 1 );
break;
}
break;
}
}
void Map45_Set_CPU_Bank7(byte byData)
{
byData &= (Map45_Regs[3] & 0x3F) ^ 0xFF;
byData &= 0x3F;
byData |= Map45_Regs[1];
W.ROMBANK3 = ROMPAGE( byData % ( S.NesHeader.ROMSize << 1) );
Map45_P[3] = byData;
}
void Map45_Set_CPU_Bank7(BYTE byData)
{
byData &= (Map45_Regs[3] & 0x3F) ^ 0xFF;
byData &= 0x3F;
byData |= Map45_Regs[1];
ROMBANK3 = ROMPAGE( byData % ( NesHeader.byRomSize << 1) );
Map45_P[3] = byData;
}
/*-------------------------------------------------------------------*/
void Map232_Init()
{
/* Initialize Mapper */
MapperInit = Map232_Init;
/* Write to Mapper */
MapperWrite = Map232_Write;
/* Write to SRAM */
MapperSram = Map0_Sram;
/* Write to APU */
MapperApu = Map0_Apu;
/* Read from APU */
MapperReadApu = Map0_ReadApu;
/* Callback at VSync */
MapperVSync = Map0_VSync;
/* Callback at HSync */
MapperHSync = Map0_HSync;
/* Callback at PPU */
MapperPPU = Map0_PPU;
/* Callback at Rendering Screen ( 1:BG, 0:Sprite ) */
MapperRenderScreen = Map0_RenderScreen;
/* Set SRAM Banks */
SRAMBANK = SRAM;
/* Set ROM Banks */
ROMBANK0 = ROMPAGE( 0 );
ROMBANK1 = ROMPAGE( 1 );
ROMBANK2 = ROMLASTPAGE( 1 );
ROMBANK3 = ROMLASTPAGE( 0 );
/* Initialize Registers */
Map232_Regs[0] = 0x0C;
Map232_Regs[1] = 0x00;
/* Set up wiring of the interrupt pin */
K6502_Set_Int_Wiring( 1, 1 );
}
/*-------------------------------------------------------------------*/
void Map222_Write( WORD wAddr, BYTE byData )
{
switch( wAddr & 0xF003 ) {
case 0x8000:
ROMBANK0 = ROMPAGE( byData % ( NesHeader.byRomSize << 1 ) );
break;
case 0xA000:
ROMBANK1 = ROMPAGE( byData % ( NesHeader.byRomSize << 1 ) );
break;
case 0xB000:
PPUBANK[ 0 ] = VROMPAGE( byData % ( NesHeader.byVRomSize << 3 ) );
InfoNES_SetupChr();
break;
case 0xB002:
PPUBANK[ 1 ] = VROMPAGE( byData % ( NesHeader.byVRomSize << 3 ) );
InfoNES_SetupChr();
break;
case 0xC000:
PPUBANK[ 2 ] = VROMPAGE( byData % ( NesHeader.byVRomSize << 3 ) );
InfoNES_SetupChr();
break;
case 0xC002:
PPUBANK[ 3 ] = VROMPAGE( byData % ( NesHeader.byVRomSize << 3 ) );
InfoNES_SetupChr();
break;
case 0xD000:
PPUBANK[ 4 ] = VROMPAGE( byData % ( NesHeader.byVRomSize << 3 ) );
InfoNES_SetupChr();
break;
case 0xD002:
PPUBANK[ 5 ] = VROMPAGE( byData % ( NesHeader.byVRomSize << 3 ) );
InfoNES_SetupChr();
break;
case 0xE000:
PPUBANK[ 6 ] = VROMPAGE( byData % ( NesHeader.byVRomSize << 3 ) );
InfoNES_SetupChr();
break;
case 0xE002:
PPUBANK[ 7 ] = VROMPAGE( byData % ( NesHeader.byVRomSize << 3 ) );
InfoNES_SetupChr();
break;
}
}
