/*
* The dce irqs are not acked by the rlc (block in charge of irq management).
* It seems the rlc block does not have xrbm access (the block in charge of
* register management).
* Then those irqs must be acked manually by the CPU.
* This is called in hard interrupt context, it does not lock the dce.
*/
void dce4_irqs_ack(struct dce4 *dce)
{
u32 disps[CRTCS_N_MAX];
u32 grphs[CRTCS_N_MAX];
unsigned i;
u32 tmp;
for (i = 0; i < dce->ddev.crtcs_n; ++i)
disps[i] = RR32(regs_disp_int_status[i]);
for (i = 0; i < dce->ddev.crtcs_n; ++i)
grphs[i] = RR32(regs_crtc_grph_int_status[i]);
/* XXX: obsolete page flipping */
for (i = 0; i < dce->ddev.crtcs_n; ++i)
if (grphs[i] & GRPH_PFLIP_INT_OCCURRED)
WR32(GRPH_PFLIP_INT_CLR, regs_crtc_grph_int_status[i]);
for (i = 0; i < dce->ddev.crtcs_n; ++i) {
if (disps[i] & vals_lb_d_vblank_int[i])
WR32(VBLANK_ACK, regs_crtc_vblank_status[i]);
if (disps[i] & vals_lb_d_vline_int[i])
WR32(VLINE_ACK, regs_crtc_vline_status[i]);
}
for (i = 0; i < HPDS_N; ++i)
if (disps[i] & vals_hpd_int[i]) {
tmp = RR32(regs_hpd_int_ctl[i]);
tmp |= HPDx_INT_CTL_INT_ACK;
WR32(tmp, regs_hpd_int_ctl[i]);
}
}
void speck_decrypt32(SPECK_TYPE32 const ct[2], SPECK_TYPE32 pt[2], SPECK_TYPE32 const K[SPECK_ROUNDS32])
{
SPECK_TYPE32 i;
pt[0] = ct[0]; pt[1] = ct[1];
for (i = 0; i < SPECK_ROUNDS32; i++){
RR32(pt[1], pt[0], K[(SPECK_ROUNDS32 - 1) - i]);
}
}
void dce4_vga_off(struct dce4 *dce)
{
unsigned i;
WR32(VGA_MEM_DIS, VGA_HDP_CTL);
WR32(RR32(VGA_RENDER_CTL) & VGA_VSTATUS_CTL_CLR, VGA_RENDER_CTL);
for (i = 0; i < dce->ddev.crtcs_n; ++i)
WR32(0, regs_vga_ctl[i]);
}
void dce6_vga_off(struct dce6 *dce)
{
u8 i;
/* lockout access to vga mem through hdp */
WR32(VHC_VGA_MEM_DIS, VGA_HDP_CTL);
WR32(RR32(VGA_RENDER_CTL) & VRC_VGA_VSTATUS_CTL_CLR, VGA_RENDER_CTL);
for (i = 0; i < dce->ddev.crtcs_n; ++i)
WR32(0, regs_vga_ctl[i]);
}
