Пример #1
0
static void rtl8169_hw_start(struct eth_device *dev)
{
	u32 i;

#ifdef DEBUG_RTL8169
	int stime = currticks();
	printf ("%s\n", __FUNCTION__);
#endif

#if 0
	/* Soft reset the chip. */
	RTL_W8(ChipCmd, CmdReset);

	/* Check that the chip has finished the reset. */
	for (i = 1000; i > 0; i--) {
		if ((RTL_R8(ChipCmd) & CmdReset) == 0)
			break;
		else
			udelay(10);
	}
#endif

	RTL_W8(Cfg9346, Cfg9346_Unlock);
	RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
	RTL_W8(EarlyTxThres, EarlyTxThld);

	/* For gigabit rtl8169 */
	RTL_W16(RxMaxSize, RxPacketMaxSize);

	/* Set Rx Config register */
	i = rtl8169_rx_config | (RTL_R32(RxConfig) &
				 rtl_chip_info[tpc->chipset].RxConfigMask);
	RTL_W32(RxConfig, i);

	/* Set DMA burst size and Interframe Gap Time */
	RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
				(InterFrameGap << TxInterFrameGapShift));


	tpc->cur_rx = 0;

	RTL_W32(TxDescStartAddr, (unsigned long)tpc->TxDescArray);
	RTL_W32(RxDescStartAddr, (unsigned long)tpc->RxDescArray);
	RTL_W8(Cfg9346, Cfg9346_Lock);
	udelay(10);

	RTL_W32(RxMissed, 0);

	rtl8169_set_rx_mode(dev);

	/* no early-rx interrupts */
	RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);

#ifdef DEBUG_RTL8169
	printf ("%s elapsed time : %d\n", __FUNCTION__, currticks()-stime);
#endif
}
Пример #2
0
/* The interrupt handler does all of the Rx thread work and cleans up after the Tx thread. */
static irqreturn_t
rtl8169_interrupt(int irq, void *dev_instance, struct pt_regs *regs)
{
    struct net_device *dev = (struct net_device *) dev_instance;
    struct rtl8169_private *tp = dev->priv;
    int boguscnt = max_interrupt_work;
    void *ioaddr = tp->mmio_addr;
    int status = 0;
    int handled = 0;

    do {
        status = RTL_R16(IntrStatus);

        /* hotplug/major error/no more work/shared irq */
        if ((status == 0xFFFF) || !status)
            break;

        handled = 1;
        /*
        		if (status & RxUnderrun)
        			link_changed = RTL_R16 (CSCR) & CSCR_LinkChangeBit;
        */
        RTL_W16(IntrStatus,
                (status & RxFIFOOver) ? (status | RxOverflow) : status);

        if (!(status & rtl8169_intr_mask))
            break;

        // Rx interrupt
        if (status & (RxOK | RxUnderrun | RxOverflow | RxFIFOOver)) {
            rtl8169_rx_interrupt(dev, tp, ioaddr);
        }
        // Tx interrupt
        if (status & (TxOK | TxErr)) {
            spin_lock(&tp->lock);
            rtl8169_tx_interrupt(dev, tp, ioaddr);
            spin_unlock(&tp->lock);
        }

        boguscnt--;
    } while (boguscnt > 0);

    if (boguscnt <= 0) {
        printk(KERN_WARNING "%s: Too much work at interrupt!\n",
               dev->name);
        /* Clear all interrupt sources. */
        RTL_W16(IntrStatus, 0xffff);
    }
    return IRQ_RETVAL(handled);
}
Пример #3
0
/**************************************************************************
HALT - Turn off ethernet interface
***************************************************************************/
static void rtl_halt(struct eth_device *dev)
{
	int i;

#ifdef DEBUG_RTL8169
	printf ("%s\n", __FUNCTION__);
#endif

	ioaddr = dev->iobase;

	/* Stop the chip's Tx and Rx DMA processes. */
	RTL_W8(ChipCmd, 0x00);

	/* Disable interrupts by clearing the interrupt mask. */
	RTL_W16(IntrMask, 0x0000);

	RTL_W32(RxMissed, 0);

	tpc->TxDescArrays = NULL;
	tpc->RxDescArrays = NULL;
	tpc->TxDescArray = NULL;
	tpc->RxDescArray = NULL;
	for (i = 0; i < NUM_RX_DESC; i++) {
		tpc->RxBufferRing[i] = NULL;
	}
}
Пример #4
0
static void
rtl8169_tx_timeout(struct net_device *dev)
{
    struct rtl8169_private *tp = dev->priv;
    void *ioaddr = tp->mmio_addr;
    u8 tmp8;

    /* disable Tx, if not already */
    tmp8 = RTL_R8(ChipCmd);
    if (tmp8 & CmdTxEnb)
        RTL_W8(ChipCmd, tmp8 & ~CmdTxEnb);

    /* Disable interrupts by clearing the interrupt mask. */
    RTL_W16(IntrMask, 0x0000);

    /* Stop a shared interrupt from scavenging while we are. */
    spin_lock_irq(&tp->lock);
    rtl8169_tx_clear(tp);
    spin_unlock_irq(&tp->lock);

    /* ...and finally, reset everything */
    rtl8169_hw_start(dev);

    netif_wake_queue(dev);
}
Пример #5
0
static int rtl8169_suspend(struct pci_dev *pdev, u32 state)
{
    struct net_device *dev = pci_get_drvdata(pdev);
    struct rtl8169_private *tp = dev->priv;
    void *ioaddr = tp->mmio_addr;
    unsigned long flags;

    if (!netif_running(dev))
        return 0;

    netif_device_detach(dev);
    netif_stop_queue(dev);
    spin_lock_irqsave(&tp->lock, flags);

    /* Disable interrupts, stop Rx and Tx */
    RTL_W16(IntrMask, 0);
    RTL_W8(ChipCmd, 0);

    /* Update the error counts. */
    tp->stats.rx_missed_errors += RTL_R32(RxMissed);
    RTL_W32(RxMissed, 0);
    spin_unlock_irqrestore(&tp->lock, flags);

    return 0;
}
Пример #6
0
__inline__ void DMDP_RTL_W16(unsigned int phy, unsigned int reg, unsigned short val16)
{
	struct rtl8192cd_priv *priv;
	//printk("++++++++++++++++++++++++++%s++++++++++++++++++++++++++\n", __FUNCTION__);
	if (phy >= NUM_WLAN_IFACE || phy < 0) {
		printk("%s: phy index[%d] out of bound !!\n", __FUNCTION__, phy);
		return;
	}
	priv = (struct rtl8192cd_priv *)if_priv[phy];
	RTL_W16(reg, val16);
}
Пример #7
0
VOID
ODM_Write2Byte(
	IN 	PDM_ODM_T		pDM_Odm,
	IN	u4Byte			RegAddr,
	IN	u2Byte			Data
	)
{
#if(DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL))
	prtl8192cd_priv	priv	= pDM_Odm->priv;
	RTL_W16(RegAddr, Data);
#elif(DM_ODM_SUPPORT_TYPE & ODM_CE)
	PADAPTER		Adapter = pDM_Odm->Adapter;
	rtw_write16(Adapter,RegAddr, Data);
#elif(DM_ODM_SUPPORT_TYPE & ODM_MP)
	PADAPTER		Adapter = pDM_Odm->Adapter;
	PlatformEFIOWrite2Byte(Adapter, RegAddr, Data);
#endif	

}
void
ODM_Write2Byte(
	PDM_ODM_T		pDM_Odm,
	u32			RegAddr,
	u16			Data
	)
{
#if(DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL))
	prtl8192cd_priv	priv	= pDM_Odm->priv;
	RTL_W16(RegAddr, Data);
#elif(DM_ODM_SUPPORT_TYPE & ODM_CE)
	struct rtw_adapter *		Adapter = pDM_Odm->Adapter;
	rtw_write16(Adapter,RegAddr, Data);
#elif(DM_ODM_SUPPORT_TYPE & ODM_MP)
	struct rtw_adapter *		Adapter = pDM_Odm->Adapter;
	PlatformEFIOWrite2Byte(Adapter, RegAddr, Data);
#endif

}
Пример #9
0
static int
rtl8169_close(struct net_device *dev)
{
    struct rtl8169_private *tp = dev->priv;
    struct pci_dev *pdev = tp->pci_dev;
    void *ioaddr = tp->mmio_addr;

    netif_stop_queue(dev);

    rtl8169_delete_timer(dev);

    spin_lock_irq(&tp->lock);

    /* Stop the chip's Tx and Rx DMA processes. */
    RTL_W8(ChipCmd, 0x00);

    /* Disable interrupts by clearing the interrupt mask. */
    RTL_W16(IntrMask, 0x0000);

    /* Update the error counts. */
    tp->stats.rx_missed_errors += RTL_R32(RxMissed);
    RTL_W32(RxMissed, 0);

    spin_unlock_irq(&tp->lock);

    synchronize_irq(dev->irq);
    free_irq(dev->irq, dev);

    rtl8169_tx_clear(tp);

    rtl8169_rx_clear(tp);

    pci_free_consistent(pdev, R8169_RX_RING_BYTES, tp->RxDescArray,
                        tp->RxPhyAddr);
    pci_free_consistent(pdev, R8169_TX_RING_BYTES, tp->TxDescArray,
                        tp->TxPhyAddr);
    tp->TxDescArray = NULL;
    tp->RxDescArray = NULL;

    return 0;
}
Пример #10
0
static void rtl_halt_common(unsigned long dev_iobase)
{
	int i;

#ifdef DEBUG_RTL8169
	printf ("%s\n", __FUNCTION__);
#endif

	ioaddr = dev_iobase;

	/* Stop the chip's Tx and Rx DMA processes. */
	RTL_W8(ChipCmd, 0x00);

	/* Disable interrupts by clearing the interrupt mask. */
	RTL_W16(IntrMask, 0x0000);

	RTL_W32(RxMissed, 0);

	for (i = 0; i < NUM_RX_DESC; i++) {
		tpc->RxBufferRing[i] = NULL;
	}
}
Пример #11
0
static void rtl8169_hw_start(pci_dev_t dev)
#endif
{
	u32 i;

#ifdef DEBUG_RTL8169
	int stime = currticks();
	printf ("%s\n", __FUNCTION__);
#endif

#if 0
	/* Soft reset the chip. */
	RTL_W8(ChipCmd, CmdReset);

	/* Check that the chip has finished the reset. */
	for (i = 1000; i > 0; i--) {
		if ((RTL_R8(ChipCmd) & CmdReset) == 0)
			break;
		else
			udelay(10);
	}
#endif

	RTL_W8(Cfg9346, Cfg9346_Unlock);

	/* RTL-8169sb/8110sb or previous version */
	if (tpc->chipset <= 5)
		RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);

	RTL_W8(EarlyTxThres, EarlyTxThld);

	/* For gigabit rtl8169 */
	RTL_W16(RxMaxSize, RxPacketMaxSize);

	/* Set Rx Config register */
	i = rtl8169_rx_config | (RTL_R32(RxConfig) &
				 rtl_chip_info[tpc->chipset].RxConfigMask);
	RTL_W32(RxConfig, i);

	/* Set DMA burst size and Interframe Gap Time */
	RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
				(InterFrameGap << TxInterFrameGapShift));


	tpc->cur_rx = 0;

#ifdef CONFIG_DM_ETH
	RTL_W32(TxDescStartAddrLow, dm_pci_mem_to_phys(dev,
			(pci_addr_t)(unsigned long)tpc->TxDescArray));
#else
	RTL_W32(TxDescStartAddrLow, pci_mem_to_phys(dev,
			(pci_addr_t)(unsigned long)tpc->TxDescArray));
#endif
	RTL_W32(TxDescStartAddrHigh, (unsigned long)0);
#ifdef CONFIG_DM_ETH
	RTL_W32(RxDescStartAddrLow, dm_pci_mem_to_phys(
			dev, (pci_addr_t)(unsigned long)tpc->RxDescArray));
#else
	RTL_W32(RxDescStartAddrLow, pci_mem_to_phys(
			dev, (pci_addr_t)(unsigned long)tpc->RxDescArray));
#endif
	RTL_W32(RxDescStartAddrHigh, (unsigned long)0);

	/* RTL-8169sc/8110sc or later version */
	if (tpc->chipset > 5)
		RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);

	RTL_W8(Cfg9346, Cfg9346_Lock);
	udelay(10);

	RTL_W32(RxMissed, 0);

	rtl8169_set_rx_mode();

	/* no early-rx interrupts */
	RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);

#ifdef DEBUG_RTL8169
	printf("%s elapsed time : %lu\n", __func__, currticks()-stime);
#endif
}
Пример #12
0
int ARFBRefresh(struct rtl8192cd_priv *priv, PSTATION_RA_INFO  pRaInfo)
{  // Wilson 2011/10/26
	unsigned int MaskFromReg;
	unsigned char i,j;

	// Test for Wilson
	RTL_W16(REG_88E_TXRPT_TIM, DefaultTxRPTTiming);  //200ms
	RTL_W32(DARFRC, 0x04020100);
	RTL_W32(DARFRC+4, 0x0a080706);

	switch(pRaInfo->RateID) {
	case RATR_INX_WIRELESS_NGB:
		pRaInfo->RAUseRate=(pRaInfo->RateMask)&0x0f8ff015;
		break;
	case RATR_INX_WIRELESS_NG:
		pRaInfo->RAUseRate=(pRaInfo->RateMask)&0x0f8ff010;
		break;
	case RATR_INX_WIRELESS_NB:
		pRaInfo->RAUseRate=(pRaInfo->RateMask)&0x0f8ff005;
		break;
	case RATR_INX_WIRELESS_N:
		pRaInfo->RAUseRate=(pRaInfo->RateMask)&0x0f8ff000;
		break;
	case RATR_INX_WIRELESS_GB:
		pRaInfo->RAUseRate=(pRaInfo->RateMask)&0x00000ff5;
		break;
	case RATR_INX_WIRELESS_G:
		pRaInfo->RAUseRate=(pRaInfo->RateMask)&0x00000ff0;
		break;
	case RATR_INX_WIRELESS_B:
		pRaInfo->RAUseRate=(pRaInfo->RateMask)&0x0000000d;
		break;
	case 12:
		MaskFromReg=RTL_R32(ARFR0);
		pRaInfo->RAUseRate=(pRaInfo->RateMask)&MaskFromReg;
		break;
	case 13:
		MaskFromReg=RTL_R32(ARFR1);
		pRaInfo->RAUseRate=(pRaInfo->RateMask)&MaskFromReg;
		break;
	case 14:
		MaskFromReg=RTL_R32(ARFR2);
		pRaInfo->RAUseRate=(pRaInfo->RateMask)&MaskFromReg;
		break;
	case 15:
		MaskFromReg=RTL_R32(ARFR3);
		pRaInfo->RAUseRate=(pRaInfo->RateMask)&MaskFromReg;
		break;
	default:
		pRaInfo->RAUseRate=(pRaInfo->RateMask);
		break;
	}
	// Highest rate
	if (pRaInfo->RAUseRate) {
		for (i=RATESIZE;i>=0;i--) {
			if((pRaInfo->RAUseRate)&BIT(i)) {
				pRaInfo->HighestRate=i;
				break;
			}
		}
	} else {
		pRaInfo->HighestRate=0;
	}

	// Lowest rate
	if (pRaInfo->RAUseRate) {
		for (i=0;i<RATESIZE;i++) {
			if((pRaInfo->RAUseRate)&BIT(i)) {
				pRaInfo->LowestRate=i;
				break;
			}
		}
	} else {
		pRaInfo->LowestRate=0;
	}
#if 0
	pRaInfo->RAWaitingCounter=0;
	pRaInfo->RAExtendCounter=0;
#endif
	
/*	panic_printk("%s %d: RateID=%d RateMask=%8.8x RAUseRate=%8.8x HighestRate=%d\n", 
				__FUNCTION__, __LINE__, 
				pRaInfo->RateID, pRaInfo->RateMask, pRaInfo->RAUseRate, pRaInfo->HighestRate);*/
	return 0;
}
Пример #13
0
static void
rtl8169_hw_start(struct net_device *dev)
{
    struct rtl8169_private *tp = dev->priv;
    void *ioaddr = tp->mmio_addr;
    u32 i;

    /* Soft reset the chip. */
    RTL_W8(ChipCmd, CmdReset);

    /* Check that the chip has finished the reset. */
    for (i = 1000; i > 0; i--) {
        if ((RTL_R8(ChipCmd) & CmdReset) == 0)
            break;
        else
            udelay(10);
    }

    RTL_W8(Cfg9346, Cfg9346_Unlock);
    RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
    RTL_W8(EarlyTxThres, EarlyTxThld);

    // For gigabit rtl8169
    RTL_W16(RxMaxSize, RxPacketMaxSize);

    // Set Rx Config register
    i = rtl8169_rx_config | (RTL_R32(RxConfig) & rtl_chip_info[tp->chipset].
                             RxConfigMask);
    RTL_W32(RxConfig, i);

    /* Set DMA burst size and Interframe Gap Time */
    RTL_W32(TxConfig,
            (TX_DMA_BURST << TxDMAShift) | (InterFrameGap <<
                                            TxInterFrameGapShift));
    tp->cp_cmd |= RTL_R16(CPlusCmd);
    RTL_W16(CPlusCmd, tp->cp_cmd);

    if (tp->mac_version == RTL_GIGA_MAC_VER_D) {
        dprintk(KERN_INFO PFX "Set MAC Reg C+CR Offset 0xE0: bit-3 and bit-14 MUST be 1\n");
        tp->cp_cmd |= (1 << 14) | PCIMulRW;
        RTL_W16(CPlusCmd, tp->cp_cmd);
    }

    tp->cur_rx = 0;

    RTL_W32(TxDescStartAddrLow, ((u64) tp->TxPhyAddr & DMA_32BIT_MASK));
    RTL_W32(TxDescStartAddrHigh, ((u64) tp->TxPhyAddr >> 32));
    RTL_W32(RxDescAddrLow, ((u64) tp->RxPhyAddr & DMA_32BIT_MASK));
    RTL_W32(RxDescAddrHigh, ((u64) tp->RxPhyAddr >> 32));
    RTL_W8(Cfg9346, Cfg9346_Lock);
    udelay(10);

    RTL_W32(RxMissed, 0);

    rtl8169_set_rx_mode(dev);

    /* no early-rx interrupts */
    RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);

    /* Enable all known interrupts by setting the interrupt mask. */
    RTL_W16(IntrMask, rtl8169_intr_mask);

    netif_start_queue(dev);

}