__interrupt void CC1101_ISR(void) { switch(__even_in_range(RF1AIV,32)) // Prioritizing Radio Core Interrupt { case 0: break; // No RF core interrupt pending case 2: break; // RFIFG0 case 4: break; // RFIFG1 case 6: break; // RFIFG2 case 8: break; // RFIFG3 case 10: break; // RFIFG4 case 12: break; // RFIFG5 case 14: break; // RFIFG6 case 16: break; // RFIFG7 case 18: break; // RFIFG8 case 20: // RFIFG9 if(receiving) // RX end of packet { // Read the length byte from the FIFO RxBufferLength = ReadSingleReg( RXBYTES ); ReadBurstReg(RF_RXFIFORD, RxBuffer, RxBufferLength); // Stop here to see contents of RxBuffer __no_operation(); // Check the CRC results if(RxBuffer[CRC_LQI_IDX] & CRC_OK) P3OUT |= BIT2; // Toggle LED1 *((pInt8U)&Rclock_ext)=RxBuffer[0]; if(Flags.sync) { Rclock=Rclock_ext; Flags.sync = 0; } diff=Rclock-Rclock_ext; //ReceiveOff(); } else if(transmitting) // TX end of packet { RF1AIE &= ~BIT9; // Disable TX end-of-packet interrupt P3OUT &= ~(BIT0+BIT1+BIT2); // Turn off LED after Transmit transmitting = 0; } else while(1); // trap break; case 22: break; // RFIFG10 case 24: break; // RFIFG11 case 26: break; // RFIFG12 case 28: break; // RFIFG13 case 30: break; // RFIFG14 case 32: break; // RFIFG15 } // __bic_SR_register_on_exit(LPM3_bits); }
__interrupt void CC1101_ISR(void) { switch(__even_in_range(RF1AIV,32)) // Prioritizing Radio Core Interrupt { case 0: break; // No RF core interrupt pending case 2: break; // RFIFG0 case 4: break; // RFIFG1 case 6: break; // RFIFG2 case 8: break; // RFIFG3 case 10: break; // RFIFG4 case 12: break; // RFIFG5 case 14: break; // RFIFG6 case 16: break; // RFIFG7 case 18: break; // RFIFG8 case 20: // RFIFG9 if(receiving) // RX end of packet { // Check for ADDRESS: // If ADDRESS = Correct: // Return contents of RxBuffer // If ADDRESS = False: // Break volatile unsigned i; // Read the length byte from the FIFO RxBufferLength = ReadSingleReg( RXBYTES ); ReadBurstReg(RF_RXFIFORD, RxBuffer, RxBufferLength); // Stop here to see contents of RxBuffer __no_operation(); // Check the CRC results if(RxBuffer[CRC_LQI_IDX] & CRC_OK){ // Check to see if the ADDRESS is correct) if(RxBuffer[0] && ADDRESS){ for(i = PACKET_LEN+1; i > 0; i--){ Received_data[i] = RxBuffer[i]; } } } } else if(transmitting) // TX end of packet { RF1AIE &= ~BIT9; // Disable TX end-of-packet interrupt transmitting = 0; } else while(1); // trap break; case 22: break; // RFIFG10 case 24: break; // RFIFG11 case 26: break; // RFIFG12 case 28: break; // RFIFG13 case 30: break; // RFIFG14 case 32: break; // RFIFG15 } __bic_SR_register_on_exit(LPM3_bits); }
void RF_Connection_Test(void) { Init_RF(); timer1_A3_Up_Mode; while(1){ if (buttonPressed) // Process a button pressed --> transmit { //P3OUT |= BIT6; // Pulse LED during Transmit buttonPressed = 0; P1IFG = 0; ReceiveOff(); Transmit( (unsigned char*)TxBuffer, sizeof TxBuffer); //Wait for TX status to be reached before going back to low power mode while((Strobe(RF_SNOP) & 0x70) != 0x20); P1IE |= BIT1; // Re-enable button press } else if (packetTransmit) { RF1AIE &= ~BIT9; // Disable RFIFG9 TX end-of-packet interrupts //P3OUT &= ~BIT6; // Turn off LED after Transmit ReceiveOn(); //Wait for RX status to be reached while((Strobe(RF_SNOP) & 0x70) != 0x10); packetTransmit = 0; } else if(packetReceived) // Process a received packet { char toggle = 1; // Read the length byte from the FIFO RxBufferLength = ReadSingleReg( RXBYTES ); ReadBurstReg(RF_RXFIFORD, RxBuffer, RxBufferLength); // Check the packet contents and don't toggle LED if they are different for(i = 0; i < RxBuffer[0]; i++) { if(RxBuffer[i] != TxBuffer[i]) toggle = 0; } if(toggle){ LED_Togg; // Toggle LED packetReceived = 0; } } } }
byte RADIOClass::ReceiveData(byte *rxBuffer) { byte size; byte status[2]; if(ReadStatusReg(RADIO_RXBYTES) & BURST_BYTES_IN_TXFIFO) // 0x7F MULTIPLE TRY PRESENT BF { size=ReadSingleReg(RADIO_RXFIFO); ReadBurstReg(RADIO_RXFIFO,rxBuffer,size); ReadBurstReg(RADIO_RXFIFO,status,2); Strobe(RADIO_SFRX); return size; } else { Strobe(RADIO_SFRX); return 0; } }
void rx_data_isr() { //Read number of bytes in RXFIFO uint8_t rxBytes = ReadSingleReg(RXBYTES); #ifdef LOG_PHY_ENABLED log_print_stack_string(LOG_PHY, "rx_data_isr (%d bytes received)", rxBytes); #endif #ifdef D7_PHY_USE_FEC if(fec) { uint8_t fecbuffer[4]; //If length is not set get the length from RXFIFO and set PKTLEN if (packetLength == 0) { ReadBurstReg(RXFIFO, fecbuffer, 4); fec_decode(fecbuffer); fec_set_length(*buffer); packetLength = ((*buffer & 0xFE) + 2) << 1; remainingBytes = packetLength - 4; WriteSingleReg(PKTLEN, (uint8_t)(packetLength & 0x00FF)); WriteSingleReg(FIFOTHR, RADIO_FIFOTHR_FIFO_THR_17_48); rxBytes -= 4; } //If remaining bytes is equal or less than 255 - fifo size, set length to fixed if(remainingBytes < 192) set_length_infinite(false); //Read data from buffer and decode while (rxBytes >= 4) { ReadBurstReg(RXFIFO, fecbuffer, 4); if(fec_decode(fecbuffer) == false) break; remainingBytes -= 4; rxBytes -= 4; } } else { #endif //If length is not set get the length from RXFIFO and set PKTLEN if (packetLength == 0) { packetLength = ReadSingleReg(RXFIFO); WriteSingleReg(PKTLEN, packetLength); WriteSingleReg(FIFOTHR, RADIO_FIFOTHR_FIFO_THR_17_48); remainingBytes = packetLength - 1; bufferPosition[0] = packetLength; bufferPosition++; rxBytes--; #ifdef LOG_PHY_ENABLED log_print_stack_string(LOG_PHY, "rx_data_isr getting packetLength (%d)", packetLength); #endif } //Never read the entire buffer as long as more data is going to be received if (remainingBytes > rxBytes) { rxBytes--; } else { rxBytes = remainingBytes; } //Read data from buffer ReadBurstReg(RXFIFO, bufferPosition, rxBytes); remainingBytes -= rxBytes; bufferPosition += rxBytes; #ifdef D7_PHY_USE_FEC } #endif //When all data has been received read rssi and lqi value and set packetreceived flag if(remainingBytes == 0) { rx_data.rssi = calculate_rssi(ReadSingleReg(RXFIFO)); rx_data.lqi = ReadSingleReg(RXFIFO) & 0x7F; rx_data.length = *buffer; rx_data.data = buffer; #ifdef LOG_PHY_ENABLED log_print_stack_string(LOG_PHY, "rx_data_isr packet received"); #endif } #ifdef LOG_PHY_ENABLED log_print_stack_string(LOG_PHY, "rx_data_isr 1"); #endif }
void CC1101_ISR(void) { switch((RF1AIV)) // Prioritizing Radio Core Interrupt { case 0: break; // No RF core interrupt pending case 2: break; // RFIFG0 case 4: break; // RFIFG1 case 6: break; // RFIFG2 case 8: break; // RFIFG3 case 10: break; // RFIFG4 case 12: break; // RFIFG5 case 14: break; // RFIFG6 case 16: break; // RFIFG7 case 18: break; // RFIFG8 case 20: // RFIFG9 if(receiving) // RX end of packet { transmit = 1; receive = 0; // Read the length byte from the FIFO RxBufferLength = ReadSingleReg( RXBYTES ); ReadBurstReg(RF_RXFIFORD, RxBuffer, RxBufferLength); // Stop here to see contents of RxBuffer __no_operation(); rssi=radio_rssi(); //print the raw buffer without CRC check - raja code //uart_write( RxBuffer, RxBufferLength ); // Check the CRC results if(RxBuffer[CRC_LQI_IDX] & CRC_OK) { LED_OUT |= (1<<LED_GBIT); // Toggle LED1 //print the CRC checked buffer and say CRC check ok -- raja code // printf("Hello, welcome to serial port example\n"); printf("REceived RSSSI is .. %i dBm \r", rssi); //printf("\n"); //uart_write( RxBuffer, RxBufferLength ); delayms(10); LED_OUT &=~(1<<LED_GBIT); } } else if(transmitting) // TX end of packet { RF1AIE &= ~BIT9; // Disable TX end-of-packet interrupt LEDR_OFF(); // Turn off LED after Transmit printf("trasmitting \n"); transmitting = 0; transmit = 0; receive = 1; } else while(1); // trap break; case 22: break; // RFIFG10 case 24: break; // RFIFG11 case 26: break; // RFIFG12 case 28: break; // RFIFG13 case 30: break; // RFIFG14 case 32: break; // RFIFG15 } __bic_SR_register_on_exit(LPM3_bits); }