void CPersTest00::PersTest00() {
if (PR1_htValid) {
switch (PR1_htInst) {
case TEST00_ENTRY: {
HtContinue(TEST00_WR0);
break;
}
case TEST00_WR0: {
GW1_test00_0_dst_s0_data[0][0].write_addr(14, 13);
GW1_test00_0_dst_s0_data[0][0].test00_0_dst_v0_data[0][0] = ((uint8_t)0x001af188b6cf7780LL);
GW1_test00_0_dst_s0_data[0][0].test00_0_dst_v0_data[1][0] = ((uint8_t)0x001af188b6cf7780LL);
GW1_test00_0_dst_s0_data[0][0].test00_0_dst_v0_data[2][0] = ((uint8_t)0x001af188b6cf7780LL);
GW1_test00_0_dst_s0_data[0][0].test00_0_dst_v1_data = ((uint32_t)0x001de80faced6660LL);
GW1_test00_0_dst_s0_data[0][0].test00_0_dst_v2_data = ((int64_t)0x0002809850655dc0LL);
HtContinue(TEST00_ST0);
break;
}
case TEST00_ST0: {
if (WriteMemBusy()) {
HtRetry();
break;
}
WriteMem_test00_0_dst_s0_data(PR1_memAddr + 0, 0, 0, 1);
WriteMemPause(TEST00_LD0);
break;
}
case TEST00_LD0: {
if (ReadMemBusy()) {
HtRetry();
break;
}
ReadMem_test00_0_dst_s0_data(PR1_memAddr + 0, 6, 5, 0, 1);
ReadMemPause(TEST00_CHK0);
break;
}
case TEST00_CHK0: {
if (GR1_test00_0_dst_s0_data[0][0].test00_0_dst_v0_data[0][0] != ((uint8_t)0x001af188b6cf7780LL)) {
HtAssert(0, 0);
}
if (GR1_test00_0_dst_s0_data[0][0].test00_0_dst_v0_data[1][0] != ((uint8_t)0x001af188b6cf7780LL)) {
HtAssert(0, 0);
}
if (GR1_test00_0_dst_s0_data[0][0].test00_0_dst_v0_data[2][0] != ((uint8_t)0x001af188b6cf7780LL)) {
HtAssert(0, 0);
}
if (GR1_test00_0_dst_s0_data[0][0].test00_0_dst_v1_data != ((uint32_t)0x001de80faced6660LL)) {
HtAssert(0, 0);
}
if (GR1_test00_0_dst_s0_data[0][0].test00_0_dst_v2_data != ((int64_t)0x0002809850655dc0LL)) {
HtAssert(0, 0);
}
HtContinue(TEST00_RTN);
break;
}
case TEST00_RTN: {
if (SendReturnBusy_test00()) {
HtRetry();
break;
}
SendReturn_test00();
break;
}
default:
assert(0);
}
}
if (PR2_htValid) {
switch (PR2_htInst) {
case TEST00_ENTRY: {
break;
}
case TEST00_WR0: {
break;
}
case TEST00_ST0: {
break;
}
case TEST00_LD0: {
P2_test00_0_dst_s0_data_RdAddr1 = (ht_uint4)6;
P2_test00_0_dst_s0_data_RdAddr2 = (ht_uint5)5;
break;
}
case TEST00_CHK0: {
break;
}
case TEST00_RTN: {
break;
}
default:
assert(0);
}
}
}
void
CPersInc11::PersInc11()
{
if (PR1_htValid) {
switch (PR1_htInst) {
case INC11_INIT:
{
P1_loopIdx[0][1] = 0;
P1_wrGrpId = PR1_htId ^ 0x5;
// wait until all threads have started
HtContinue(INC11_READ);
}
break;
case INC11_READ:
{
if (ReadMemBusy()) {
HtRetry();
break;
}
// Calculate memory read address
MemAddr_t memRdAddr = SR_arrayAddr + ((P1_loopBase + P1_loopIdx[0][1]) << 3);
Inc11Ptr_t arrayMemWrPtr = (PR1_htId << 7) | P1_loopIdx[0][1];
// Issue read request to memory
ReadMem_arrayMem11(memRdAddr, arrayMemWrPtr);
bool bLast = P1_loopIdx[0][1] == P1_elemCnt - 1;
if (bLast) {
P1_loopIdx[0][1] = 0;
ReadMemPause(INC11_WRITE);
} else {
P1_loopIdx[0][1] += 1;
HtContinue(INC11_READ);
}
// Set address for reading memory response data
P1_arrayMemRdPtr = (PR1_htId << 7) | P1_loopIdx[0][1];
}
break;
case INC11_WRITE:
{
if (WriteMemBusy()) {
//if (WriteMemBusy(wrRspGrpId)) {
HtRetry();
break;
}
// Increment memory data
uint64_t memWrData = GR1_arrayMem11.data + 1;
// Calculate memory write address
MemAddr_t memWrAddr = SR_arrayAddr + ((P1_loopBase + P1_loopIdx[0][1]) << 3);
// Issue write memory request
WriteMem(PR1_wrGrpId, memWrAddr, memWrData);
bool bLast = P1_loopIdx[0][1] == P1_elemCnt - 1;
if (bLast) {
P1_loopIdx[0][1] = 0;
//WriteMemPause(wrRspGrpId, INC11_RTN);
WriteMemPause(PR1_wrGrpId, INC11_RTN);
//HtPause();
} else {
P1_loopIdx[0][1] += 1;
HtContinue(INC11_WRITE);
}
// Set address for reading memory response data
P1_arrayMemRdPtr = (PR1_htId << 7) | P1_loopIdx[0][1];
}
break;
case INC11_RTN:
{
if (SendReturnBusy_inc11()) {
HtRetry();
break;
}
SendReturn_inc11(P1_elemCnt);
break;
}
default:
assert(0);
}
}
}
void CPersRd::PersRd() {
if (PR_htValid) {
switch (PR_htInst) {
case RD_ENTRY: {
P_bStandalonePause = false;
P_reqIdx = 0;
P_loopIdx = 0;
P_memOffset = PR_threadId;
HtBarrier(RD_REQ, 8);
break;
}
case RD_REQ: {
if (ReadMemBusy()) {
HtRetry();
break;
}
ht_uint5 elemCnt = ((PR_threadId + PR_reqIdx) & 7) + 1;
if (PR_memOffset + elemCnt + PR_threadId >= 256)
P_memOffset = PR_threadId;
ht_uint8 info = PR_threadId + P_memOffset;
ht_uint48 addr = PR_memAddr + P_memOffset * 8;
ReadMem_rdFunc(addr, info, elemCnt);
P_memOffset += elemCnt;
if (PR_reqIdx == 7) {
if (PR_bStandalonePause) {
HtContinue(RD_PAUSE);
} else {
ReadMemPause(RD_LOOP);
}
P_bStandalonePause ^= 1;
P_reqIdx = 0;
} else {
P_reqIdx += 1;
HtContinue(RD_REQ);
}
break;
}
case RD_PAUSE: {
if (ReadMemBusy()) {
HtRetry();
break;
}
ReadMemPause(RD_LOOP);
break;
}
case RD_LOOP: {
if (PR_loopIdx == 255) {
HtContinue(RD_RTN);
} else {
HtContinue(RD_REQ);
}
P_loopIdx += 1;
break;
}
case RD_RTN: {
if (SendReturnBusy_rdPause()) {
HtRetry();
break;
}
SendReturn_rdPause();
break;
}
default:
assert(0);
}
}
}
void
CPersInc::PersInc()
{
if (PR_htValid) {
switch (PR_htInst) {
case INC_INIT:
{
P_loopCnt = 0;
P_reqCnt = 0;
// Set address for reading memory response data
P_arrayMemRdPtr = PR_htId;
HtContinue(INC_READ);
}
break;
case INC_READ:
{
if (ReadMemBusy() || SendReturnBusy_htmain()) {
HtRetry();
break;
}
// Check if end of loop
if (P_loopCnt == P_elemCnt) {
// Return to host interface
SendReturn_htmain(P_loopCnt);
} else {
// Calculate memory read address
sc_uint<MEM_ADDR_W> memRdAddr = (sc_uint<MEM_ADDR_W>)(SR_arrayAddr + (((P_loopCnt + P_reqCnt) * 2) << 3));
sc_uint<2> rdDstId = P_reqCnt;
bool bLast = P_reqCnt == 3;
// Issue read request to memory
switch (rdDstId) {
case 0:
ReadMem_arrayMem1Fld1(memRdAddr, PR_htId);
break;
case 1:
ReadMem_arrayMem1Fld2(memRdAddr, PR_htId);
break;
case 2:
ReadMem_arrayMem2Fld1(memRdAddr, PR_htId);
break;
case 3:
ReadMem_arrayMem2Fld2(memRdAddr, PR_htId);
break;
}
if (bLast) {
P_reqCnt = 0;
ReadMemPause(INC_WRITE);
} else {
P_reqCnt += 1;
HtContinue(INC_READ);
}
}
}
break;
case INC_WRITE:
{
if (WriteMemBusy()) {
HtRetry();
break;
}
// Increment memory data
uint64_t memWrData = 0;
sc_uint<2> rdDstId = P_reqCnt;
switch (rdDstId) {
case 0:
memWrData = GR_arrayMem1.fld1 + 1;
break;
case 1:
memWrData = GR_arrayMem1.fld2 + 1;
break;
case 2:
memWrData = GR_arrayMem2.fld1 + 1;
break;
case 3:
memWrData = GR_arrayMem2.fld2 + 1;
break;
}
// Calculate memory write address
sc_uint<MEM_ADDR_W> memWrAddr = (sc_uint<MEM_ADDR_W>)(SR_arrayAddr + (((P_loopCnt + P_reqCnt) * 2 + 1) << 3));
bool bLast = P_reqCnt == 3;
// Issue write memory request
WriteMem(memWrAddr, memWrData);
if (bLast) {
// Increment loop count
P_loopCnt = P_loopCnt + 4;
P_reqCnt = 0;
WriteMemPause(INC_READ);
} else {
P_reqCnt += 1;
HtContinue(INC_WRITE);
}
}
break;
default:
assert(0);
}
}
}
void CPersTest00::PersTest00() {
if (PR_htValid) {
switch (PR_htInst) {
case TEST00_ENTRY: {
HtContinue(TEST00_WR0);
break;
}
case TEST00_WR0: {
PW_test00_0_dst_u0_data.write_addr(0);
PW_test00_0_dst_u0_data.test00_0_dst_v0_data[0][0] = ((int32_t)0x0015f6080d6fd5c0LL);
PW_test00_0_dst_u0_data.test00_0_dst_v0_data[0][1] = ((int32_t)0x0015f6080d6fd5c0LL);
PW_test00_0_dst_u0_data.test00_0_dst_v0_data[0][2] = ((int32_t)0x0015f6080d6fd5c0LL);
PW_test00_0_dst_u0_data.test00_0_dst_v0_data[0][3] = ((int32_t)0x0015f6080d6fd5c0LL);
PW_test00_0_dst_u0_data.test00_0_dst_v0_data[0][4] = ((int32_t)0x0015f6080d6fd5c0LL);
PW_test00_0_dst_u0_data.test00_0_dst_v0_data[1][0] = ((int32_t)0x0015f6080d6fd5c0LL);
PW_test00_0_dst_u0_data.test00_0_dst_v0_data[1][1] = ((int32_t)0x0015f6080d6fd5c0LL);
PW_test00_0_dst_u0_data.test00_0_dst_v0_data[1][2] = ((int32_t)0x0015f6080d6fd5c0LL);
PW_test00_0_dst_u0_data.test00_0_dst_v0_data[1][3] = ((int32_t)0x0015f6080d6fd5c0LL);
PW_test00_0_dst_u0_data.test00_0_dst_v0_data[1][4] = ((int32_t)0x0015f6080d6fd5c0LL);
PW_test00_0_dst_u0_data.test00_0_dst_v0_data[2][0] = ((int32_t)0x0015f6080d6fd5c0LL);
PW_test00_0_dst_u0_data.test00_0_dst_v0_data[2][1] = ((int32_t)0x0015f6080d6fd5c0LL);
PW_test00_0_dst_u0_data.test00_0_dst_v0_data[2][2] = ((int32_t)0x0015f6080d6fd5c0LL);
PW_test00_0_dst_u0_data.test00_0_dst_v0_data[2][3] = ((int32_t)0x0015f6080d6fd5c0LL);
PW_test00_0_dst_u0_data.test00_0_dst_v0_data[2][4] = ((int32_t)0x0015f6080d6fd5c0LL);
HtContinue(TEST00_ST0);
break;
}
case TEST00_ST0: {
if (WriteMemBusy()) {
HtRetry();
break;
}
WriteMem_test00_0_dst_u0_data(PR_memAddr + 0, 0);
WriteMemPause(TEST00_LD0);
break;
}
case TEST00_LD0: {
if (ReadMemBusy()) {
HtRetry();
break;
}
ReadMem_test00_0_dst_u0_data(PR_memAddr + 0, 0);
P_test00_0_dst_u0_data_RdAddr1 = (ht_uint1)0;
ReadMemPause(TEST00_CHK0);
break;
}
case TEST00_CHK0: {
if (PR_test00_0_dst_u0_data.test00_0_dst_v0_data[0][0] != ((int32_t)(ht_int32)0x000000000d6fd5c0LL)) {
HtAssert(0, 0);
}
if (PR_test00_0_dst_u0_data.test00_0_dst_v0_data[0][1] != ((int32_t)(ht_int32)0x000000000d6fd5c0LL)) {
HtAssert(0, 0);
}
if (PR_test00_0_dst_u0_data.test00_0_dst_v0_data[0][2] != ((int32_t)(ht_int32)0x000000000d6fd5c0LL)) {
HtAssert(0, 0);
}
if (PR_test00_0_dst_u0_data.test00_0_dst_v0_data[0][3] != ((int32_t)(ht_int32)0x000000000d6fd5c0LL)) {
HtAssert(0, 0);
}
if (PR_test00_0_dst_u0_data.test00_0_dst_v0_data[0][4] != ((int32_t)(ht_int32)0x000000000d6fd5c0LL)) {
HtAssert(0, 0);
}
if (PR_test00_0_dst_u0_data.test00_0_dst_v0_data[1][0] != ((int32_t)(ht_int32)0x000000000d6fd5c0LL)) {
HtAssert(0, 0);
}
if (PR_test00_0_dst_u0_data.test00_0_dst_v0_data[1][1] != ((int32_t)(ht_int32)0x000000000d6fd5c0LL)) {
HtAssert(0, 0);
}
if (PR_test00_0_dst_u0_data.test00_0_dst_v0_data[1][2] != ((int32_t)(ht_int32)0x000000000d6fd5c0LL)) {
HtAssert(0, 0);
}
if (PR_test00_0_dst_u0_data.test00_0_dst_v0_data[1][3] != ((int32_t)(ht_int32)0x000000000d6fd5c0LL)) {
HtAssert(0, 0);
}
if (PR_test00_0_dst_u0_data.test00_0_dst_v0_data[1][4] != ((int32_t)(ht_int32)0x000000000d6fd5c0LL)) {
HtAssert(0, 0);
}
if (PR_test00_0_dst_u0_data.test00_0_dst_v0_data[2][0] != ((int32_t)(ht_int32)0x000000000d6fd5c0LL)) {
HtAssert(0, 0);
}
if (PR_test00_0_dst_u0_data.test00_0_dst_v0_data[2][1] != ((int32_t)(ht_int32)0x000000000d6fd5c0LL)) {
HtAssert(0, 0);
}
if (PR_test00_0_dst_u0_data.test00_0_dst_v0_data[2][2] != ((int32_t)(ht_int32)0x000000000d6fd5c0LL)) {
HtAssert(0, 0);
}
if (PR_test00_0_dst_u0_data.test00_0_dst_v0_data[2][3] != ((int32_t)(ht_int32)0x000000000d6fd5c0LL)) {
HtAssert(0, 0);
}
if (PR_test00_0_dst_u0_data.test00_0_dst_v0_data[2][4] != ((int32_t)(ht_int32)0x000000000d6fd5c0LL)) {
HtAssert(0, 0);
}
if (PR_test00_0_dst_u0_data.test00_0_dst_v1_data != ((uint32_t)(ht_uint32)0x000000000d6fd5c0LL)) {
HtAssert(0, 0);
}
HtContinue(TEST00_RTN);
break;
}
case TEST00_RTN: {
if (SendReturnBusy_test00()) {
HtRetry();
break;
}
SendReturn_test00();
break;
}
default:
assert(0);
}
}
}
void CPersRdSub::PersRdSub()
{
if (PR_htValid) {
switch (PR_htInst) {
case WS_READ:
{
#ifndef _HTV
entryMask |= 1 << PR_htId;
#endif
if (
#ifndef _HTV
entryMask != ((1ull << (1 << WS_HTID_W))-1) ||
#endif
ReadMemBusy()) {
HtRetry();
break;
}
switch (P_rdType) {
case 0:
ReadMem_uint8(P_rdAddr, PR_htId);
break;
case 1:
ReadMem_uint16(P_rdAddr, PR_htId);
break;
case 2:
ReadMem_uint32(P_rdAddr, PR_htId);
break;
case 3:
ReadMem_uint64(P_rdAddr, PR_htId);
break;
case 4:
ReadMem_int8(P_rdAddr, PR_htId);
break;
case 5:
ReadMem_int16(P_rdAddr, PR_htId);
break;
case 6:
ReadMem_int32(P_rdAddr, PR_htId);
break;
case 7:
ReadMem_int64(P_rdAddr, PR_htId);
break;
default:
assert(0);
}
ReadMemPause(WS_RETURN);
}
break;
case WS_RETURN:
{
if (SendReturnBusy_RdSub()) {
HtRetry();
break;
}
SendReturn_RdSub(S_actual[PR_htId], P_expected);
}
break;
default:
assert(0);
}
}
}
void
CPersInc0::PersInc0()
{
if (PR_htValid) {
switch (PR_htInst) {
case INC0_INIT:
{
P_loopIdx = 0;
HtContinue(INC0_READ);
}
break;
case INC0_READ:
{
if (ReadMemBusy()) {
HtRetry();
break;
}
// Calculate memory read address
MemAddr_t memRdAddr = SR_arrayAddr + ((P_loopBase + P_loopIdx) << 3);
Inc0Ptr_t arrayMemWrPtr = (Inc0Ptr_t)P_loopIdx;
// Issue read request to memory
ReadMem_arrayMem0(memRdAddr, arrayMemWrPtr);
bool bLast = P_loopIdx == P_elemCnt - 1;
if (bLast) {
P_loopIdx = 0;
ReadMemPause(INC0_WRITE);
} else {
P_loopIdx += 1;
HtContinue(INC0_READ);
}
// Set address for reading memory response data
P_arrayMemRdPtr = (Inc0Ptr_t)P_loopIdx;
}
break;
case INC0_WRITE:
{
if (WriteMemBusy()) {
HtRetry();
break;
}
// Increment memory data
uint64_t memWrData = GR_arrayMem0.data + 1;
// Calculate memory write address
MemAddr_t memWrAddr = SR_arrayAddr + ((P_loopBase + P_loopIdx) << 3);
// Issue write memory request
WriteMem(memWrAddr, memWrData);
bool bLast = P_loopIdx == P_elemCnt - 1;
if (bLast) {
P_loopIdx = 0;
WriteMemPause(INC0_RTN);
} else {
P_loopIdx += 1;
HtContinue(INC0_WRITE);
}
// Set address for reading memory response data
P_arrayMemRdPtr = (Inc0Ptr_t)P_loopIdx;
}
break;
case INC0_RTN:
{
if (SendReturnBusy_inc0()) {
HtRetry();
break;
}
SendReturn_inc0(P_elemCnt);
break;
}
default:
assert(0);
}
}
}
void CPersTest00::PersTest00() {
if (PR_htValid) {
switch (PR_htInst) {
case TEST00_ENTRY: {
HtContinue(TEST00_WR);
break;
}
case TEST00_WR: {
GW_test00_g_0_0_0_data = (uint16_t)0x0015c20462c8ce60LL;
P_test00_p_0_2_0_data[0] = (uint16_t)0x001e2a75cc536260LL;
S_test00_s_1_4_0_data.write_addr(1);
S_test00_s_1_4_0_data.write_mem((uint32_t)0x001fff1d35a161a0LL);
GW_test00_g_0_7_0_data[1].write_addr(4);
GW_test00_g_0_7_0_data[1] = (uint8_t)0x00155ea1c93695a0LL;
P_test00_g_0_7_0_data_RdAddr = (ht_uint3)4;
HtContinue(TEST00_ST0);
break;
}
case TEST00_ST0: {
if (WriteMemBusy()) {
HtRetry();
break;
}
WriteMem_uint16_t(PR_memAddr + 0, GR_test00_g_0_0_0_data);
HtContinue(TEST00_ST1);
break;
}
case TEST00_ST1: {
if (WriteMemBusy()) {
HtRetry();
break;
}
WriteMem_test00_p_0_2_0_data(PR_memAddr + 32);
HtContinue(TEST00_ST2);
break;
}
case TEST00_ST2: {
if (WriteMemBusy()) {
HtRetry();
break;
}
WriteMem_test00_s_1_4_0_data(PR_memAddr + 64, 1, 1);
HtContinue(TEST00_ST3);
break;
}
case TEST00_ST3: {
if (WriteMemBusy()) {
HtRetry();
break;
}
WriteMem_uint8_t(PR_memAddr + 96, GR_test00_g_0_7_0_data[1]);
WriteMemPause(TEST00_LD0);
break;
}
case TEST00_LD0: {
if (ReadMemBusy()) {
HtRetry();
break;
}
ReadMem_test00_g_0_1_0_data(PR_memAddr + 0);
HtContinue(TEST00_LD1);
break;
}
case TEST00_LD1: {
if (ReadMemBusy()) {
HtRetry();
break;
}
ReadMem_test00_p_0_3_0_data(PR_memAddr + 32);
HtContinue(TEST00_LD2);
break;
}
case TEST00_LD2: {
if (ReadMemBusy()) {
HtRetry();
break;
}
ReadMem_test00_g_0_6_0_data(PR_memAddr + 64);
HtContinue(TEST00_LD3);
break;
}
case TEST00_LD3: {
if (ReadMemBusy()) {
HtRetry();
break;
}
ReadMem_test00_p_0_8_0_data(PR_memAddr + 96, 1, 1);
ReadMemPause(TEST00_CHK);
break;
}
case TEST00_CHK: {
if (GR_test00_g_0_1_0_data != (uint16_t)0x0015c20462c8ce60LL) {
HtAssert(0, (uint32_t)0x00000000);
}
if (PR_test00_p_0_3_0_data[1] != (uint16_t)0x001e2a75cc536260LL) {
HtAssert(0, (uint32_t)0x00000001);
}
if (GR_test00_g_0_6_0_data != (uint32_t)0x001fff1d35a161a0LL) {
HtAssert(0, (uint32_t)0x00000002);
}
if (P_test00_p_0_8_0_data[1] != (uint8_t)0x00155ea1c93695a0LL) {
HtAssert(0, (uint32_t)0x00000003);
}
HtContinue(TEST00_RTN);
break;
}
case TEST00_RTN: {
if (SendReturnBusy_test00()) {
HtRetry();
break;
}
SendReturn_test00();
break;
}
default:
assert(0);
}
}
}
void CPersTest02::PersTest02() {
if (PR1_htValid) {
switch (PR1_htInst) {
case TEST02_ENTRY: {
HtContinue(TEST02_WR);
break;
}
case TEST02_WR: {
GW1_test02_2_src_s0_data[0].test02_2_src_v2_data[0] = ((int32_t)0x000f769b29b0de80LL);
GW1_test02_3_src_v0_data[2][1].write_addr(0);
GW1_test02_3_src_v0_data[2][1] = ((uint16_t)0x00119150471acf80LL);
HtContinue(TEST02_ST0);
break;
}
case TEST02_ST0: {
if (WriteMemBusy()) {
HtRetry();
break;
}
WriteMem_test02_0_dst_s0_data(PR1_memAddr + 0);
HtContinue(TEST02_ST1);
break;
}
case TEST02_ST1: {
if (WriteMemBusy()) {
HtRetry();
break;
}
WriteMem_test02_1_src_v0_data(PR1_memAddr + 64);
HtContinue(TEST02_ST2);
break;
}
case TEST02_ST2: {
if (WriteMemBusy()) {
HtRetry();
break;
}
WriteMem_test02_2_src_v2_data(PR1_memAddr + 128, 0, 0, 1);
HtContinue(TEST02_ST3);
break;
}
case TEST02_ST3: {
if (WriteMemBusy()) {
HtRetry();
break;
}
WriteMem_uint16_t(PR1_memAddr + 192, GR1_test02_3_src_v0_data[2][1]);
WriteMemPause(TEST02_LD0);
break;
}
case TEST02_LD0: {
if (ReadMemBusy()) {
HtRetry();
break;
}
ReadMem_test02_0_dst_s0_data(PR1_memAddr + 0);
HtContinue(TEST02_LD1);
break;
}
case TEST02_LD1: {
if (ReadMemBusy()) {
HtRetry();
break;
}
ReadMem_test02_1_dst_v0_data(PR1_memAddr + 64);
HtContinue(TEST02_LD2);
break;
}
case TEST02_LD2: {
if (ReadMemBusy()) {
HtRetry();
break;
}
ReadMem_test02_2_dst_v0_data(PR1_memAddr + 128);
HtContinue(TEST02_LD3);
break;
}
case TEST02_LD3: {
if (ReadMemBusy()) {
HtRetry();
break;
}
ReadMem_test02_3_dst_v0_data(PR1_memAddr + 192, 0, 8, 1);
ReadMemPause(TEST02_CHK);
break;
}
case TEST02_CHK: {
if ((int16_t)PR1_test02_0_dst_s0_data.test02_0_dst_v0_data != ((int16_t)0x00102586b946bdc0LL)) {
HtAssert(0, 0);
}
if ((int16_t)PR1_test02_0_dst_s0_data.test02_0_dst_v1_data != ((int16_t)0x0004dbed0c8b8ba0LL)) {
HtAssert(0, 0);
}
if ((int32_t)PR1_test02_0_dst_s0_data.test02_0_dst_s1_data[0].test02_0_dst_v3_data != ((int32_t)0x00097da2cf0219e0LL)) {
HtAssert(0, 0);
}
if ((int32_t)P1_test02_1_dst_v0_data[0] != ((int32_t)0x000c1276415dc900LL)) {
HtAssert(0, 0);
}
if ((int32_t)SR_test02_2_dst_v0_data != ((int32_t)0x000f769b29b0de80LL)) {
HtAssert(0, 0);
}
if ((uint16_t)PR1_test02_3_dst_v0_data != ((uint16_t)0x00119150471acf80LL)) {
HtAssert(0, 0);
}
HtContinue(TEST02_RTN);
break;
}
case TEST02_RTN: {
if (SendReturnBusy_test02()) {
HtRetry();
break;
}
SendReturn_test02();
break;
}
default:
assert(0);
}
}
if (PR2_htValid) {
switch (PR2_htInst) {
case TEST02_ENTRY: {
break;
}
case TEST02_WR: {
GW2_test02_1_src_v0_data[2] = ((int32_t)0x000c1276415dc900LL);
break;
}
case TEST02_ST0: {
break;
}
case TEST02_ST1: {
break;
}
case TEST02_ST2: {
break;
}
case TEST02_ST3: {
break;
}
case TEST02_LD0: {
break;
}
case TEST02_LD1: {
break;
}
case TEST02_LD2: {
break;
}
case TEST02_LD3: {
break;
}
case TEST02_CHK: {
break;
}
case TEST02_RTN: {
break;
}
default:
assert(0);
}
}
if (PR3_htValid) {
switch (PR3_htInst) {
case TEST02_ENTRY: {
break;
}
case TEST02_WR: {
PW3_test02_0_dst_s0_data.test02_0_dst_v0_data = ((int16_t)0x00102586b946bdc0LL);
PW3_test02_0_dst_s0_data.test02_0_dst_v1_data = ((int16_t)0x0004dbed0c8b8ba0LL);
PW3_test02_0_dst_s0_data.test02_0_dst_s1_data[0].test02_0_dst_v3_data = ((int32_t)0x00097da2cf0219e0LL);
P3_test02_3_src_v0_data_RdAddr1 = (ht_uint3)0;
break;
}
case TEST02_ST0: {
break;
}
case TEST02_ST1: {
break;
}
case TEST02_ST2: {
break;
}
case TEST02_ST3: {
break;
}
case TEST02_LD0: {
break;
}
case TEST02_LD1: {
break;
}
case TEST02_LD2: {
break;
}
case TEST02_LD3: {
P3_test02_3_dst_v0_data_RdAddr1 = (ht_uint2)0;
P3_test02_3_dst_v0_data_RdAddr2 = (ht_uint4)8;
break;
}
case TEST02_CHK: {
break;
}
case TEST02_RTN: {
break;
}
default:
assert(0);
}
}
}
void CPersRd3::PersRd3()
{
if (PR_htValid) {
switch (PR_htInst) {
case RD3_INIT:
{
P_loopCnt = 0;
P_err = 0;
P_pauseLoopCnt = 0;
P_arrayMemRd1Ptr = PR_HTID;
HtContinue(RD3_READ1);
}
break;
case RD3_READ1:
{
if (ReadMemBusy() || SendReturnBusy_rd3()) {
HtRetry();
break;
}
// Check if end of loop
if (P_loopCnt == PAUSE_LOOP_CNT || P_err) {
// Return to host interface
SendReturn_rd3(P_err);
} else {
// Calculate memory read address
MemAddr_t memRdAddr = P_arrayAddr + ((P_loopCnt & 0xf) << 3);
// Issue read request to memory
ReadMem_rd3Mem(PR_rdGrpId, memRdAddr, PR_HTID, 0);
// Set address for reading memory response data
HtContinue(RD3_READ2);
}
}
break;
case RD3_READ2:
{
if (ReadMemBusy()) {
HtRetry();
break;
}
// Calculate memory read address
MemAddr_t memRdAddr = P_arrayAddr + (((P_loopCnt + 1) & 0xf) << 3);
// Issue read request to memory
ReadMem_rd3Mem(PR_rdGrpId, memRdAddr, PR_HTID, 1);
HtContinue(RD3_READ3);
}
break;
case RD3_READ3:
{
if (ReadMemBusy()) {
HtRetry();
break;
}
// Calculate memory read address
MemAddr_t memRdAddr = P_arrayAddr + (((P_loopCnt + 2) & 0xf) << 3);
// Issue read request to memory
ReadMem_rd3Mem(PR_rdGrpId, memRdAddr, PR_HTID, 2);
HtContinue(RD3_READ4);
}
break;
case RD3_READ4:
{
if (ReadMemBusy()) {
HtRetry();
break;
}
// Calculate memory read address
MemAddr_t memRdAddr = P_arrayAddr + (((P_loopCnt + 3) & 0xf) << 3);
// Issue read request to memory
ReadMem_rd3Mem(PR_rdGrpId, memRdAddr, PR_HTID, 3);
HtContinue(RD3_LOOP);
}
break;
case RD3_LOOP:
{
if (ReadMemBusy()) {
HtRetry();
break;
}
// wait a few instructions for last response to line up with call to ReadMemPause
if (P_pauseLoopCnt == 3) {
P_pauseLoopCnt = 0;
P_arrayMemRd2Ptr = 0;
ReadMemPause(PR_rdGrpId, RD3_TEST1);
} else {
P_pauseLoopCnt += 1;
HtContinue(RD3_LOOP);
}
}
break;
case RD3_TEST1:
{
if (GR_rd3Mem.data != (P_loopCnt & 0xf)) {
HtAssert(0, 0);
P_err += 1;
}
P_arrayMemRd2Ptr = 1;
HtContinue(RD3_TEST2);
}
break;
case RD3_TEST2:
{
if (GR_rd3Mem.data != ((P_loopCnt + 1) & 0xf)) {
HtAssert(0, 0);
P_err += 1;
}
P_arrayMemRd2Ptr = 2;
HtContinue(RD3_TEST3);
}
break;
case RD3_TEST3:
{
if (GR_rd3Mem.data != ((P_loopCnt + 2) & 0xf)) {
HtAssert(0, 0);
P_err += 1;
}
P_arrayMemRd2Ptr = 3;
HtContinue(RD3_TEST4);
}
break;
case RD3_TEST4:
{
if (GR_rd3Mem.data != ((P_loopCnt + 3) & 0xf)) {
HtAssert(0, 0);
P_err += 1;
}
// Pauserement loop count
P_loopCnt = P_loopCnt + 1;
HtContinue(RD3_READ1);
}
break;
default:
assert(0);
}
}
if (r_m1_rdRspRdy) {
#ifndef _HTV
#if (RD3_RD_GRP_W == 0)
if (!r_rdGrpRsmWait)
printf("-");
else if (r_rdGrpRspCnt == 1)
printf("2");
else
printf("+");
#else
#if (RD3_RD_GRP_W <= 2)
if (!r_rdGrpState[r_m2_rdRspInfo.m_grpId].m_pause)
printf("-");
else if (r_rdGrpState[r_m2_rdRspInfo.m_grpId].m_cnt == 1)
printf("3");
else
printf("+");
#else
{
m_rdGrpReqState1.read_addr(r_rdCompGrpId);
m_rdGrpRspState0.read_addr(r_rdCompGrpId);
CRdGrpRspState c_m2_rdGrpRspState = m_rdGrpRspState0.read_mem();
CRdGrpReqState c_m2_rdGrpReqState = m_rdGrpReqState1.read_mem();
if (c_m2_rdGrpRspState.m_pause == c_m2_rdGrpReqState.m_pause)
printf("-");
else if (c_m2_rdGrpReqState.m_cnt - c_m2_rdGrpRspState.m_cnt == 1)
printf("3");
else
printf("+");
}
#endif
#endif
#endif
}
}
void
CPersEcho::PersEcho()
{
if (PR_htValid) {
switch (PR_htInst) {
case ECHO_INIT:
{
if (ReadMemBusy()) {
HtRetry();
break;
}
// Set address for reading memory response data
P_arrayMemRdPtr = 2;
P_dataCnt = 0;
sc_uint<MEM_ADDR_W> memRdAddr = (sc_uint<MEM_ADDR_W>)r_arrayAddr;
// Issue read request to memory
ReadMem_arrayMem(memRdAddr, 2);
ReadMemPause(ECHO_DATA);
}
break;
case ECHO_DATA:
{
if (ReadMemBusy() || SendReturnBusy_echo() || RecvHostDataBusy() || SendHostDataBusy()) {
HtRetry();
break;
}
// handle adding value to popped queue data and pushing to output queue
if (RecvHostDataMarker()) {
SendHostDataMarker();
// Return to host interface
SendReturn_echo(P_dataCnt);
} else {
uint64_t inData = PeekHostData();
RecvHostData();
uint64_t outData = inData + GR_arrayMem.data;
SendHostData(outData);
P_dataCnt += 1;
// Calculate memory read address
sc_uint<MEM_ADDR_W> memRdAddr = (sc_uint<MEM_ADDR_W>)(r_arrayAddr + (P_dataCnt << 3));
// Issue read request to memory
ReadMem_arrayMem(memRdAddr, 2);
ReadMemPause(ECHO_DATA);
}
}
break;
default:
assert(0);
}
}
}
