//------------------------------------------------------------------------------
// Function: AcpPacketHandler
// Description: disable digital output for ACP type 2 and above
//
//------------------------------------------------------------------------------
static void AcpPacketHandler(uint8_t qOn)
{
//disable SPIDF when ACP type >=2 For simply test.
if((qOn)&&(RegisterRead(REG__ACP_BYTE2) > 1))
{
RegisterWrite(REG__AUD_CTRL, (CONF__AUD_CTRL&(~BIT__SPEN)));
DEBUG_PRINT(("ACP type > 1, digital output blocked\n"));
}
else
RegisterWrite(REG__AUD_CTRL, CONF__AUD_CTRL);
}
static void ResetZoneControl(void)
{
{
RegisterWrite(REG__FACTORY_A87,0x03);
RegisterWrite(REG__FACTORY_A81,0x10);
RegisterWrite(REG__FACTORY_A88,0x40);
RegisterWrite(REG__FACTORY_A87,0x43);
RegisterWrite(REG__FACTORY_A81,0x18);
DEBUG_PRINT(("reset zone\n"));
CurrentStatus.AudioState = STATE_AUDIO__REQUEST_AUDIO;
CurrentStatus.VideoState = STATE_VIDEO__MUTED;
}
}
// Affected Register(s): CEC_CAPTURE_ID
// Document Reference : CEC Promgramming Interface (CPI) Programmer's Reference
// Warning: Only a single CEC device can be select with this interface even though
// the all 16 devices can be selected.
//------------------------------------------------------------------------------
//
uint8_t CEC_CAPTURE_ID_Set( uint8_t logical_address )
{
uint8_t error = FALSE;
uint8_t capture_address[2];
uint8_t capture_addr_sel = 0x01;
capture_address[0] = 0;
capture_address[1] = 0;
if( logical_address < 8 )
{
capture_addr_sel = capture_addr_sel << logical_address;
capture_address[0] = capture_addr_sel;
}
else
{
capture_addr_sel = capture_addr_sel << ( logical_address - 8 );
capture_address[1] = capture_addr_sel;
}
// Set Capture Address
RegisterWriteBlock(REG__CEC_CAPTURE_ID0,capture_address,2);
RegisterWrite(REG__CEC_TX_INIT, logical_address);
return 0;
}
/**
* Changes the state of an LED (ON or OFF)
*
* - Uses base address of I/O
* @param ledNum LED number (0 to 7)
* @param state State to change to (ON or OFF)
*/
void ZedBoard::Set1Led(int ledNum, int state)
{
std::cout << "\nWriting to LED " << ledNum << std::endl;
RegisterWrite(gpio_led1_offset + (ledNum * 4), state);
std::cout << "LED offset: " << std::hex << gpio_led1_offset+(ledNum*4) << " ";
std::cout << "LED state: " << state << std::endl;
}
//------------------------------------------------------------------------------
// Function Name: SiI_918x_Start
// Function Description: Intilize Stream Switch Device
// CEC Software Connection #1
//------------------------------------------------------------------------------
//void SiI_918x_Start( void )
void CEC_Init( void )
{
// uint8_t cec_phyAddr[2];
#if(CONF__CEC_ENABLE == ENABLE)
DEBUG_PRINT(("\nStream switch start\n"));
//CEC workaround for ES0
GPIO_ClearCecD();
RegisterModify(REG__CEC_CONFIG_CPI,BIT__CEC_PASS_THROUGH,CLEAR);
if((RegisterRead(DEV_REV_RX)& 0x0F)==VAL__REV_1_2) //if rev1.2 CEC by default reset
RegisterModify(REG__C0_SRST2, BIT__CEC_SRST, SET); //0 is reset, 1 is normal
else
RegisterBitToggle(REG__C0_SRST2,BIT__CEC_SRST);
RegisterWrite(REG__SLAVE_ADDR_EDID,CONF__I2C_SLAVE_PAGE_9);
RegisterWrite(REG__SLAVE_ADDR_CEC,CONF__I2C_SLAVE_PAGE_8);
// Set CEC device type = TV and logical address to capture.
InitiatorAddress = CEC_LOGADDR_UNREGORBC_MSG ;
if( CEC_CAPTURE_ID_Set( InitiatorAddress ) )
{
DEBUG_PRINT(("\n Cannot init CEC"));
}
//
// 4. Initialize Event Descriptor
//
CEC_event_descriptor_clear();
// Enumirate as an TV
bCECTask = SiI_CEC_Enumiration;
bEnumType = SiI_EnumTV;
#endif // #if(CONF__CEC_ENABLE == ENABLE)
//====================
// 5. Program EDID and set port specific address space.
// Program (a) EDID and (b) Physical address
//====================
ProgramEDID();
}
uint8_t SiI_CEC_SetCommand( SiI_CEC_t * pSiI_CEC )
{
uint8_t error = FALSE;
uint8_t cec_int_status_reg[2];
uint8_t sw_retry_counter = 0 ;
// Clear Tx Buffer
RegisterModify(REG__CEC_DEBUG_3, BIT_FLUSH_TX_FIFO, BIT_FLUSH_TX_FIFO);
DEBUG_PRINT(("\n TX: HDR[0x%02X],OPC[0x%02X],OPR[0x%02X, %02X, %02X]", (int)pSiI_CEC->bDestOrRXHeader, (int)pSiI_CEC->bOpcode, (int)pSiI_CEC->bOperand[0], (int)pSiI_CEC->bOperand[1], (int)pSiI_CEC->bOperand[2])) ;
#ifdef CEC_TX_AUTO_CALC_ENABLED
//
// Enable TX_AUTO_CALC
//
RegisterWrite(REG__CEC_TRANSMIT_DATA, BIT__TX_AUTO_CALC);
#endif// CEC_TX_AUTO_CALC_ENABLED
//
// Clear Tx-related buffers; write 1 to bits to be clear directly; writing 0 has no effect on the status bit
//
cec_int_status_reg[0] = 0x64 ; // Clear Tx Transmit Buffer Full Bit, Tx msg Sent Event Bit, and Tx FIFO Empty Event Bit
cec_int_status_reg[1] = 0x02 ; // Clear Tx Frame Retranmit Count Exceeded Bit.
RegisterWriteBlock(REG__CEC_INT_STATUS_0, cec_int_status_reg, 2);
// Write Source and Destination address
RegisterWrite(REG__CEC_TX_DEST,pSiI_CEC->bDestOrRXHeader);
// Send CEC Opcode AND up to 15 Operands
RegisterWriteBlock( REG__CEC_TX_COMMAND, &pSiI_CEC->bOpcode, pSiI_CEC->bCount + 1);
if( error )
{
DEBUG_PRINT(("\n SiI_CEC_SetCommand(): Fail to write CEC opcode and operands\n")) ;
}
#ifndef CEC_TX_AUTO_CALC_ENABLED
//
// Write Operand count and activate send
//
RegisterWrite(REG__CEC_TRANSMIT_DATA, BIT_TRANSMIT_CMD | pSiI_CEC->bCount );
#endif // CEC_TX_AUTO_CALC_ENABLED
return error;
}//e.o. uint8_t SiI_CEC_SetCommand( SiI_CEC_t * pSiI_CEC )
//------------------------------------------------------------------------------
// Function: ConfigureSelectedPort
// Description: Setup new input port after port change
//------------------------------------------------------------------------------
static void ConfigureSelectedPort(void)
{
switch (CurrentStatus.PortSelection)
{
case PORT_SELECT__PORT_0:
{
RegisterModify(REG__PORT_SWTCH2, MSK__PORT_EN,VAL__PORT0_EN); //select port 0
RegisterWrite(REG__PORT_SWTCH, BIT__DDC0_EN); //select DDC 0
HAL_VccEnable(ON);
}
break;
case PORT_SELECT__PORT_1:
{
RegisterModify(REG__PORT_SWTCH2, MSK__PORT_EN,VAL__PORT1_EN); //select port 1
RegisterWrite(REG__PORT_SWTCH, BIT__DDC1_EN); //select DDC 1
HAL_VccEnable(ON);
}
break;
case PORT_SELECT__PORT_2:
{
RegisterModify(REG__PORT_SWTCH2, MSK__PORT_EN,VAL__PORT2_EN); //select port 2
RegisterWrite(REG__PORT_SWTCH, BIT__DDC2_EN); //select DDC 2
HAL_VccEnable(ON);
}
break;
case PORT_SELECT__PORT_3:
{
RegisterModify(REG__PORT_SWTCH2, MSK__PORT_EN,VAL__PORT3_EN); //select port 3
RegisterWrite(REG__PORT_SWTCH, BIT__DDC3_EN); //select DDC 3
HAL_VccEnable(ON);
}
break;
case PORT_SELECT__PORT_7:
{
DEBUG_PRINT(("turn off 3V power! \n")); //power down
HAL_VccEnable(OFF);
}
break;
} //end of switch
}
/**
* Show lower 8 bits of integer value on LEDs
*
* @param ptr Base address of I/O
* @param value Value to show on LEDs
*/
void SetLedNumber(char *ptr, int value)
{
RegisterWrite(ptr, gpio_led1_offset, value % 2);
RegisterWrite(ptr, gpio_led2_offset, (value / 2) % 2);
RegisterWrite(ptr, gpio_led3_offset, (value / 4) % 2);
RegisterWrite(ptr, gpio_led4_offset, (value / 8) % 2);
RegisterWrite(ptr, gpio_led5_offset, (value / 16) % 2);
RegisterWrite(ptr, gpio_led6_offset, (value / 32) % 2);
RegisterWrite(ptr, gpio_led7_offset, (value / 64) % 2);
RegisterWrite(ptr, gpio_led8_offset, (value / 128) % 2);
}
void sii_set_hdmi_port(char port)
{
if( (port>=0) && (port<4) )
{
RegisterWrite(REG__PORT_SWTCH, (1<<(port+4)) );
RegisterModify(REG__PORT_SWTCH2, MSK__PORT_EN, port);
}
return ;
}
status_t
ArchMailboxArmBCM2835::Write(uint8 channel, uint32 value)
{
// We have to wait for the mailbox to drain if it is marked full.
while ((RegisterRead(ARM_MAILBOX_STATUS) & ARM_MAILBOX_FULL) != 0)
;
value &= ARM_MAILBOX_DATA_MASK;
RegisterWrite(ARM_MAILBOX_WRITE, value | channel);
return B_OK;
}
uint8_t PclkCheck(void)
{
uint8_t xpcnt0_0;
uint8_t xpcnt1_0;
uint8_t xpcnt0_1;
uint8_t xpcnt1_1;
uint8_t wrongzone = 0;
if((RegisterRead(REG__STATE))&BIT__PCLK_STABLE) //pclk stable
{
xpcnt0_0 = RegisterRead(0x06E);
xpcnt1_0 = RegisterRead(0x06F);
RegisterWrite(0x069,0x80); //change base
// DEBUG_PRINT(("full cnt=%02X %02X ",(int)xpcnt0_0, (int)xpcnt1_0));
xpcnt0_1 = RegisterRead(0x06E);
xpcnt1_1 = RegisterRead(0x06F);
// DEBUG_PRINT(("half cnt=%02X %02X\n",(int)xpcnt0_1, (int)xpcnt1_1));
RegisterWrite(0x069,0xFF);
if((xpcnt0_0==xpcnt0_1)&&(xpcnt1_0 <= xpcnt1_1)) //if xpcnt changes
wrongzone=1;
else
return TRUE;
}
else
{
wrongzone=1;
}
if(wrongzone==1)
{
DEBUG_PRINT(("pclk stopped"));
TurnVideoMute(ON);
CurrentStatus.ColorDepth = 0;
RegisterModify(REG__TMDS_CCTRL2, MSK__DC_CTL, VAL__DC_CTL_8BPP_1X);
}
return FALSE;
}
//------------------------------------------------------------------------------
// Function: SetUpAudioOutput
// Description: Setup registers for audio output formatting for each format (PCM, DSD, HBR)
// Each frmat has its own unique MCLK value.
// Only PCM and DSD support multi channel output.
//
// Notes: Compile time configuration is done using CONF__* defines in config.h
//------------------------------------------------------------------------------
static void SetUpAudioOutput(void)
{
uint8_t bAudioStatus;
bAudioStatus = RegisterRead(REG__AUDP_STAT);
if (bAudioStatus & BIT__DSD_STATUS) //DSD Audio
{
if(CurrentStatus.AudioMode!=AUDIO_MODE__DSD)
{
CurrentStatus.AudioMode = AUDIO_MODE__DSD;
RegisterWrite(REG__I2S_CTRL1, CONF__DSD__I2S_CTRL1);
if (bAudioStatus & BIT__HDMI_LO) //layout = 1, enable multi channel
RegisterWrite(REG__I2S_CTRL2, CONF__DSD__I2S_CTRL2__LAYOUT_1 | BIT__MCLKEN); //enable MCLK
else //layout = 0, enable 2 channel only
RegisterWrite(REG__I2S_CTRL2, CONF__DSD__I2S_CTRL2__LAYOUT_0 | BIT__MCLKEN); //enable MCLK
DEBUG_PRINT(("DSD aud\n"));
}
}
else if (bAudioStatus & BIT__HBRA_ON) //HBR Audio
{
CurrentStatus.AudioMode = AUDIO_MODE__HBR;
RegisterWrite(REG__I2S_CTRL1, CONF__HBR__I2S_CTRL1);
RegisterWrite(REG__I2S_CTRL2, CONF__HBR__I2S_CTRL2 | BIT__MCLKEN); //enable MCLK
DEBUG_PRINT(("HBR aud\n"));
}
else
{
if(CurrentStatus.AudioMode!=AUDIO_MODE__PCM)
{
CurrentStatus.AudioMode = AUDIO_MODE__PCM;
RegisterWrite(REG__I2S_CTRL1, CONF__PCM__I2S_CTRL1);
if (bAudioStatus & BIT__HDMI_LO) //layout = 1, enable multi channel
RegisterWrite(REG__I2S_CTRL2, CONF__PCM__I2S_CTRL2__LAYOUT_1 | BIT__MCLKEN); //enable MCLK
else //layout = 0, enable 2 channel only
RegisterWrite(REG__I2S_CTRL2, CONF__PCM__I2S_CTRL2__LAYOUT_0 | BIT__MCLKEN); //enable MCLK
DEBUG_PRINT(("PCM aud\n"));
}
}
}
//------------------------------------------------------------------------------
// Function: AutoVideoSetup
// Description: Setup registers for Auto Video Mode
//
// Notes: Compile time configuration is done using CONF__* defines in config.h
//------------------------------------------------------------------------------
static void AutoVideoSetup(void)
{
const uint8_t unmuteTimeConf[] = {0xFF,0x00,0x00,0xFF,0x00,0x00};
RegisterWriteBlock(REG__WAIT_CYCLE, (uint8_t *)&unmuteTimeConf[0],6); //video unmute wait
RegisterWrite(REG__VID_CTRL, (BIT__IVS & CONF__VSYNC_INVERT) |
(BIT__IHS & CONF__HSYNC_INVERT) ); //set HSYNC,VSNC polarity
RegisterWrite(REG__RPI_AUTO_CONFIG, BIT__CHECKSUM_EN|BIT__V_UNMUTE_EN|BIT__HCDP_EN|BIT__TERM_EN); //auto config
RegisterWrite(REG__SRST, BIT__SWRST_AUTO); //enable auto sw reset
RegisterWrite(REG__VID_AOF, CONF__OUTPUT_VIDEO_FORMAT); //set output video format
RegisterModify(REG__AEC_CTRL, BIT__AVC_EN, SET); //enable auto video configuration
#if (CONF__ODCK_LIMITED == ENABLE)
RegisterModify(REG__SYS_PSTOP, MSK__PCLK_MAX, CONF__PCLK_MAX_CNT);
#endif //(CONF__ODCK_LIMITED==ENABLE)
#if (PEBBLES_ES1_ZONE_WORKAROUND == ENABLE)
RegisterWrite(REG__AVC_EN2, BIT__AUTO_DC_CONF); //mask out auto configure deep color clock
RegisterWrite(REG__VIDA_XPCNT_EN, BIT__VIDA_XPCNT_EN); //en read xpcnt
#endif //(PEBBLES_ES1_ZONE_WORKAROUND == ENABLE)
#if (PEBBLES_STARTER_NO_CLK_DIVIDER == ENABLE)
RegisterModify(REG__AVC_EN2, BIT__AUTO_CLK_DIVIDER,SET); //msk out auto clk divider
#endif //(PEBBLES_STARTER_NO_CLK_DIVIDER == ENABLE)
}
DEMOD_STATUS cnxt_lnb_set_output_enable( NIM *pNIM, bool enable )
{
#if (INTERNAL_DEMOD == INTERNAL_COBRA_LIKE)
#else
#if RTOS != NOOS
int api_error;
#endif /* RTOS != NOOS */
#endif
/* Set up the LNB enable signal. It is different for internal/external. */
#if (INTERNAL_DEMOD == INTERNAL_COBRA_LIKE)
/* LNB enable signal is driven from the PIO expander; set to 1 to
enable, 0 to disable. */
cnxt_gpio_set_output_level( PIO_LNB_ENABLE, enable );
lnb_state.enabled = enable;
#else
/* Cobra GPIO4 is the enable for the external LNB signal generator;
set to 1 to enable, 0 to disable. */
if ( RegisterWrite( pNIM, CX24130_GPIO4VAL, enable ) == True )
{
lnb_state.enabled = enable;
}
else
{
#if RTOS != NOOS
trace_new( TL_ERROR,
"Cobra demod failed to write to LNB signal enable"
" (GPIO4).\n" );
trace_new( TL_ERROR, "File: %s, line: %d\n",
API_GetErrorFilename(pNIM),
API_GetErrorLineNumber(pNIM) );
api_error = API_GetLastError( pNIM );
trace_new( TL_ERROR, "Error %d, %s\n", api_error,
API_GetErrorMessage(pNIM, (APIERRNO)api_error) );
#endif /* RTOS != NOOS */
return DEMOD_ERROR;
}
#endif
return DEMOD_SUCCESS;
}
/**
* @brief 通讯接收数据解析函数
* @param comm : 通讯结构指针
* @param head : 数据指针
* @param len : 数据长度
* @retval None
*/
static void RxProcessor(NavipackComm_Type *comm, NaviPack_HeadType *head, u16 len)
{
if(head->deviceAddr == NAVIPACK_SLAVE_ID)
{
if((head->functionCode == FUNC_ID_WRITE_CONTROL
|| head->functionCode == FUNC_ID_WRITE_USER)
&& head->len != len - sizeof(NaviPack_HeadType))
{
return;
}
switch(head->functionCode)
{
case FUNC_ID_WRITE_CONTROL:
if(!RegisterWrite(head, (u8*)&comm->control, sizeof(comm->control), REG_ID_COTROL))
{
return;
}
break;
}
Navipack_RxCallback(comm, head);
}
}
//------------------------------------------------------------------------------
// Function: System_Init
// Description: One time initialization at statup
//------------------------------------------------------------------------------
static void SystemInit(void)
{
const uint8_t EQTable[] = {0x8A,0xAA,0x1A,0x2A};
while( (RegisterRead(REG__BSM_STAT)& BIT__BOOT_DONE )== 0) //wait done
DEBUG_PRINT(("BIT__BOOT_DONE = 0; \n"));
if((RegisterRead(REG__BSM_STAT)& BIT__BOOT_ERROR)!=0)
DEBUG_PRINT(("First Boot error! \n"));
RegisterModify(REG__HPD_HW_CTRL,MSK__INVALIDATE_ALL, SET); //disable auto HPD conf at RESET
TurnAudioMute(ON);
TurnVideoMute(ON);
#if(PEBBLES_ES1_STARTER_CONF==ENABLE)
RegisterWrite(REG__TERMCTRL2, VAL__45OHM); //1.term default value
RegisterWrite(REG__FACTORY_A87,0x43); //2.Set PLL mode to internal and set selcalrefg to F
RegisterWrite(REG__FACTORY_A81,0x18); //Set PLL zone to auto and set Div20 to 1
RegisterWrite(REG__DRIVE_CNTL,0x64); //3.change output strength,
RegisterWrite(REG__FACTORY_ABB,0x04); //4.desable DEC_CON
RegisterWriteBlock(REG__FACTORY_A92,(uint8_t *)&EQTable[0],4);//5.Repgrogram EQ table
RegisterWrite(REG__FACTORY_AB5,0x40); //EnableEQ
RegisterWrite(REG__FACTORY_9E5, 0x02); //6. DLL by pass
RegisterWrite(REG__FACTORY_A89,0x00); //7. configure the PLLbias
RegisterWrite(REG__FACTORY_00E,0x40); //for ES1.1 conf only
#endif
CEC_Init();
//set recommended values
RegisterWrite(REG__AACR_CFG1, CONF__AACR_CFG1_VALUE); //pll config #1
RegisterWrite(REG__CBUS_PAD_SC, VAL__SC_CONF); //CBUS slew rate
RegisterWrite(REG__SRST, BIT__SWRST_AUTO); //enable auto sw reset
RegisterWrite(REG__INFM_CLR,BIT__CLR_GBD|BIT__CLR_ACP); //clr GBD & ACP
RegisterWrite(REG__ECC_HDCP_THRES, CONF__HDCPTHRESH & 0xff); //HDCP threshold low uint8_t
RegisterWrite(REG__ECC_HDCP_THRES+1, (CONF__HDCPTHRESH>>8) & 0xff); //HDCP threshold high uint8_t
AutoVideoSetup();
AutoAudioSetup();
SetupInterruptMasks();
InitializePortSwitch();
TurnPowerDown(OFF);
RegisterModify(REG__HPD_HW_CTRL,MSK__INVALIDATE_ALL, CLEAR); //CLEAR disable auto HPD conf
/* Inti Hdmi Info frame related chip registers and data */
HdmiInitIf ();
}
//------------------------------------------------------------------------------
// Function: AudioUnmuteHandler
// Description: State machine for performing audio unmute in firmware.
//------------------------------------------------------------------------------
void AudioUnmuteHandler(void)
{
uint8_t bIntrStatus2;
uint8_t bIntrStatus4;
RegisterModify(REG__ECC_CTRL, BIT__CAPCNT, SET); //clear the error cont
switch (CurrentStatus.AudioState)
{
case STATE_AUDIO__REQUEST_AUDIO:
{
bIntrStatus2 = RegisterRead(REG__INTR2);
bIntrStatus4 = RegisterRead(REG__INTR4);
if ((bIntrStatus2 & BIT__GOTAUD) && (bIntrStatus2 & BIT__GOTCTS)) //audio stable
{
if(bIntrStatus4 & MSK__CTS_ERROR)
// reset ACR
RegisterBitToggle(REG__SRST, BIT__ACRRST);
else
{
// init ACR
RegisterWrite(REG__ACR_CTRL1, BIT__ACR_INIT);
DEBUG_PRINT(("aud rdy\n"));
SetUpAudioOutput();
CurrentStatus.AudioState = STATE_AUDIO__AUDIO_READY;
}
}
// clear all the audio interrupts
RegisterWrite(REG__INTR2, (BIT__GOTAUD | BIT__GOTCTS));
RegisterWrite(REG__INTR4, (MSK__CTS_ERROR | MSK__FIFO_ERROR));
TIMER_Set(TIMER__AUDIO, 20); // delay 20ms before request audio again
}
break;
case STATE_AUDIO__AUDIO_READY:
{
bIntrStatus4 = RegisterRead(REG__INTR4);
if(bIntrStatus4 & MSK__CTS_ERROR)
CurrentStatus.AudioState = STATE_AUDIO__REQUEST_AUDIO;
else if (!(bIntrStatus4 & MSK__FIFO_ERROR)) // no audio FIFO error
{
if ((CurrentStatus.VideoState == STATE_VIDEO__ON)
||(CurrentStatus.VideoState == STATE_VIDEO__CHECKED))
//||ResetVideoControl())//video unmute status ok
{
if(CurrentStatus.AudioMode==AUDIO_MODE__DSD)
HAL_SetAudioDACMode(AUDIO_MODE__DSD);
else
HAL_SetAudioDACMode(AUDIO_MODE__PCM);
RegisterWrite(REG__INTR5, MSK__AUDIO_INTR);// clear all audio interrupts
CurrentStatus.AudioState = STATE_AUDIO__ON;
TurnAudioMute(OFF);
}
}
else
{
// reset audio FIFO
RegisterBitToggle(REG__SRST, BIT__FIFORST);
// clear audio FIFO interrupts
RegisterWrite(REG__INTR4, MSK__FIFO_ERROR);
TIMER_Set(TIMER__AUDIO, 20); // delay 20ms before ready audio again
}
}
}
}
DEMOD_STATUS cnxt_lnb_init( NIM *pNIM )
{
#if (INTERNAL_DEMOD == INTERNAL_COBRA_LIKE)
#else
#if RTOS != NOOS
int api_error;
#endif /* RTOS != NOOS */
#endif
/* Set the PIO that controls the direction of the 22KHz signal for output
as the initial setting. Any DiSEqC input will need to change it. */
#if PIO_LNB_22KHZ_DIRECTION != GPIO_INVALID
/*
* !!! HACK ALERT !!!
* WARNING!!!!! Hack required to keep from setting this PIO on a
* Bronco1. When Bronco1 boards disappear, so should this hack. (PIO
* setting should become conditional only upon value of
* PIO_LNB_22KHZ_DIRECTION != GPIO_INVALID.)
* !!! HACK ALERT !!!
*/
#if I2C_CONFIG_EEPROM_ADDR != NOT_PRESENT
{
extern int ConfigurationValid;
extern CONFIG_TABLE config_table;
if ( ConfigurationValid &&
( config_table.board_type != 0x00 ||
((config_table.board_type == 0x00) &&
(config_table.board_rev != 0x01)) ) )
{
cnxt_gpio_set_output_level( PIO_LNB_22KHZ_DIRECTION, TRUE );
}
}
#endif
/*
* !!! HACK ALERT !!!
* !!! HACK ALERT !!!
*/
#endif
/* Set up directional control for the PIO controlling LNB enable. */
#if (INTERNAL_DEMOD == INTERNAL_COBRA_LIKE)
/* No direction control necessary. */
#else
/* Cobra GPIO4 is the enable for the external LNB signal generator;
set as an output. */
if ( RegisterWrite( pNIM, CX24130_GPIO4DIR, 1 ) != True )
{
#if RTOS != NOOS
trace_new( TL_ERROR,
"Cobra demod failed to set direction of LNB signal enable"
" (GPIO4).\n" );
trace_new( TL_ERROR, "File: %s, line: %d\n",
API_GetErrorFilename(pNIM),
API_GetErrorLineNumber(pNIM) );
api_error = API_GetLastError( pNIM );
trace_new( TL_ERROR, "Error %d, %s\n", api_error,
API_GetErrorMessage(pNIM, (APIERRNO)api_error) );
#endif /* RTOS != NOOS */
return DEMOD_ERROR;
}
#endif
/* Actually enable LNB output unless initialization with output disabled is
requested. */
#ifndef LNB_INITIALLY_DISABLED
cnxt_lnb_set_output_enable( pNIM, TRUE );
#endif
return DEMOD_SUCCESS;
}
//------------------------------------------------------------------------------
// Function Name: SiI_CEC_SendPing
// Function Description: This command intiate sending a ping, and used for checking available
// CEC devices
//
// Accepts: bCECLogAddr
// Returns: none
// Globals: none
//------------------------------------------------------------------------------
void SiI_CEC_SendPing ( uint8_t bCECLogAddr )
{
RegisterWrite( REG__CEC_TX_INIT, BIT_SEND_POLL | bCECLogAddr );
}
