MACHINE_RESET_MEMBER(namcos2_shared_state,namcos2)
{
// address_space &space = m_maincpu->space(AS_PROGRAM);
address_space &audio_space = m_audiocpu->space(AS_PROGRAM);
mFinalLapProtCount = 0;
namcos2_mcu_analog_ctrl = 0;
namcos2_mcu_analog_data = 0xaa;
namcos2_mcu_analog_complete = 0;
sendval = 0;
/* Initialise the bank select in the sound CPU */
namcos2_sound_bankselect_w(audio_space, 0, 0); /* Page in bank 0 */
m_audiocpu->set_input_line(INPUT_LINE_RESET, ASSERT_LINE );
/* Place CPU2 & CPU3 into the reset condition */
ResetAllSubCPUs( machine(), ASSERT_LINE );
/* Initialise interrupt handlers */
InitC148();
/* reset POSIRQ timer */
namcos2_posirq_timer->adjust(attotime::never);
m_player_mux = 0;
}
static UINT16
ReadWriteC148( address_space &space, offs_t offset, UINT16 data, int bWrite )
{
offs_t addr = ((offset * 2) + 0x1c0000) & 0x1fe000;
device_t *altcpu = NULL;
UINT16 *pC148Reg = NULL;
UINT16 *pC148RegAlt = NULL;
UINT16 result = 0;
if (&space.device() == space.machine().device("maincpu"))
{
pC148Reg = namcos2_68k_master_C148;
altcpu = space.machine().device("slave");
pC148RegAlt = namcos2_68k_slave_C148;
}
else if (&space.device() == space.machine().device("slave"))
{
pC148Reg = namcos2_68k_slave_C148;
altcpu = space.machine().device("maincpu");
pC148RegAlt = namcos2_68k_master_C148;
}
else if (&space.device() == space.machine().device("gpu"))
{
pC148Reg = namcos2_68k_gpu_C148;
altcpu = space.machine().device("maincpu");
pC148RegAlt = namcos2_68k_master_C148;
}
if( bWrite )
{
int reg = (addr >> 13) & 0x1f;
// If writing an IRQ priority register, clear any pending IRQs.
// Dirt Fox and Winning Run require this behaviour
if (reg < 8)
space.device().execute().set_input_line(pC148Reg[reg], CLEAR_LINE);
pC148Reg[reg] = data & 0x0007;
}
switch(addr)
{
case 0x1c0000: break; /* ? NAMCOS2_C148_0 */
case 0x1c2000: break; /* ? NAMCOS2_C148_1 */
case 0x1c4000: break; /* ? NAMCOS2_C148_2 */
/* IRQ level */
case 0x1c6000: break; /* NAMCOS2_C148_CPUIRQ */
case 0x1c8000: break; /* NAMCOS2_C148_EXIRQ */
case 0x1ca000: break; /* NAMCOS2_C148_POSIRQ */
case 0x1cc000: break; /* NAMCOS2_C148_SERIRQ */
case 0x1ce000: break; /* NAMCOS2_C148_VBLANKIRQ */
case 0x1d0000: /* ? NAMCOS2_C148_0 */
if( bWrite )
{
// mame_printf_debug( "cpu(%d) RAM[0x%06x] = 0x%x\n", cpu, addr, data );
/* Dubious to assert IRQ for other CPU here, but Starblade seems to rely on it.
It fails to show large polygons otherwise. */
altcpu->execute().set_input_line(pC148RegAlt[NAMCOS2_C148_CPUIRQ], ASSERT_LINE);
}
break;
case 0x1d2000: break; /* ? NAMCOS2_C148_1 */
case 0x1d4000: /* ? NAMCOS2_C148_2 */
if( bWrite )
{
// mame_printf_debug( "cpu(%d) RAM[0x%06x] = 0x%x\n", cpu, addr, data );
/* Dubious to assert IRQ for other CPU here: Rolling Thunder 2 and Fine Hour break. */
// altcpu->execute().set_input_line(pC148RegAlt[NAMCOS2_C148_CPUIRQ], ASSERT_LINE);
}
break;
/* IRQ ack */
case 0x1d6000: /* NAMCOS2_C148_CPUIRQ */
// if( bWrite ) mame_printf_debug( "cpu(%d) RAM[0x%06x] = 0x%x\n", cpu, addr, data );
space.device().execute().set_input_line(pC148Reg[NAMCOS2_C148_CPUIRQ], CLEAR_LINE);
break;
case 0x1d8000: /* NAMCOS2_C148_EXIRQ */
// if( bWrite ) mame_printf_debug( "cpu(%d) RAM[0x%06x] = 0x%x\n", cpu, addr, data );
space.device().execute().set_input_line(pC148Reg[NAMCOS2_C148_EXIRQ], CLEAR_LINE);
break;
case 0x1da000: /* NAMCOS2_C148_POSIRQ */
// if( bWrite ) mame_printf_debug( "cpu(%d) RAM[0x%06x] = 0x%x\n", cpu, addr, data );
space.device().execute().set_input_line(pC148Reg[NAMCOS2_C148_POSIRQ], CLEAR_LINE);
break;
case 0x1dc000: /* NAMCOS2_C148_SERIRQ */
// if( bWrite ) mame_printf_debug( "cpu(%d) RAM[0x%06x] = 0x%x\n", cpu, addr, data );
space.device().execute().set_input_line(pC148Reg[NAMCOS2_C148_SERIRQ], CLEAR_LINE);
break;
case 0x1de000: /* NAMCOS2_C148_VBLANKIRQ */
space.device().execute().set_input_line(pC148Reg[NAMCOS2_C148_VBLANKIRQ], CLEAR_LINE);
break;
case 0x1e0000: /* EEPROM Status Register */
result = ~0; /* Only BIT0 used: 1=EEPROM READY 0=EEPROM BUSY */
break;
case 0x1e2000: /* Sound CPU Reset control */
if (&space.device() == space.machine().device("maincpu")) /* ? */
{
if (data & 0x01)
{
/* Resume execution */
space.machine().device("audiocpu")->execute().set_input_line(INPUT_LINE_RESET, CLEAR_LINE);
space.device().execute().yield();
}
else
{
/* Suspend execution */
space.machine().device("audiocpu")->execute().set_input_line(INPUT_LINE_RESET, ASSERT_LINE);
}
if (namcos2_kickstart != NULL)
{
//printf( "dspkick=0x%x\n", data );
if (data & 0x04)
{
(*namcos2_kickstart)(space.machine(), 1);
}
}
}
break;
case 0x1e4000: /* Alt 68000 & IO CPU Reset */
if (&space.device() == space.machine().device("maincpu")) /* ? */
{
if (data & 0x01)
{ /* Resume execution */
ResetAllSubCPUs(space.machine(), CLEAR_LINE);
/* Give the new CPU an immediate slice of the action */
space.device().execute().yield();
}
else
{ /* Suspend execution */
ResetAllSubCPUs(space.machine(), ASSERT_LINE);
}
}
break;
case 0x1e6000: /* Watchdog reset kicker */
/* watchdog_reset_w(0,0); */
break;
default:
break;
}
return result;
}
static UINT16
ReadWriteC148( int cpu, offs_t offset, UINT16 data, int bWrite )
{
offs_t addr = ((offset*2)+0x1c0000)&0x1fe000;
UINT16 *pC148Reg = NULL;
UINT16 *pC148RegAlt = NULL;
UINT16 result = 0;
int altCPU = 0;
switch( cpu )
{
case CPU_MASTER:
pC148Reg = namcos2_68k_master_C148;
altCPU = CPU_SLAVE;
pC148RegAlt = namcos2_68k_slave_C148;
break;
case CPU_SLAVE:
pC148Reg = namcos2_68k_slave_C148;
altCPU = CPU_MASTER;
pC148RegAlt = namcos2_68k_master_C148;
break;
case CPU_GPU:
pC148Reg = namcos2_68k_gpu_C148;
altCPU = CPU_MASTER;
pC148RegAlt = namcos2_68k_master_C148;
break;
}
if( bWrite )
{
pC148Reg[(addr>>13)&0x1f] = data&0x0007;
}
switch(addr)
{
case 0x1c0000: break; /* NAMCOS2_C148_0 level */
case 0x1c2000: break; /* NAMCOS2_C148_1 level */
case 0x1c4000: break; /* NAMCOS2_C148_2 level */
case 0x1c6000: break; /* NAMCOS2_C148_CPUIRQ level */
case 0x1c8000: break; /* NAMCOS2_C148_EXIRQ level */
case 0x1ca000: break; /* NAMCOS2_C148_POSIRQ level */
case 0x1cc000: break; /* NAMCOS2_C148_SERIRQ level */
case 0x1ce000: break; /* NAMCOS2_C148_VBLANKIRQ level */
case 0x1d0000:
if( bWrite )
{
cpunum_set_input_line(altCPU, pC148RegAlt[NAMCOS2_C148_CPUIRQ], ASSERT_LINE);
} cpunum_set_input_line(cpu, pC148Reg[NAMCOS2_C148_0], CLEAR_LINE);
break;
case 0x1d2000:
cpunum_set_input_line(cpu, pC148Reg[NAMCOS2_C148_1], CLEAR_LINE);
break;
case 0x1d4000:
if( bWrite )
{
cpunum_set_input_line(altCPU, pC148RegAlt[NAMCOS2_C148_CPUIRQ], ASSERT_LINE);
}
cpunum_set_input_line(cpu, pC148Reg[NAMCOS2_C148_2], CLEAR_LINE);
break;
case 0x1d6000:
if( bWrite )
{
// mame_printf_debug( "cpu(%d) RAM[0x%06x] = 0x%x\n", cpu, addr, data );
}
cpunum_set_input_line(cpu, pC148Reg[NAMCOS2_C148_CPUIRQ], CLEAR_LINE);
break;
case 0x1d8000: /* ack EXIRQ */
if( bWrite )
{
// mame_printf_debug( "cpu(%d) RAM[0x%06x] = 0x%x\n", cpu, addr, data );
}
cpunum_set_input_line(cpu, pC148Reg[NAMCOS2_C148_EXIRQ], CLEAR_LINE);
break;
case 0x1da000: /* ack POSIRQ */
if( bWrite )
{
// mame_printf_debug( "cpu(%d) RAM[0x%06x] = 0x%x\n", cpu, addr, data );
}
cpunum_set_input_line(cpu, pC148Reg[NAMCOS2_C148_POSIRQ], CLEAR_LINE);
break;
case 0x1dc000: /* ack SCIRQ */
if( bWrite )
{
// mame_printf_debug( "cpu(%d) RAM[0x%06x] = 0x%x\n", cpu, addr, data );
}
cpunum_set_input_line(cpu, pC148Reg[NAMCOS2_C148_SERIRQ], CLEAR_LINE);
break;
case 0x1de000: /* ack VBLANK */
cpunum_set_input_line(cpu, pC148Reg[NAMCOS2_C148_VBLANKIRQ], CLEAR_LINE);
break;
case 0x1e0000: /* EEPROM Status Register */
result = ~0; /* Only BIT0 used: 1=EEPROM READY 0=EEPROM BUSY */
break;
case 0x1e2000: /* Sound CPU Reset control */
if( cpu == CPU_MASTER ) /* ? */
{
if( data&0x01 )
{
/* Resume execution */
cpunum_set_input_line(CPU_SOUND, INPUT_LINE_RESET, CLEAR_LINE);
cpu_yield();
}
else
{
/* Suspend execution */
cpunum_set_input_line(CPU_SOUND, INPUT_LINE_RESET, ASSERT_LINE);
}
if( IsSystem21() )
{
//printf( "dspkick=0x%x\n", data );
if( data&4 )
{
namcos21_kickstart(1);
}
}
}
break;
case 0x1e4000: /* Alt 68000 & IO CPU Reset */
if( cpu == CPU_MASTER ) /* ? */
{
if( data&0x01 )
{ /* Resume execution */
ResetAllSubCPUs( CLEAR_LINE );
/* Give the new CPU an immediate slice of the action */
cpu_yield();
}
else
{ /* Suspend execution */
ResetAllSubCPUs( ASSERT_LINE );
}
}
break;
case 0x1e6000: /* Watchdog reset kicker */
/* watchdog_reset_w(0,0); */
break;
default:
break;
}
return result;
}
