/**
* FchXhciInitIndirectReg - Config XHCI Indirect Registers
*
*
*
* @param[in] StdHeader AMD Standard Header
* @param[in] FchRevision FCH Chip revision
*
*/
VOID
FchXhciRecoveryInitIndirectReg (
IN AMD_CONFIG_PARAMS *StdHeader,
IN UINT8 FchRevision
)
{
UINT8 Index;
UINT32 DrivingStrength;
UINT32 Port;
UINT32 Register;
UINT32 RegValue;
UINT32 Xhci20Phy[MAX_XHCI_PORTS];
Xhci20Phy[0] = 0x21;
Xhci20Phy[1] = 0x21;
Xhci20Phy[2] = 0x24;
Xhci20Phy[3] = 0x24;
DrivingStrength = 0;
//
// SuperSpeed PHY Configuration (adaptation mode setting)
//
RwXhciIndReg ( FCH_XHCI_IND_REG94, 0xFFFFFC00, 0x00000021, StdHeader);
RwXhciIndReg ( FCH_XHCI_IND_REGD4, 0xFFFFFC00, 0x00000021, StdHeader);
//
// BLM Meaasge
//
RwXhciIndReg ( FCH_XHCI_IND_REG00, 0xF8FFFFFF, 0x07000000, StdHeader);
//
// xHCI USB 2.0 PHY Settings
// Step 1 is done by hardware default
// Step 2
for (Port = 0; Port < 2; Port ++) {
DrivingStrength = (UINT32) (Xhci20Phy[Port]);
RwXhci0IndReg ( FCH_XHCI_IND60_REG00, 0xFFFFC000, (Port << 13) + BIT12 + DrivingStrength, StdHeader);
RwXhci0IndReg ( FCH_XHCI_IND60_REG00, 0xFFFFC000, (Port << 13) + DrivingStrength, StdHeader);
RwXhci0IndReg ( FCH_XHCI_IND60_REG00, 0xFFFFC000, (Port << 13) + BIT12 + DrivingStrength, StdHeader);
}
RwXhci0IndReg ( FCH_XHCI_IND60_REG50, ~ ((UINT32) (0x0f)), ((UINT32) (0x07)), StdHeader);
RwXhci0IndReg ( FCH_XHCI_IND60_REG0C, ~ ((UINT32) (0x0f << 4)), ((UINT32) (0x02 << 4)), StdHeader);
RwXhci0IndReg ( FCH_XHCI_IND60_REG0C, ~ ((UINT32) (0x0f << 8)), ((UINT32) (0x02 << 8)), StdHeader);
RwXhci0IndReg ( FCH_XHCI_IND60_REG08, 0x80FC00FF, 0, StdHeader);
// RPR 8.25 Clock Gating in PHY
for (Port = 0; Port < 4; Port ++) {
DrivingStrength = 0x1E4;
if (Port < 2) {
RwXhci0IndReg ( FCH_XHCI_IND60_REG00, 0xFFFE0000, (Port << 13) + BIT12 + DrivingStrength, StdHeader);
Register = FCH_XHCI_IND60_REG00;
Index = 0;
do {
WritePci ((USB_XHCI_BUS_DEV_FUN << 16) + 0x48, AccessWidth32, &Register, StdHeader);
ReadPci ((USB_XHCI_BUS_DEV_FUN << 16) + 0x4C, AccessWidth32, &RegValue, StdHeader);
Index++;
FchStall (10, StdHeader);
} while ((RegValue & BIT17) && (Index < 10 ));
RwXhci0IndReg ( FCH_XHCI_IND60_REG00, 0xFFFE0000, (Port << 13) + DrivingStrength, StdHeader);
Register = FCH_XHCI_IND60_REG00;
Index = 0;
do {
WritePci ((USB_XHCI_BUS_DEV_FUN << 16) + 0x48, AccessWidth32, &Register, StdHeader);
ReadPci ((USB_XHCI_BUS_DEV_FUN << 16) + 0x4C, AccessWidth32, &RegValue, StdHeader);
Index++;
FchStall (10, StdHeader);
} while ((RegValue & BIT17) && (Index < 10 ));
RwXhci0IndReg ( FCH_XHCI_IND60_REG00, 0xFFFE0000, (Port << 13) + BIT12 + DrivingStrength, StdHeader);
}
}
// Enhance XHC LS Rise time
for (Port = 0; Port < 2; Port ++) {
DrivingStrength = 0x1C4;
RwXhci0IndReg ( FCH_XHCI_IND60_REG00, 0xFFFFC000, (Port << 13) + BIT12 + DrivingStrength, StdHeader);
RwXhci0IndReg ( FCH_XHCI_IND60_REG00, 0xFFFFC000, (Port << 13) + DrivingStrength, StdHeader);
RwXhci0IndReg ( FCH_XHCI_IND60_REG00, 0xFFFFC000, (Port << 13) + BIT12 + DrivingStrength, StdHeader);
}
RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REGB4, AccessWidth32, ~(BIT23), BIT23);
// XHCI ISO device CRC false error detection
for (Port = 0; Port < 4; Port ++) {
if (Port < 2) {
ReadXhci0Phy (Port, (0x7 << 7), &DrivingStrength, StdHeader);
DrivingStrength &= 0x0000000F8;
DrivingStrength |= BIT0 + BIT2;
RwXhci0IndReg ( FCH_XHCI_IND60_REG00, 0xFFFFC000, (Port << 13) + BIT12 + (0x7 << 7) + DrivingStrength, StdHeader);
RwXhci0IndReg ( FCH_XHCI_IND60_REG00, 0xFFFFC000, (Port << 13) + (0x7 << 7) + DrivingStrength, StdHeader);
RwXhci0IndReg ( FCH_XHCI_IND60_REG00, 0xFFFFC000, (Port << 13) + BIT12 + (0x7 << 7) + DrivingStrength, StdHeader);
}
}
// L1 Residency Duration
RwXhci0IndReg ( FCH_XHCI_IND60_REG48, 0xFFFFFFFE0, BIT0, StdHeader);
}
/**
* FchXhciInitIndirectReg - Config XHCI Indirect Registers
*
*
*
* @param[in] FchDataPtr Fch configuration structure pointer.
*
*/
VOID
FchXhciInitIndirectReg (
IN FCH_DATA_BLOCK *FchDataPtr
)
{
UINT8 Index;
UINT32 DrivingStrength;
UINT32 Port;
UINT32 Register;
UINT32 RegValue;
FCH_DATA_BLOCK *LocalCfgPtr;
AMD_CONFIG_PARAMS *StdHeader;
LocalCfgPtr = (FCH_DATA_BLOCK *)FchDataPtr;
StdHeader = LocalCfgPtr->StdHeader;
DrivingStrength = 0;
//
// SuperSpeed PHY Configuration (adaptation mode setting)
//
RwXhciIndReg ( FCH_XHCI_IND_REG94, 0xFFFFFC00, 0x00000021, StdHeader);
RwXhciIndReg ( FCH_XHCI_IND_REGD4, 0xFFFFFC00, 0x00000021, StdHeader);
//
// SuperSpeed PHY Configuration (CR phase and frequency filter settings)
//
RwXhciIndReg ( FCH_XHCI_IND_REG98, 0xFFFFFFC0, 0x0000000A, StdHeader);
RwXhciIndReg ( FCH_XHCI_IND_REGD8, 0xFFFFFFC0, 0x0000000A, StdHeader);
//
// BLM Meaasge
//
RwXhciIndReg ( FCH_XHCI_IND_REG00, 0xF8FFFFFF, 0x07000000, StdHeader);
//
// xHCI USB 2.0 PHY Settings
// Step 1 is done by hardware default
// Step 2
for (Port = 0; Port < 4; Port ++) {
DrivingStrength = (UINT32) (LocalCfgPtr->Usb.Xhci20Phy[Port]);
if (Port < 2) {
RwXhci0IndReg ( FCH_XHCI_IND60_REG00, 0xFFFFC000, (Port << 13) + BIT12 + DrivingStrength, StdHeader);
RwXhci0IndReg ( FCH_XHCI_IND60_REG00, 0xFFFFC000, (Port << 13) + DrivingStrength, StdHeader);
RwXhci0IndReg ( FCH_XHCI_IND60_REG00, 0xFFFFC000, (Port << 13) + BIT12 + DrivingStrength, StdHeader);
} else {
RwXhci1IndReg ( FCH_XHCI_IND60_REG00, 0xFFFFC000, ((Port - 2) << 13) + BIT12 + DrivingStrength, StdHeader);
RwXhci1IndReg ( FCH_XHCI_IND60_REG00, 0xFFFFC000, ((Port - 2) << 13) + DrivingStrength, StdHeader);
RwXhci1IndReg ( FCH_XHCI_IND60_REG00, 0xFFFFC000, ((Port - 2) << 13) + BIT12 + DrivingStrength, StdHeader);
}
}
// Step 3
RwXhciIndReg ( FCH_XHCI_IND60_REG0C, ~ ((UINT32) (0x0f << 8)), ((UINT32) (0x02 << 8)), StdHeader);
RwXhciIndReg ( FCH_XHCI_IND60_REG08, ~ ((UINT32) (0xff << 8)), ((UINT32) (0x0f << 8)), StdHeader);
// RPR 8.25 Clock Gating in PHY
for (Port = 0; Port < 4; Port ++) {
DrivingStrength = 0x1E4;
if (Port < 2) {
RwXhci0IndReg ( FCH_XHCI_IND60_REG00, 0xFFFE0000, (Port << 13) + BIT12 + DrivingStrength, StdHeader);
Register = FCH_XHCI_IND60_REG00;
Index = 0;
do {
WritePci ((USB_XHCI_BUS_DEV_FUN << 16) + 0x48, AccessWidth32, &Register, StdHeader);
ReadPci ((USB_XHCI_BUS_DEV_FUN << 16) + 0x4C, AccessWidth32, &RegValue, StdHeader);
Index++;
FchStall (10, StdHeader);
} while ((RegValue & BIT17) && (Index < 10 ));
RwXhci0IndReg ( FCH_XHCI_IND60_REG00, 0xFFFE0000, (Port << 13) + DrivingStrength, StdHeader);
Register = FCH_XHCI_IND60_REG00;
Index = 0;
do {
WritePci ((USB_XHCI_BUS_DEV_FUN << 16) + 0x48, AccessWidth32, &Register, StdHeader);
ReadPci ((USB_XHCI_BUS_DEV_FUN << 16) + 0x4C, AccessWidth32, &RegValue, StdHeader);
Index++;
FchStall (10, StdHeader);
} while ((RegValue & BIT17) && (Index < 10 ));
RwXhci0IndReg ( FCH_XHCI_IND60_REG00, 0xFFFE0000, (Port << 13) + BIT12 + DrivingStrength, StdHeader);
} else {
RwXhci1IndReg ( FCH_XHCI_IND60_REG00, 0xFFFE0000, ((Port - 2) << 13) + BIT12 + DrivingStrength, StdHeader);
Register = FCH_XHCI_IND60_REG00;
Index = 0;
do {
WritePci ((USB_XHCI1_BUS_DEV_FUN << 16) + 0x48, AccessWidth32, &Register, StdHeader);
ReadPci ((USB_XHCI1_BUS_DEV_FUN << 16) + 0x4C, AccessWidth32, &RegValue, StdHeader);
Index++;
FchStall (10, StdHeader);
} while ((RegValue & BIT17) && (Index < 10 ));
RwXhci1IndReg ( FCH_XHCI_IND60_REG00, 0xFFFE0000, ((Port - 2) << 13) + DrivingStrength, StdHeader);
Register = FCH_XHCI_IND60_REG00;
Index = 0;
do {
WritePci ((USB_XHCI1_BUS_DEV_FUN << 16) + 0x48, AccessWidth32, &Register, StdHeader);
ReadPci ((USB_XHCI1_BUS_DEV_FUN << 16) + 0x4C, AccessWidth32, &RegValue, StdHeader);
Index++;
FchStall (10, StdHeader);
} while ((RegValue & BIT17) && (Index < 10 ));
RwXhci1IndReg ( FCH_XHCI_IND60_REG00, 0xFFFE0000, ((Port - 2) << 13) + BIT12 + DrivingStrength, StdHeader);
}
}
if ( ReadFchChipsetRevision ( StdHeader ) >= FCH_BOLTON ) {
// RRG 8.36 Enhance XHC LS Rise time
for (Port = 0; Port < 2; Port ++) {
DrivingStrength = 0x1C4;
RwXhciIndReg ( FCH_XHCI_IND60_REG00, 0xFFFFC000, (Port << 13) + BIT12 + DrivingStrength, StdHeader);
RwXhciIndReg ( FCH_XHCI_IND60_REG00, 0xFFFFC000, (Port << 13) + DrivingStrength, StdHeader);
RwXhciIndReg ( FCH_XHCI_IND60_REG00, 0xFFFFC000, (Port << 13) + BIT12 + DrivingStrength, StdHeader);
}
RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REGB4, AccessWidth32, ~(UINT32) (BIT23), BIT23);
// RPR 8.61 XHCI ISO device CRC false error detection
for (Port = 0; Port < 4; Port ++) {
if (Port < 2) {
ReadXhci0Phy (Port, (0x7 << 7), &DrivingStrength, StdHeader);
DrivingStrength &= 0x0000000F8;
DrivingStrength |= BIT0 + BIT2;
RwXhci0IndReg ( FCH_XHCI_IND60_REG00, 0xFFFFC000, (Port << 13) + BIT12 + (0x7 << 7) + DrivingStrength, StdHeader);
RwXhci0IndReg ( FCH_XHCI_IND60_REG00, 0xFFFFC000, (Port << 13) + (0x7 << 7) + DrivingStrength, StdHeader);
RwXhci0IndReg ( FCH_XHCI_IND60_REG00, 0xFFFFC000, (Port << 13) + BIT12 + (0x7 << 7) + DrivingStrength, StdHeader);
} else {
ReadXhci1Phy ((Port - 2), (0x7 << 7), &DrivingStrength, StdHeader);
DrivingStrength &= 0x0000000F8;
DrivingStrength |= BIT0 + BIT2;
RwXhci1IndReg ( FCH_XHCI_IND60_REG00, 0xFFFFC000, ((Port - 2) << 13) + BIT12 + (0x7 << 7) + DrivingStrength, StdHeader);
RwXhci1IndReg ( FCH_XHCI_IND60_REG00, 0xFFFFC000, ((Port - 2) << 13) + (0x7 << 7) + DrivingStrength, StdHeader);
RwXhci1IndReg ( FCH_XHCI_IND60_REG00, 0xFFFFC000, ((Port - 2) << 13) + BIT12 + (0x7 << 7) + DrivingStrength, StdHeader);
}
}
//8.64 L1 Residency Duration
RwXhciIndReg ( FCH_XHCI_IND60_REG48, 0xFFFFFFFE0, BIT0, StdHeader);
}
}
/**
* FchXhciInitIndirectReg - Config XHCI Indirect Registers
*
*
*
* @param[in] StdHeader AMD Standard Header
*
*/
VOID
FchXhciInitIndirectReg (
IN AMD_CONFIG_PARAMS *StdHeader
)
{
UINT32 DrivingStrength;
UINT32 Port;
UINT32 Register;
UINT32 RegValue;
UINT8 Index;
DrivingStrength = 0;
Port = 0;
//
// SuperSpeed PHY Configuration (adaptation mode setting)
//
RwXhciIndReg ( FCH_XHCI_IND_REG94, 0xFFFFFC00, 0x00000021, StdHeader);
RwXhciIndReg ( FCH_XHCI_IND_REGD4, 0xFFFFFC00, 0x00000021, StdHeader);
//
// SuperSpeed PHY Configuration (CR phase and frequency filter settings)
//
RwXhciIndReg ( FCH_XHCI_IND_REG98, 0xFFFFFFC0, 0x0000000A, StdHeader);
RwXhciIndReg ( FCH_XHCI_IND_REGD8, 0xFFFFFFC0, 0x0000000A, StdHeader);
//
// BLM Meaasge
//
RwXhciIndReg ( FCH_XHCI_IND_REG00, 0xF8FFFFFF, 0x07000000, StdHeader);
//
// xHCI USB 2.0 PHY Settings
// Step 1 is done by hardware default
// Step 2
for (Port = 0; Port < 4; Port ++) {
DrivingStrength = BIT2;
if (Port < 2) {
RwXhci0IndReg ( FCH_XHCI_IND60_REG00, 0xFFFE1E78, (Port << 13) + DrivingStrength, StdHeader);
RwXhci0IndReg ( FCH_XHCI_IND60_REG00, 0xFFFE1E78, (Port << 13) + BIT8 + BIT7 + DrivingStrength, StdHeader);
RwXhci0IndReg ( FCH_XHCI_IND60_REG00, 0xFFFE0E78, (Port << 13) + BIT8 + BIT7 + DrivingStrength, StdHeader);
Register = FCH_XHCI_IND60_REG00;
Index = 0;
do {
WritePci ((USB_XHCI_BUS_DEV_FUN << 16) + 0x48, AccessWidth32, &Register, StdHeader);
ReadPci ((USB_XHCI_BUS_DEV_FUN << 16) + 0x4C, AccessWidth32, &RegValue, StdHeader);
Index++;
FchStall (10, StdHeader);
} while ((RegValue & BIT17) && (Index < 10 ));
RwXhci0IndReg ( FCH_XHCI_IND60_REG00, 0xFFFFEFFF, 0x00001000, StdHeader);
} else {
RwXhci1IndReg ( FCH_XHCI_IND60_REG00, 0xFFFE1E78, ((Port - 2) << 13) + DrivingStrength, StdHeader);
RwXhci1IndReg ( FCH_XHCI_IND60_REG00, 0xFFFE1E78, ((Port - 2) << 13) + BIT8 + BIT7 + DrivingStrength, StdHeader);
RwXhci1IndReg ( FCH_XHCI_IND60_REG00, 0xFFFE0E78, ((Port - 2) << 13) + BIT8 + BIT7 + DrivingStrength, StdHeader);
Register = FCH_XHCI_IND60_REG00;
Index = 0;
do {
WritePci ((USB_XHCI1_BUS_DEV_FUN << 16) + 0x48, AccessWidth32, &Register, StdHeader);
ReadPci ((USB_XHCI1_BUS_DEV_FUN << 16) + 0x4C, AccessWidth32, &RegValue, StdHeader);
Index++;
FchStall (10, StdHeader);
} while ((RegValue & BIT17) && (Index < 10 ));
RwXhci1IndReg ( FCH_XHCI_IND60_REG00, 0xFFFFEFFF, 0x00001000, StdHeader);
}
}
// Step 3
RwXhciIndReg ( FCH_XHCI_IND60_REG0C, ~ ((UINT32) (0x0f << 8)), ((UINT32) (0x02 << 8)), StdHeader);
RwXhciIndReg ( FCH_XHCI_IND60_REG08, ~ ((UINT32) (0xff << 8)), ((UINT32) (0x0f << 8)), StdHeader);
}