static void s3c2443_rtc_setfreq(struct s3c_rtc *info, int freq)
{
unsigned int tmp = 0;
int val;
tmp = readb(info->base + S3C2410_TICNT);
tmp &= S3C2410_TICNT_ENABLE;
val = (info->rtc->max_user_freq / freq) - 1;
tmp |= S3C2443_TICNT_PART(val);
writel(S3C2443_TICNT1_PART(val), info->base + S3C2443_TICNT1);
writel(tmp, info->base + S3C2410_TICNT);
}
static int s3c_rtc_setfreq(struct rtc_device *rtc_dev, int freq)
{
//struct platform_device *pdev = to_platform_device(dev);
//struct rtc_device *rtc_dev = platform_get_drvdata(pdev);
unsigned int tmp = 0;
int val;
if (!is_power_of_2(freq)) {
return -EINVAL;
}
clk_enable(rtc_clk);
spin_lock_irq(&s3c_rtc_pie_lock);
if (s3c_rtc_cpu_type != TYPE_S3C64XX) {
tmp = readb(s3c_rtc_base + S3C2410_TICNT);
tmp &= S3C2410_TICNT_ENABLE;
}
//val = (rtc_dev->max_user_freq / freq) - 1;
val = udiv32(max_user_freq, freq) - 1;
if (s3c_rtc_cpu_type == TYPE_S3C2416
|| s3c_rtc_cpu_type == TYPE_S3C2443) {
tmp |= S3C2443_TICNT_PART(val);
writel(S3C2443_TICNT1_PART(val), s3c_rtc_base + S3C2443_TICNT1);
if (s3c_rtc_cpu_type == TYPE_S3C2416)
writel(S3C2416_TICNT2_PART(val),
s3c_rtc_base + S3C2416_TICNT2);
} else {
tmp |= val;
}
writel(tmp, s3c_rtc_base + S3C2410_TICNT);
spin_unlock_irq(&s3c_rtc_pie_lock);
clk_disable(rtc_clk);
return 0;
}