/*
* reset the cpu by setting up the watchdog timer and let him time out
*/
void reset_cpu (ulong ignored)
{
volatile S3C24X0_WATCHDOG * watchdog;
#ifdef CONFIG_TRAB
extern void disable_vfd (void);
disable_vfd();
#endif
watchdog = S3C24X0_GetBase_WATCHDOG();
/* Disable watchdog */
watchdog->WTCON = 0x0000;
/* Initialize watchdog timer count register */
watchdog->WTCNT = 0x0001;
/* Enable watchdog timer; assert reset at timer timeout */
watchdog->WTCON = 0x0021;
while(1); /* loop forever and wait for reset to happen */
/*NOTREACHED*/
}
void Timer_StartEx(void)
{
S3C24X0_WATCHDOG * const wdtregs = S3C24X0_GetBase_WATCHDOG();
wdtregs->WTCON=((get_PCLK()/1000000-1)<<8)|(0<<3)|(1<<2); // 16us
wdtregs->WTDAT=0xffff;
wdtregs->WTCNT=0xffff;
// 1/16/(65+1),interrupt enable,reset disable,watchdog enable
wdtregs->WTCON=((get_PCLK()/1000000-1)<<8)|(0<<3)|(1<<2)|(0<<0)|(1<<5);
}
unsigned int Timer_StopEx(void)
{
int count;
S3C24X0_WATCHDOG * const wdtregs = S3C24X0_GetBase_WATCHDOG();
wdtregs->WTCON=((get_PCLK()/1000000-1)<<8);
intregs->INTMSK|=BIT_WDT_AC97; //BIT_WDT;
intregs->INTSUBMSK |= (1<<13);
count=(0xffff-wdtregs->WTCNT)+(intCount*0xffff);
return ((unsigned int)count*16/1000000);
}
/*disable watchdog*/
void disable_watch_dog()
{
S3C24X0_WATCHDOG *const watchdog = S3C24X0_GetBase_WATCHDOG();
watchdog->WTCON = 0;
}
