static int s3c64xx_pcm_cfg_gpio(struct platform_device *pdev)
{
printk("bs pdev->id=%d %s %s:%d",pdev->id,__func__,__FILE__,__LINE__);//
switch (pdev->id) {
case 0:
s3c_gpio_cfgpin(S3C64XX_GPD(0), S3C64XX_GPD0_PCM0_SCLK);
s3c_gpio_cfgpin(S3C64XX_GPD(1), S3C64XX_GPD1_PCM0_EXTCLK);
s3c_gpio_cfgpin(S3C64XX_GPD(2), S3C64XX_GPD2_PCM0_FSYNC);
s3c_gpio_cfgpin(S3C64XX_GPD(3), S3C64XX_GPD3_PCM0_SIN);
s3c_gpio_cfgpin(S3C64XX_GPD(4), S3C64XX_GPD4_PCM0_SOUT);
break;
case 1:
s3c_gpio_cfgpin(S3C64XX_GPE(0), S3C64XX_GPE0_PCM1_SCLK);
s3c_gpio_cfgpin(S3C64XX_GPE(1), S3C64XX_GPE1_PCM1_EXTCLK);
s3c_gpio_cfgpin(S3C64XX_GPE(2), S3C64XX_GPE2_PCM1_FSYNC);
s3c_gpio_cfgpin(S3C64XX_GPE(3), S3C64XX_GPE3_PCM1_SIN);
s3c_gpio_cfgpin(S3C64XX_GPE(4), S3C64XX_GPE4_PCM1_SOUT);
break;
default:
printk(KERN_DEBUG "Invalid PCM Controller number!");
return -EINVAL;
}
return 0;
}
static int s3c64xx_i2s_probe(struct platform_device *pdev,
struct snd_soc_dai *dai)
{
/* configure GPIO for i2s port */
switch (dai->id) {
case 0:
s3c_gpio_cfgpin(S3C64XX_GPD(0), S3C64XX_GPD0_I2S0_CLK);
s3c_gpio_cfgpin(S3C64XX_GPD(1), S3C64XX_GPD1_I2S0_CDCLK);
s3c_gpio_cfgpin(S3C64XX_GPD(2), S3C64XX_GPD2_I2S0_LRCLK);
s3c_gpio_cfgpin(S3C64XX_GPD(3), S3C64XX_GPD3_I2S0_DI);
s3c_gpio_cfgpin(S3C64XX_GPD(4), S3C64XX_GPD4_I2S0_DO);
break;
case 1:
s3c_gpio_cfgpin(S3C64XX_GPE(0), S3C64XX_GPE0_I2S1_CLK);
s3c_gpio_cfgpin(S3C64XX_GPE(1), S3C64XX_GPE1_I2S1_CDCLK);
s3c_gpio_cfgpin(S3C64XX_GPE(2), S3C64XX_GPE2_I2S1_LRCLK);
s3c_gpio_cfgpin(S3C64XX_GPE(3), S3C64XX_GPE3_I2S1_DI);
s3c_gpio_cfgpin(S3C64XX_GPE(4), S3C64XX_GPE4_I2S1_DO);
break;
case 2:
s3c_gpio_cfgpin(S3C64XX_GPC(4), S3C64XX_GPC4_I2S_V40_DO0);
s3c_gpio_cfgpin(S3C64XX_GPC(5), S3C64XX_GPC5_I2S_V40_DO1);
s3c_gpio_cfgpin(S3C64XX_GPC(7), S3C64XX_GPC7_I2S_V40_DO2);
s3c_gpio_cfgpin(S3C64XX_GPH(6), S3C64XX_GPH6_I2S_V40_BCLK);
s3c_gpio_cfgpin(S3C64XX_GPH(7), S3C64XX_GPH7_I2S_V40_CDCLK);
s3c_gpio_cfgpin(S3C64XX_GPH(8), S3C64XX_GPH8_I2S_V40_LRCLK);
s3c_gpio_cfgpin(S3C64XX_GPH(9), S3C64XX_GPH9_I2S_V40_DI);
break;
}
return 0;
}
static int s3c64xx_ac97_cfg_gpd(struct platform_device *pdev)
{
s3c_gpio_cfgpin(S3C64XX_GPD(0), S3C64XX_GPD0_AC97_BITCLK);
s3c_gpio_cfgpin(S3C64XX_GPD(1), S3C64XX_GPD1_AC97_nRESET);
s3c_gpio_cfgpin(S3C64XX_GPD(2), S3C64XX_GPD2_AC97_SYNC);
s3c_gpio_cfgpin(S3C64XX_GPD(3), S3C64XX_GPD3_AC97_SDI);
s3c_gpio_cfgpin(S3C64XX_GPD(4), S3C64XX_GPD4_AC97_SDO);
return 0;
}
static int s3c64xx_i2s_probe(struct platform_device *pdev,
struct snd_soc_dai *dai)
{
struct device *dev = &pdev->dev;
struct s3c_i2sv2_info *i2s;
int ret;
dev_dbg(dev, "%s: probing dai %d\n", __func__, pdev->id);
if (pdev->id < 0 || pdev->id > ARRAY_SIZE(s3c64xx_i2s)) {
dev_err(dev, "id %d out of range\n", pdev->id);
return -EINVAL;
}
i2s = &s3c64xx_i2s[pdev->id];
ret = s3c_i2sv2_probe(pdev, dai, i2s,
pdev->id ? S3C64XX_PA_IIS1 : S3C64XX_PA_IIS0);
if (ret)
return ret;
i2s->dma_capture = &s3c64xx_i2s_pcm_stereo_in[pdev->id];
i2s->dma_playback = &s3c64xx_i2s_pcm_stereo_out[pdev->id];
i2s->iis_cclk = clk_get(dev, "audio-bus");
if (IS_ERR(i2s->iis_cclk)) {
dev_err(dev, "failed to get audio-bus");
iounmap(i2s->regs);
return -ENODEV;
}
/* configure GPIO for i2s port */
switch (pdev->id) {
case 0:
s3c_gpio_cfgpin(S3C64XX_GPD(0), S3C64XX_GPD0_I2S0_CLK);
s3c_gpio_cfgpin(S3C64XX_GPD(1), S3C64XX_GPD1_I2S0_CDCLK);
s3c_gpio_cfgpin(S3C64XX_GPD(2), S3C64XX_GPD2_I2S0_LRCLK);
s3c_gpio_cfgpin(S3C64XX_GPD(3), S3C64XX_GPD3_I2S0_DI);
s3c_gpio_cfgpin(S3C64XX_GPD(4), S3C64XX_GPD4_I2S0_D0);
break;
case 1:
s3c_gpio_cfgpin(S3C64XX_GPE(0), S3C64XX_GPE0_I2S1_CLK);
s3c_gpio_cfgpin(S3C64XX_GPE(1), S3C64XX_GPE1_I2S1_CDCLK);
s3c_gpio_cfgpin(S3C64XX_GPE(2), S3C64XX_GPE2_I2S1_LRCLK);
s3c_gpio_cfgpin(S3C64XX_GPE(3), S3C64XX_GPE3_I2S1_DI);
s3c_gpio_cfgpin(S3C64XX_GPE(4), S3C64XX_GPE4_I2S1_D0);
}
return 0;
}
static int s3c64xx_i2s_cfg_gpio(struct platform_device *pdev)
{
unsigned int base;
switch (pdev->id) {
case 0:
base = S3C64XX_GPD(0);
break;
case 1:
base = S3C64XX_GPE(0);
break;
case 2:
s3c_gpio_cfgpin(S3C64XX_GPC(4), S3C_GPIO_SFN(5));
s3c_gpio_cfgpin(S3C64XX_GPC(5), S3C_GPIO_SFN(5));
s3c_gpio_cfgpin(S3C64XX_GPC(7), S3C_GPIO_SFN(5));
s3c_gpio_cfgpin_range(S3C64XX_GPH(6), 4, S3C_GPIO_SFN(5));
return 0;
default:
printk(KERN_DEBUG "Invalid I2S Controller number: %d\n",
pdev->id);
return -EINVAL;
}
s3c_gpio_cfgpin_range(base, 5, S3C_GPIO_SFN(3));
return 0;
}
static int s3c64xx_i2s_probe(struct platform_device *pdev,
struct snd_soc_dai *dai)
{
/* configure GPIO for i2s port */
switch (dai->id) {
case 0:
s3c_gpio_cfgpin(S3C64XX_GPD(0), S3C64XX_GPD0_I2S0_CLK);
s3c_gpio_cfgpin(S3C64XX_GPD(1), S3C64XX_GPD1_I2S0_CDCLK);
s3c_gpio_cfgpin(S3C64XX_GPD(2), S3C64XX_GPD2_I2S0_LRCLK);
s3c_gpio_cfgpin(S3C64XX_GPD(3), S3C64XX_GPD3_I2S0_DI);
s3c_gpio_cfgpin(S3C64XX_GPD(4), S3C64XX_GPD4_I2S0_D0);
break;
case 1:
s3c_gpio_cfgpin(S3C64XX_GPE(0), S3C64XX_GPE0_I2S1_CLK);
s3c_gpio_cfgpin(S3C64XX_GPE(1), S3C64XX_GPE1_I2S1_CDCLK);
s3c_gpio_cfgpin(S3C64XX_GPE(2), S3C64XX_GPE2_I2S1_LRCLK);
s3c_gpio_cfgpin(S3C64XX_GPE(3), S3C64XX_GPE3_I2S1_DI);
s3c_gpio_cfgpin(S3C64XX_GPE(4), S3C64XX_GPE4_I2S1_D0);
}
return 0;
}
static int s3c64xx_i2sv3_cfg_gpio(struct platform_device *pdev)
{
switch (pdev->id) {
case 0:
s3c_gpio_cfgpin(S3C64XX_GPD(0), S3C64XX_GPD0_I2S0_CLK);
s3c_gpio_cfgpin(S3C64XX_GPD(1), S3C64XX_GPD1_I2S0_CDCLK);
s3c_gpio_cfgpin(S3C64XX_GPD(2), S3C64XX_GPD2_I2S0_LRCLK);
s3c_gpio_cfgpin(S3C64XX_GPD(3), S3C64XX_GPD3_I2S0_DI);
s3c_gpio_cfgpin(S3C64XX_GPD(4), S3C64XX_GPD4_I2S0_D0);
break;
case 1:
s3c_gpio_cfgpin(S3C64XX_GPE(0), S3C64XX_GPE0_I2S1_CLK);
s3c_gpio_cfgpin(S3C64XX_GPE(1), S3C64XX_GPE1_I2S1_CDCLK);
s3c_gpio_cfgpin(S3C64XX_GPE(2), S3C64XX_GPE2_I2S1_LRCLK);
s3c_gpio_cfgpin(S3C64XX_GPE(3), S3C64XX_GPE3_I2S1_DI);
s3c_gpio_cfgpin(S3C64XX_GPE(4), S3C64XX_GPE4_I2S1_D0);
default:
printk(KERN_DEBUG "Invalid I2S Controller number!");
return -EINVAL;
}
return 0;
}
static int s3c64xx_pcm_cfg_gpio(struct platform_device *pdev)
{
unsigned int base;
switch (pdev->id) {
case 0:
base = S3C64XX_GPD(0);
break;
case 1:
base = S3C64XX_GPE(0);
break;
default:
printk(KERN_DEBUG "Invalid PCM Controller number: %d\n",
pdev->id);
return -EINVAL;
}
s3c_gpio_cfgpin_range(base, 5, S3C_GPIO_SFN(2));
return 0;
}
.ngpio = S3C64XX_GPIO_B_NR,
.label = "GPB",
},
}, {
.base = S3C64XX_GPC_BASE,
.config = &gpio_4bit_cfg_eint0111,
.chip = {
.base = S3C64XX_GPC(0),
.ngpio = S3C64XX_GPIO_C_NR,
.label = "GPC",
},
}, {
.base = S3C64XX_GPD_BASE,
.config = &gpio_4bit_cfg_eint0111,
.chip = {
.base = S3C64XX_GPD(0),
.ngpio = S3C64XX_GPIO_D_NR,
.label = "GPD",
},
}, {
.base = S3C64XX_GPE_BASE,
.config = &gpio_4bit_cfg_noint,
.chip = {
.base = S3C64XX_GPE(0),
.ngpio = S3C64XX_GPIO_E_NR,
.label = "GPE",
},
}, {
.base = S3C64XX_GPG_BASE,
.config = &gpio_4bit_cfg_eint0111,
.chip = {
static int s3c64xx_ac97_cfg_gpd(struct platform_device *pdev)
{
return s3c_gpio_cfgpin_range(S3C64XX_GPD(0), 5, S3C_GPIO_SFN(4));
}
static int s3c_i2s_probe(struct platform_device *pdev,
struct snd_soc_dai *dai)
{
int ret = 0;
struct clk *cm, *cf;
debug_msg("%s\n", __FUNCTION__);
/* Configure the I2S pins in correct mode */
#ifndef CONFIG_SND_S3C64XX_I2S_BUS1
s3c_gpio_cfgpin(S3C64XX_GPD(0),S3C64XX_GPD0_I2S0_CLK);
s3c_gpio_cfgpin(S3C64XX_GPD(1),S3C64XX_GPD1_I2S0_CDCLK);
s3c_gpio_cfgpin(S3C64XX_GPD(2),S3C64XX_GPD2_I2S0_LRCLK);
s3c_gpio_cfgpin(S3C64XX_GPD(3),S3C64XX_GPD3_I2S0_DI);
s3c_gpio_cfgpin(S3C64XX_GPD(4),S3C64XX_GPD4_I2S0_DO);
/* pull-up-enable, pull-down-disable*/
s3c_gpio_setpull(S3C64XX_GPD(0), S3C_GPIO_PULL_UP);
s3c_gpio_setpull(S3C64XX_GPD(1), S3C_GPIO_PULL_UP);
s3c_gpio_setpull(S3C64XX_GPD(2), S3C_GPIO_PULL_UP);
s3c_gpio_setpull(S3C64XX_GPD(3), S3C_GPIO_PULL_UP);
s3c_gpio_setpull(S3C64XX_GPD(4), S3C_GPIO_PULL_UP);
#else
s3c_gpio_cfgpin(S3C64XX_GPE(0),S3C64XX_GPE0_I2S1_CLK);
s3c_gpio_cfgpin(S3C64XX_GPE(1),S3C64XX_GPE1_I2S1_CDCLK);
s3c_gpio_cfgpin(S3C64XX_GPE(2),S3C64XX_GPE2_I2S1_LRCLK);
s3c_gpio_cfgpin(S3C64XX_GPE(3),S3C64XX_GPE3_I2S1_DI);
s3c_gpio_cfgpin(S3C64XX_GPE(4),S3C64XX_GPE4_I2S1_DO);
/* pull-up-enable, pull-down-disable*/
s3c_gpio_setpull(S3C64XX_GPE(0), S3C_GPIO_PULL_UP);
s3c_gpio_setpull(S3C64XX_GPE(1), S3C_GPIO_PULL_UP);
s3c_gpio_setpull(S3C64XX_GPE(2), S3C_GPIO_PULL_UP);
s3c_gpio_setpull(S3C64XX_GPE(3), S3C_GPIO_PULL_UP);
s3c_gpio_setpull(S3C64XX_GPE(4), S3C_GPIO_PULL_UP);
#endif
s3c_i2s.regs = ioremap(S3C_IIS_PABASE, 0x100);
if (s3c_i2s.regs == NULL)
return -ENXIO;
ret = request_irq(S3C_IISIRQ, s3c_iis_irq, 0, "s3c-i2s", pdev);
if (ret < 0) {
printk("fail to claim i2s irq , ret = %d\n", ret);
iounmap(s3c_i2s.regs);
return -ENODEV;
}
printk("pd name=%s\n", pdev->name);
s3c_i2s.iis_clk = clk_get(&pdev->dev, PCLKCLK);
if (IS_ERR(s3c_i2s.iis_clk)) {
printk("failed to get clk(%s)\n", PCLKCLK);
goto lb5;
}
clk_enable(s3c_i2s.iis_clk);
s3c_i2s.clk_rate = clk_get_rate(s3c_i2s.iis_clk);
debug_msg("s3c_i2s.clk_rate1=%d\n",s3c_i2s.clk_rate);
#ifdef USE_CLKAUDIO
s3c_i2s.audio_bus = clk_get(NULL, EXTCLK);
if (IS_ERR(s3c_i2s.audio_bus)) {
printk("failed to get clk(%s)\n", EXTCLK);
goto lb4;
}
cm = clk_get(NULL, "mout_epll");
if (IS_ERR(cm)) {
printk("failed to get mout_epll\n");
goto lb3;
}
if(clk_set_parent(s3c_i2s.audio_bus, cm)){
printk("failed to set MOUTepll as parent of CLKAUDIO0\n");
goto lb2;
}
cf = clk_get(NULL, "fout_epll");
if (IS_ERR(cf)) {
printk("failed to get fout_epll\n");
goto lb2;
}
clk_enable(cf);
if(clk_set_parent(cm, cf)){
printk("failed to set FOUTepll as parent of MOUTepll\n");
goto lb1;
}
s3c_i2s.clk_rate = clk_get_rate(s3c_i2s.audio_bus);
clk_put(cf);
clk_put(cm);
#endif
debug_msg("s3c_i2s.clk_rate2=%d\n",s3c_i2s.clk_rate);
writel(S3C_IISCON_I2SACTIVE | S3C_IISCON_SWRESET, s3c_i2s.regs + S3C_IISCON);
s3c_snd_txctrl(0);
s3c_snd_rxctrl(0);
return 0;
#ifdef USE_CLKAUDIO
lb1:
clk_put(cf);
lb2:
clk_put(cm);
lb3:
clk_put(s3c_i2s.audio_bus);
#endif
lb4:
clk_disable(s3c_i2s.iis_clk);
clk_put(s3c_i2s.iis_clk);
lb5:
free_irq(S3C_IISIRQ, pdev);
iounmap(s3c_i2s.regs);
return -ENODEV;
}
static int s3c_i2s_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params)
{
struct snd_soc_pcm_runtime *rtd = substream->private_data;
unsigned long iiscon;
unsigned long iismod;
unsigned long iisfcon;
unsigned int *reg_GPDCON;
unsigned int *reg_GPBCON;
reg_GPDCON = ioremap(0x7f008060,0x100);
reg_GPBCON = ioremap(0x7f008020,0x100);
s3cdbg("Entered %s\n", __FUNCTION__);
/*Set I2C port to controll WM8753 codec*/
s3c_gpio_setpull(S3C64XX_GPB(5), S3C_GPIO_PULL_DOWN);
s3c_gpio_setpull(S3C64XX_GPB(6), S3C_GPIO_PULL_DOWN);
s3c_gpio_cfgpin(S3C64XX_GPB(5), S3C64XX_GPB5_I2C_SCL0);
s3c_gpio_cfgpin(S3C64XX_GPB(6), S3C64XX_GPB6_I2C_SDA0);
s3c24xx_i2s.master = 1;
/* Configure the I2S pins in correct mode */
s3c_gpio_cfgpin(S3C64XX_GPD(2),S3C64XX_GPD2_I2S0_LRCLK);
if (s3c24xx_i2s.master && !extclk){
s3cdbg("Setting Clock Output as we are Master\n");
s3c_gpio_cfgpin(S3C64XX_GPD(0),S3C64XX_GPD0_I2S0_CLK);
}
s3c_gpio_cfgpin(S3C64XX_GPD(1),S3C64XX_GPD1_I2S0_CDCLK);
s3c_gpio_cfgpin(S3C64XX_GPD(3),S3C64XX_GPD3_I2S0_DI);
s3c_gpio_cfgpin(S3C64XX_GPD(4),S3C64XX_GPD4_I2S0_DO);
/* pull-up-enable, pull-down-disable*/
s3c_gpio_setpull(S3C64XX_GPD(0), S3C_GPIO_PULL_UP);
s3c_gpio_setpull(S3C64XX_GPD(1), S3C_GPIO_PULL_UP);
s3c_gpio_setpull(S3C64XX_GPD(2), S3C_GPIO_PULL_UP);
s3c_gpio_setpull(S3C64XX_GPD(3), S3C_GPIO_PULL_UP);
s3c_gpio_setpull(S3C64XX_GPD(4), S3C_GPIO_PULL_UP);
s3cdbg("substream->stream : %d\n", substream->stream);
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
rtd->dai->cpu_dai->dma_data = &s3c24xx_i2s_pcm_stereo_out;
} else {
rtd->dai->cpu_dai->dma_data = &s3c24xx_i2s_pcm_stereo_in;
}
/* Working copies of registers */
iiscon = readl(s3c24xx_i2s.regs + S3C64XX_IIS0CON);
iismod = readl(s3c24xx_i2s.regs + S3C64XX_IIS0MOD);
iisfcon = readl(s3c24xx_i2s.regs + S3C64XX_IIS0FIC);
/* is port used by another stream */
if (!(iiscon & S3C64XX_IIS0CON_I2SACTIVE)) {
// Clear BFS field [2:1]
iismod &= ~(0x3<<1);
iismod |= S3C64XX_IIS0MOD_32FS | S3C64XX_IIS0MOD_INTERNAL_CLK;
if (!s3c24xx_i2s.master)
iismod |= S3C64XX_IIS0MOD_IMS_SLAVE;
else
iismod |= S3C64XX_IIS0MOD_IMS_EXTERNAL_MASTER;
}
/* enable TX & RX all to support Full-duplex */
iismod |= S3C64XX_IIS0MOD_TXRXMODE;
iiscon |= S3C64XX_IIS0CON_TXDMACTIVE;
iisfcon |= S3C64XX_IIS_TX_FLUSH;
iiscon |= S3C64XX_IIS0CON_RXDMACTIVE;
iisfcon |= S3C64XX_IIS_RX_FLUSH;
writel(iiscon, s3c24xx_i2s.regs + S3C64XX_IIS0CON);
writel(iismod, s3c24xx_i2s.regs + S3C64XX_IIS0MOD);
writel(iisfcon, s3c24xx_i2s.regs + S3C64XX_IIS0FIC);
// Tx, Rx fifo flush bit clear
iisfcon &= ~(S3C64XX_IIS_TX_FLUSH | S3C64XX_IIS_RX_FLUSH);
writel(iisfcon, s3c24xx_i2s.regs + S3C64XX_IIS0FIC);
s3cdbg("IISCON: %lx IISMOD: %lx", iiscon, iismod);
return 0;
}
