VciGcdMaster<vci_param>::VciGcdMaster( sc_module_name insname, const soclib::common::IntTab &index, const soclib::common::MappingTable &mt, const int seed, const typename vci_param::addr_t base) : sc_module(insname), r_fsm("r_fsm"), r_opa("r_opa"), r_opb("r_opb"), r_res("r_res"), r_cycle("r_cycle"), m_srcid(mt.indexForId(index)), m_base(base), p_resetn("p_resetn"), p_clk("p_clk"), p_vci("p_vci") { SC_METHOD(transition); dont_initialize(); sensitive << p_clk.pos(); SC_METHOD(genMoore); dont_initialize(); sensitive << p_clk.neg(); srand(seed); }
RTDriver::RTDriver(sc_module_name mname) : sc_module(mname), NI2P("NI2P"), P2NI("P2NI"), rtia("rtia"), rtic("rtic"), rtica("rtica"), rtoa("rtoa"), rtoc("rtoc"), rtoca("rtoca") { SC_METHOD(IPdetect); sensitive << rtia; SC_METHOD(OPdetect); sensitive << rtod[0] << rtod[1] << rtod[2] << rtod[3] << rtovc << rtoft; SC_METHOD(Creditdetect); for(unsigned int i = 0; i<SubChN; i++) { sensitive << CPa[i]; sensitive << out_cred[i]; } sensitive << rtic << rtoca; SC_THREAD(send); SC_THREAD(recv); rtinp_sig = false; rtoutp_sig = false; }
tmpl(/**/)::LoadWord (sc_module_name insname) : BaseModule(insname) { SC_METHOD (transition); dont_initialize(); sensitive << p_clk.pos(); SC_METHOD (genMoore); dont_initialize(); sensitive << p_clk.neg(); SC_METHOD (genMealy); dont_initialize(); sensitive << p_clk.neg() << p_input.rok << p_output.wok; build(); current = start; assert (shiftRegSize <= sizeof(unsigned long long)*8); #ifdef SOCLIB_MODULE_DEBUG // debug State * c = start; std::cout << "=== states === regSize: " << shiftRegSize << std::endl; while(1) { std::cout << (*c) << std::endl; if (c->num > 0 && c->next->num == 1) { break; } c = c->next; } std::cout << "=====================" << std::endl; #endif }
DbgPort::DbgPort(sc_module_name name_) : sc_module(name_) { SC_METHOD(comb); sensitive << i_nrst; sensitive << i_dport_valid; sensitive << i_dport_write; sensitive << i_dport_region; sensitive << i_dport_addr; sensitive << i_dport_wdata; sensitive << i_ireg_rdata; sensitive << i_csr_rdata; sensitive << i_pc; sensitive << i_npc; sensitive << i_e_valid; sensitive << i_m_valid; sensitive << r.ready; sensitive << r.rdata; sensitive << r.halt; sensitive << r.stepping_mode; sensitive << r.clock_cnt; sensitive << r.executed_cnt; sensitive << r.stepping_mode_cnt; SC_METHOD(registers); sensitive << i_clk.pos(); };
tmpl(/**/)::VciTimer( sc_module_name name, const IntTab &index, const MappingTable &mt, size_t nirq) : caba::BaseModule(name), m_vci_fsm(p_vci, mt.getSegmentList(index)), m_ntimer(nirq), r_value(soclib::common::alloc_elems<sc_signal<typename vci_param::data_t> >("value", m_ntimer)), r_period(soclib::common::alloc_elems<sc_signal<typename vci_param::data_t> >("period", m_ntimer)), r_counter(soclib::common::alloc_elems<sc_signal<typename vci_param::data_t> >("counter", m_ntimer)), r_mode(soclib::common::alloc_elems<sc_signal<int> >("mode", m_ntimer)), r_irq(soclib::common::alloc_elems<sc_signal<bool> >("saved_irq", m_ntimer)), p_clk("clk"), p_resetn("resetn"), p_vci("vci"), p_irq(soclib::common::alloc_elems<sc_out<bool> >("irq", m_ntimer)) { m_vci_fsm.on_read_write(on_read, on_write); SC_METHOD(transition); dont_initialize(); sensitive << p_clk.pos(); SC_METHOD(genMoore); dont_initialize(); sensitive << p_clk.neg(); }
fetch_packet_l3::fetch_packet_l3(sc_module_name name) : sc_module(name){ SC_METHOD(register_signals); sensitive_pos(clk); sensitive_neg(resetx); SC_METHOD(select_and_ack_packet); for(int destination = 0; destination < 2; destination++){ sensitive << posted_available[destination] << nposted_available[destination] << response_available[destination] << posted_requested[destination] << nposted_requested[destination] << response_requested[destination] << posted_packet_addr[destination] << nposted_packet_addr[destination] << response_packet_addr[destination]; } SC_METHOD(reconstruct_packet); sensitive << command_packet_rd_data_ro[0] << command_packet_rd_data_ro[1] #ifdef ENABLE_REORDERING << packet_passpw[0] << packet_passpw[1] << packet_seqid[0] << packet_seqid[1] << packet_chain[0] << packet_chain[1] #endif << packet_vc[0] << packet_vc[0] << packet_fetched[0] << packet_fetched[1]; }
cd_packet_crc_l3::cd_packet_crc_l3(sc_module_name name) : sc_module(name) { SC_METHOD(clocked_process); sensitive_neg << resetx; sensitive_pos << clk; SC_METHOD(calculate_outputs); sensitive << lk_dword_cd << crc1_value << crc2_value; }
tmpl(/**/)::VciBlockDevice( sc_module_name name, const MappingTable &mt, const IntTab &srcid, const IntTab &tgtid, const std::string &filename, const uint32_t block_size, const uint32_t latency) : caba::BaseModule(name), m_vci_target_fsm(p_vci_target, mt.getSegmentList(tgtid)), m_vci_init_fsm(p_vci_initiator, mt.indexForId(srcid)), m_block_size(block_size), m_latency(latency), p_clk("clk"), p_resetn("resetn"), p_vci_target("vci_target"), p_vci_initiator("vci_initiator"), p_irq("irq") { m_vci_target_fsm.on_read_write(on_read, on_write); m_fd = ::open(filename.c_str(), O_RDWR); if ( m_fd < 0 ) { std::cerr << "Unable to open block device image file " << filename << std::endl; m_device_size = 0; } else { m_device_size = lseek(m_fd, 0, SEEK_END) / m_block_size; if ( m_device_size > ((uint64_t)1<<(vci_param::B*8)) ) { std::cerr << "Warning: block device " << filename << " has more blocks than addressable with " << (8*vci_param::B) << "." << std::endl; m_device_size = ((uint64_t)1<<(vci_param::B*8)); } } #ifdef SOCLIB_MODULE_DEBUG std::cout << name << " = Opened " << filename << " which has " << m_device_size << " blocks of " << m_block_size << " bytes" << std::endl; #endif SC_METHOD(transition); dont_initialize(); sensitive << p_clk.pos(); SC_METHOD(genMoore); dont_initialize(); sensitive << p_clk.neg(); }
tmpl(/**/)::VciXicu( sc_core::sc_module_name name, const MappingTable &mt, const IntTab &index, size_t pti_count, size_t hwi_count, size_t wti_count, size_t irq_count ) : caba::BaseModule(name), m_seglist( mt.getSegmentList(index) ), m_pti_count( pti_count ), m_hwi_count( hwi_count ), m_wti_count( wti_count ), m_irq_count( irq_count ), r_fsm( "r_fsm" ), r_data( "r_data" ), r_srcid( "r_srcid" ), r_trdid( "r_trdid" ), r_pktid( "r_pktid" ), r_msk_pti( alloc_elems<sc_signal<uint32_t> >("r_msk_pti" , irq_count) ), r_msk_wti( alloc_elems<sc_signal<uint32_t> >("r_msk_wti" , irq_count) ), r_msk_hwi( alloc_elems<sc_signal<uint32_t> >("r_msk_hwi" , irq_count) ), r_pti_pending( "r_pti_pending" ), r_wti_pending( "r_wti_pending" ), r_hwi_pending( "r_hwi_pending" ), r_pti_per( alloc_elems<sc_signal<uint32_t> >("r_pti_per" , pti_count) ), r_pti_val( alloc_elems<sc_signal<uint32_t> >("r_pti_val" , pti_count) ), r_wti_reg( alloc_elems<sc_signal<uint32_t> >("r_wti_reg" , wti_count) ), p_clk( "clk" ), p_resetn( "resetn" ), p_vci( "vci" ), p_irq( alloc_elems<sc_core::sc_out<bool> >("irq", irq_count) ), p_hwi( alloc_elems<sc_core::sc_in<bool> >("hwi", hwi_count) ) { std::cout << " - Building VciXicu : " << name << std::endl; std::list<soclib::common::Segment>::iterator seg; for ( seg = m_seglist.begin() ; seg != m_seglist.end() ; seg++ ) { std::cout << " => segment " << seg->name() << " / base = " << std::hex << seg->baseAddress() << " / size = " << seg->size() << std::endl; } SC_METHOD(transition); dont_initialize(); sensitive << p_clk.pos(); SC_METHOD(genMoore); dont_initialize(); sensitive << p_clk.neg(); }
void ProcessingElement::connectToMemorySystem(MemorySystem *memsys) { m_memorySystem = memsys; createPortsAndFIFOs(); // must be done after FIFOs are created SC_METHOD(denseVectorAddrGen); sensitive << m_colIndValue->data_written_event() << m_denseVectorAddr->data_read_event(); dont_initialize(); SC_METHOD(rowPtrValueSplit); sensitive << m_rowPtrValueRaw->data_written_event() << m_rowPtrValue->data_read_event(); }
tmpl()::Downsampling( sc_core::sc_module_name insname, int ncycles) : soclib::caba::BaseModule(insname), m_work_latency(ncycles) { SC_METHOD(transition); dont_initialize(); sensitive << p_clk.pos(); SC_METHOD(genMoore); dont_initialize(); sensitive << p_clk.neg(); }
iu::iu(int _regFileSize, memory *_mem){ regFileSize = _regFileSize; mem = _mem; regFile = (uint32_t*)malloc(regFileSize*sizeof(uint32_t)); SC_METHOD(iu_comb); sensitive; SC_METHOD(iu_sync); sensitive; }
router(sc_module_name mn): sc_module(mn), buf1(8), buf2(8) { in1.bind(buf1); in2(buf2); SC_METHOD(read_port2); SC_THREAD(read_data_from_in1) }
Switch::Switch(sc_module_name name, int n, int m, int bufferSize) : sc_module(name), n(n), m(m), bufferSize(bufferSize) { //All packet in- and outputs in = new sc_in<packet> [n]; out = new sc_out<packet> [m]; // Is set to true if there is a pending packet on that address. pPending = new sc_in<bool> [n]; //pReceived = new sc_out<bool>[n]; cBusy = new sc_in<bool> [m]; buffer = new packet*[m]; bufferCount = new int[m]; for (int i = 0; i < m; ++i) { buffer[i] = new packet[bufferSize]; bufferCount[i] = 0; } SC_HAS_PROCESS( Switch); SC_METHOD( distribute); sensitive << clk.pos(); }
//extern unsigned int BitsLength; //============================================================================= // Constructor //(author:cylin)=============================================================== sc_h264d_top::sc_h264d_top( const sc_module_name name, const sc_time accept_delay, // accept delay (SC_TIME) const sc_time read_response_delay, // read response delay (SC_TIME) const sc_time write_response_delay // write response delay (SC_TIME) ) : sc_module (name) , accept_delay (accept_delay) , read_response_delay (read_response_delay) , write_response_delay (write_response_delay) { MEM = (unsigned char *) calloc(0xffffff, 1);//local memory in H264 //register socket methods target_socket.register_b_transport(this, &sc_h264d_top::b_transport); target_socket.register_nb_transport_fw(this, &sc_h264d_top::nb_transport_fw ); SC_THREAD(t_decoder_main); SC_THREAD(t_decoder_dump_frame); SC_THREAD(t_decoder_deblock_thread); SC_THREAD(transaction_req); SC_METHOD(call_nb_transport_bw); sensitive<<event_call_nb_bw; dont_initialize(); //--initialization tlm2 payload ,initiator_socket transaction_ptr = new tlm::tlm_generic_payload(this); data_buffer_ptr = new unsigned char [4]; //show_cur_tran = 30; flag_dump_frame = 0; }
SdMMC::SdMMC( sc_core::sc_module_name name, const std::string &filename, const uint32_t latency) : caba::BaseModule(name), m_latency(latency), p_clk("p_clk"), p_resetn("p_resetn"), p_spi_ss("p_spi_ss"), p_spi_clk("p_spi_clk"), p_spi_mosi("p_spi_mosi"), p_spi_miso("p_spi_miso") { std::cout << " - Building SdMMC " << name << std::endl; SC_METHOD(genMealy); dont_initialize(); sensitive << p_clk.neg(); sensitive << p_resetn; sensitive << p_spi_ss; sensitive << p_spi_clk; m_fd = ::open(filename.c_str(), O_RDWR); if ( m_fd < 0 ) { std::cout << "Error in component SdMMC : " << name << " Unable to open file " << filename << std::endl; exit(1); } m_device_size = lseek(m_fd, 0, SEEK_END); } // end constructor
diode_1p::diode_1p (sc_core::sc_module_name name, double Vf, double If, double nVT) : diode(If / (exp(Vf / nVT) - 1), nVT) { SC_METHOD(calculus); sensitive << activation; port <<= R; }
InstrDecoder::InstrDecoder(sc_module_name name_) : sc_module(name_) { SC_METHOD(comb); sensitive << i_nrst; sensitive << i_any_hold; sensitive << i_f_valid; sensitive << i_f_pc; sensitive << i_f_instr; sensitive << r.valid; sensitive << r.pc; sensitive << r.instr; sensitive << r.memop_load; sensitive << r.memop_store; SC_METHOD(registers); sensitive << i_clk.pos(); };
mosfet_1p::mosfet_1p (sc_core::sc_module_name name, double Vsat, double Isat) : mosfet(Vsat, Isat, 1) { SC_METHOD(calculus); sensitive << activation << control; port <<= R; }
WbSimpleSlave<wb_param>::WbSimpleSlave(sc_core::sc_module_name insname) : sc_core::sc_module(insname) { SC_METHOD(transition); sensitive << p_clk.pos(); SC_METHOD(genMealy); sensitive << p_clk.neg(); sensitive << p_wb; std::cout << "WishBone simple slave " << name() << " created successfully" << std::endl; }
VciVgsb<vci_param>::VciVgsb ( sc_module_name name, MappingTable &maptab, size_t nb_master, size_t nb_slave) : sc_core::sc_module(name), m_routing_table(maptab.getRoutingTable( IntTab() ) ), m_nb_initiator(nb_master), m_nb_target(nb_slave), p_clk("clk"), p_resetn("resetn"), p_to_initiator(soclib::common::alloc_elems<soclib::caba::VciTarget<vci_param> >("p_to_initiator", nb_master)), p_to_target(soclib::common::alloc_elems<soclib::caba::VciInitiator<vci_param> >("p_to_target", nb_slave)), r_fsm("r_fsm"), r_initiator_index("r_initiator_index"), r_target_index("r_target_index"), r_vci_counter(soclib::common::alloc_elems<sc_signal<uint32_t> >("r_vci_counter", nb_master, nb_slave)) { SC_METHOD(transition); dont_initialize(); sensitive << p_clk.pos(); SC_METHOD(genMealy_rspval); dont_initialize(); sensitive << p_clk.neg(); for ( size_t i=0 ; i<nb_slave ; i++ ) sensitive << p_to_target[i]; SC_METHOD(genMealy_rspack); dont_initialize(); sensitive << p_clk.neg(); for ( size_t i=0 ; i<nb_master ; i++ ) sensitive << p_to_initiator[i]; SC_METHOD(genMealy_cmdval); dont_initialize(); sensitive << p_clk.neg(); for ( size_t i=0 ; i<nb_master ; i++ ) sensitive << p_to_initiator[i]; SC_METHOD(genMealy_cmdack); dont_initialize(); sensitive << p_clk.neg(); for ( size_t i=0 ; i<nb_slave ; i++ ) sensitive << p_to_target[i]; if ( !m_routing_table.isAllBelow( nb_slave ) ) { std::cout << "error in vci_gsb component" << std::endl; std::cout << "one target index is larger than the number of targets" << std::endl; exit(0); } } // end constructor
Mod(const sc_module_name& name) : sc_module(name), a("a") { SC_METHOD(foo); sensitive << clk.pos(); dont_initialize(); sc_trace(sc_tf, a, a.name()); }
PulseOxyAnalogIn::PulseOxyAnalogIn(sc_module_name mname) : sc_module(mname) { i_pwmdac_dc = new pwmdac("DC_PWMDAC"); i_pwmdac_dc->pwm(dc_pwm); i_pwmdac_dc->analog(dc_analog); SC_METHOD(filt_update); sensitive << dc_analog << sensor_analog; }
NativeWrapper::NativeWrapper(sc_core::sc_module_name name) : sc_module(name), irq("irq") { interrupt = false; SC_THREAD(compute); SC_METHOD(interrupt_handler_internal); sensitive << irq.pos(); dont_initialize(); }
sc_event_queue::sc_event_queue( sc_module_name name_ ) : sc_module( name_ ), m_ppq( 128, sc_time_compare ), m_e( (std::string(SC_KERNEL_EVENT_PREFIX)+"_event").c_str() ), m_change_stamp(0), m_pending_delta(0) { SC_METHOD( fire_event ); sensitive << m_e; dont_initialize(); }
simple_die_controller::simple_die_controller(sc_module_name module_name) : sc_module(module_name) { m_cache_reg = NULL; m_data_reg = NULL; m_die_busy = false; m_bus_busy = false; m_op_mode = DIE_FREE_MODE; SC_METHOD(on_exec_completed); sensitive << m_exec_completed_event; dont_initialize(); }
VideoOut<wb_param>::VideoOut(sc_core::sc_module_name insname) : sc_core::sc_module(insname) { std::cout << "WishBone video out " << name() << " created sucsesfully" << std::endl; SC_METHOD(masterTransition); dont_initialize(); sensitive << p_clk.pos(); SC_METHOD(masterMoore); dont_initialize(); sensitive << p_clk.neg(); SC_METHOD(slaveTransition); dont_initialize(); sensitive << p_clk.pos(); SC_METHOD(slaveMoore); dont_initialize(); sensitive << p_clk.neg(); SC_METHOD(outputTransition); dont_initialize(); sensitive<<p_video_clk.pos(); SC_METHOD(outputMoore); dont_initialize(); sensitive<<p_clk.neg(); }
TraceSC::TraceSC (sc_core::sc_module_name name, Vorpsoc_top *_traceTarget, int argc, char *argv[]) : sc_module (name), traceTarget (_traceTarget) { #if VM_TRACE // Setup the name of the VCD dump file char* dumpName; char* dumpSuffix = "-vlt.vcd\0"; char* dumpNameDefault = "vlt-dump.vcd\0"; // We will be passed the current test-name when we're called if (argc > 1) { // Assume test name is first thing int testname_argv_index = 1; // Take the second argument as the test name and we'll // concatendate "-vlt.vcd" on the end dumpName = (char*) malloc((strlen(argv[testname_argv_index] + strlen(dumpSuffix))*sizeof(char))); // Copy in the test name strcpy(dumpName, argv[testname_argv_index]); // Now add on the suffix strcat(dumpName, dumpSuffix); printf("VCD dumpfile: %s\n", dumpName); } else dumpName = dumpNameDefault; Verilated::traceEverOn (true); cout << "Enabling VCD trace" << endl; // Establish a new trace with its correct time resolution, and trace to // great depth. spTraceFile = new SpTraceVcdCFile (); setSpTimeResolution (sc_get_time_resolution ()); traceTarget->trace (spTraceFile, 99); spTraceFile->open (dumpName); // Method to drive the dump on each clock edge SC_METHOD (driveTrace); sensitive << clk; #endif } // TraceSC ()
SCBus::SCBus(sc_module_name mname) : sc_module(mname), udp_socket(INVALID_SOCKET), local2wall_adjust_us(0), ext_synced(false) { LARGE_INTEGER perfCountFreq; if (!QueryPerformanceFrequency(&perfCountFreq)) { cerr << "SCBus: This platform does not support high resolution timers" << endl; exit(GetLastError()); } perfCountPerUS = double(perfCountFreq.QuadPart) / 1e6; cout << "SCBus: DBG Performance Counter per uS: " << perfCountPerUS << endl; SC_METHOD(transmit_data); dont_initialize(); sensitive << clk.pos() << rst; SC_METHOD(receive_data); dont_initialize(); sensitive << clk.pos() << rst; WIN32_FIND_DATA FindFileData; HANDLE hFind; hFind = FindFirstFile("*.sca", &FindFileData); if (hFind == INVALID_HANDLE_VALUE) { cout << "SCBus: No valid input batch file found (" << GetLastError() << ")" << endl; cout << "SCBus: Starting to listen on UDP" << endl; SC_THREAD(comm_thread); } else { cout << "SCBus: Using batch file '" << FindFileData.cFileName << "'" << endl; setup_batch(FindFileData.cFileName); FindClose(hFind); SC_THREAD(batch_thread); } }
ARMV5::ARMV5(sc_module_name name, uint32_t addr, bool using_gdb, unsigned int gdb_port): sc_module(name) { this->core_id = 0; cp15.c0_idcode = 0x41069265; cp15.c0_cachetype = 0x1dd20d2; cp15.c0_cachetype = 0x1d112152; gdb = 0; this->using_gdb = using_gdb; this->gdb_port = gdb_port; gdb_init = false; using_prog = false; bkptRemove(); // clear all break points watchRemove(); // clear all watch points rfInit(addr); cpInit(); cacheInit(); delay = 0; mmu_enable = false; icache_enable = false; dcache_enable = false; vectorHi = false; /* start to simulate */ SC_THREAD(run); sensitive << clk.pos(); //dont_initialize(); SC_METHOD(shared_event_listener); sensitive << ARMV5::shared_event; SC_METHOD(irq_n_listener); sensitive << irq_n.neg(); }