static bool nvsd_phase_in_adjustments(struct tegra_dc *dc, struct tegra_dc_sd_settings *settings) { u8 step, cur_sd_brightness; u16 target_k, cur_k; u32 man_k, val; cur_sd_brightness = atomic_read(_sd_brightness); target_k = tegra_dc_readl(dc, DC_DISP_SD_HW_K_VALUES); target_k = SD_HW_K_R(target_k); cur_k = tegra_dc_readl(dc, DC_DISP_SD_MAN_K_VALUES); cur_k = SD_HW_K_R(cur_k); /* read brightness value */ val = tegra_dc_readl(dc, DC_DISP_SD_BL_CONTROL); val = SD_BLC_BRIGHTNESS(val); step = settings->phase_adj_step; if (cur_sd_brightness != val || target_k != cur_k) { if (!step) step = ADJ_PHASE_STEP; /* Phase in Backlight and Pixel K every ADJ_PHASE_STEP frames*/ if ((step-- & ADJ_PHASE_STEP) == ADJ_PHASE_STEP) { if (val != cur_sd_brightness) { val > cur_sd_brightness ? (cur_sd_brightness++) : (cur_sd_brightness--); } if (target_k != cur_k) { if (target_k > cur_k) cur_k += K_STEP; else cur_k -= K_STEP; } /* Set manual k value */ man_k = SD_MAN_K_R(cur_k) | SD_MAN_K_G(cur_k) | SD_MAN_K_B(cur_k); tegra_dc_io_start(dc); tegra_dc_writel(dc, man_k, DC_DISP_SD_MAN_K_VALUES); tegra_dc_io_end(dc); /* Set manual brightness value */ atomic_set(_sd_brightness, cur_sd_brightness); } settings->phase_adj_step = step; return true; } else return false; }
static bool nvsd_phase_in_adjustments(struct tegra_dc *dc, struct tegra_dc_sd_settings *settings) { u8 step, cur_sd_brightness; int commanded; u16 target_k, cur_k; u32 man_k, val; struct platform_device *pdev; struct backlight_device *bl; bool below_min_brightness = false; cur_sd_brightness = atomic_read(sd_brightness); target_k = tegra_dc_readl(dc, DC_DISP_SD_HW_K_VALUES); target_k = SD_HW_K_R(target_k); cur_k = tegra_dc_readl(dc, DC_DISP_SD_MAN_K_VALUES); cur_k = SD_HW_K_R(cur_k); /* read brightness value */ val = tegra_dc_readl(dc, DC_DISP_SD_BL_CONTROL); val = SD_BLC_BRIGHTNESS(val); if (settings->panel_min_brightness) { pdev = settings->bl_device; bl = platform_get_drvdata(pdev); commanded = (cur_sd_brightness * bl->props.brightness) / 255; /* Need to reduce how aggressive we are */ if (commanded < settings->panel_min_brightness) { if (cur_k || cur_sd_brightness != 255) below_min_brightness = true; else return false; } /* Return so we don't modify in the opposite direction */ if (commanded == settings->panel_min_brightness && target_k > cur_k) return false; } /* Correct until brightness is high enough */ if (below_min_brightness) { if (cur_sd_brightness != 255) cur_sd_brightness++; if (cur_k) cur_k -= K_STEP; man_k = SD_MAN_K_R(cur_k) | SD_MAN_K_G(cur_k) | SD_MAN_K_B(cur_k); tegra_dc_writel(dc, man_k, DC_DISP_SD_MAN_K_VALUES); atomic_set(sd_brightness, cur_sd_brightness); return true; } step = settings->phase_adj_step; if (cur_sd_brightness != val || target_k != cur_k) { if (!step) step = ADJ_PHASE_STEP; /* Phase in Backlight and Pixel K every ADJ_PHASE_STEP frames*/ if ((step-- & ADJ_PHASE_STEP) == ADJ_PHASE_STEP) { if (val != cur_sd_brightness) { val > cur_sd_brightness ? (cur_sd_brightness++) : (cur_sd_brightness--); } if (target_k != cur_k) { if (target_k > cur_k) cur_k += K_STEP; else cur_k -= K_STEP; } /* Set manual k value */ man_k = SD_MAN_K_R(cur_k) | SD_MAN_K_G(cur_k) | SD_MAN_K_B(cur_k); tegra_dc_writel(dc, man_k, DC_DISP_SD_MAN_K_VALUES); /* Set manual brightness value */ atomic_set(sd_brightness, cur_sd_brightness); } settings->phase_adj_step = step; return true; } else return false; }
static int nvsd_set_brightness(struct tegra_dc *dc) { u32 bin_width; int i, j; int val; int pix; int bin_idx; int incr; int base; u32 histo[32]; u32 histo_total = 0; /* count of pixels */ fixed20_12 nonhisto_gain; /* gain of pixels not in histogram */ fixed20_12 est_achieved_gain; /* final gain of pixels */ fixed20_12 histo_gain = dfixed_init(0); /* gain of pixels */ fixed20_12 k, threshold; /* k is the fractional part of HW_K */ fixed20_12 den, num, out; fixed20_12 pix_avg, pix_avg_softclip; /* Collet the inputs of the algorithm */ for (i = 0; i < DC_DISP_SD_HISTOGRAM_NUM; i++) { val = tegra_dc_readl(dc, DC_DISP_SD_HISTOGRAM(i)); for (j = 0; j < 4; j++) histo[i * 4 + j] = SD_HISTOGRAM_BIN(val, (j * 8)); } val = tegra_dc_readl(dc, DC_DISP_SD_HW_K_VALUES); k.full = dfixed_const(SD_HW_K_R(val)); den.full = dfixed_const(1024); k.full = dfixed_div(k, den); val = tegra_dc_readl(dc, DC_DISP_SD_SOFT_CLIPPING); threshold.full = dfixed_const(SD_SOFT_CLIPPING_THRESHOLD(val)); val = tegra_dc_readl(dc, DC_DISP_SD_CONTROL); bin_width = SD_BIN_WIDTH_VAL(val); incr = 1 << bin_width; base = 256 - 32 * incr; for (pix = base, bin_idx = 0; pix < 256; pix += incr, bin_idx++) { num.full = dfixed_const(pix + pix + incr); den.full = dfixed_const(2); pix_avg.full = dfixed_div(num, den); pix_avg_softclip.full = nvsd_softclip(pix_avg, k, threshold); num.full = dfixed_const(histo[bin_idx]); den.full = dfixed_const(256); out.full = dfixed_div(num, den); num.full = dfixed_mul(out, pix_avg_softclip); out.full = dfixed_div(num, pix_avg); histo_gain.full += out.full; histo_total += histo[bin_idx]; } out.full = dfixed_const(256 - histo_total); den.full = dfixed_const(1) + k.full; num.full = dfixed_mul(out, den); den.full = dfixed_const(256); nonhisto_gain.full = dfixed_div(num, den); den.full = nonhisto_gain.full + histo_gain.full; num.full = dfixed_const(1); out.full = dfixed_div(num, den); num.full = dfixed_const(255); est_achieved_gain.full = dfixed_mul(num, out); val = dfixed_trunc(est_achieved_gain); return nvsd_backlght_interplate(val, 128); }