void hisi_mclk_config(struct hisi_sensor_ctrl_t *s_ctrl,
struct sensor_power_setting *power_setting, int state)
{
int sensor_index;
cam_debug("%s enter.state:%d", __func__, state);
if (SENSOR_INDEX_INVALID != power_setting->sensor_index) {
sensor_index = power_setting->sensor_index;
} else {
sensor_index = s_ctrl->sensor->sensor_info->sensor_index;
}
if (is_fpga_board())
return;
if (POWER_ON == state) {
/* mclk */
if (CAMERA_SENSOR_PRIMARY == sensor_index) {
SETREG8(REG_ISP_CLK_DIVIDER, 0x44);
} else {
SETREG8(REG_ISP_CLK_DIVIDER, 0x44);
}
} else {
//SETREG8(REG_ISP_CLK_DIVIDER, 0);
}
if (0 != power_setting->delay) {
camdrv_msleep(power_setting->delay);
}
return;
}
int serial_init (void)
{
serial_setgpio();
OUTREG8( (DEBUG_UART_BASE + UART_UIER_OFFSET), 0 );
CLRREG8( (DEBUG_UART_BASE + UART_UFCR_OFFSET), UFCR_UME );
CLRREG8( (DEBUG_UART_BASE + UART_UISR_OFFSET), (UISR_RCVEIR|UISR_XMITIR) );
SETREG8( (DEBUG_UART_BASE + UART_ULCR_OFFSET), (ULCR_WLS_8BITS|ULCR_SBLS_1BIT) );
serial_setbrg();
SETREG8( (DEBUG_UART_BASE + UART_UFCR_OFFSET), (UFCR_FME | UFCR_RFRT | UFCR_TFRT | UFCR_UME | UFCR_RDTR_15) );
return 0;
}
//------------------------------------------------------------------------------
//
// Function: BSPIntrActiveIrq
//
// This function is called from interrupt handler to give BSP chance to
// translate IRQ in case of secondary interrupt controller.
//
UINT32 BSPIntrActiveIrq(UINT32 irq)
{
UINT8 data;
UINT32 doneIrq;
OALMSG(OAL_INTR&&OAL_VERBOSE, (L"+BSPIntrActiveIrq(%d)\r\n", irq));
switch(irq)
{
case IRQ_GPIO:
// Check whether alarm happen
if(OALRTCAlarmIntrHandler() == FALSE) {
irq = OAL_INTR_IRQ_UNDEFINED;
}
// Acknowledge GPIO interrupt
OUTREG32(&g_pVRC5477Regs->GIUINSTAT, 0xffffffff);
// Re-enable IRQ_GPIO interrupt on VRC5477
doneIrq = IRQ_GPIO;
OALIntrDoneIrqs(1, &doneIrq);
break;
case IRQ_INTC:
// Read PIC1 interrupt
OUTREG8(&g_pPIC1Regs->ctrl, 0x0E);
data = INREG8(&g_pPIC1Regs->data) & 0x07;
if (data != 2) {
irq = IRQ_PIC_0 + data;
SETREG8(&g_pPIC1Regs->mask, 1 << data);
} else {
// Read PIC2 interrupt
OUTREG8(&g_pPIC2Regs->ctrl, 0x0E);
data = INREG8(&g_pPIC2Regs->data) & 0x07;
irq = IRQ_PIC_8 + data;
SETREG8(&g_pPIC2Regs->mask, 1 << data);
// End interrupt on PIC2
OUTREG8(&g_pPIC2Regs->ctrl, 0x20);
}
// End interrupt on PIC1
OUTREG8(&g_pPIC1Regs->ctrl, 0x20);
// Re-enable IRQ_INTC interrupt on VRC5477
doneIrq = IRQ_INTC;
OALIntrDoneIrqs(1, &doneIrq);
break;
}
OALMSG(OAL_INTR&&OAL_VERBOSE, (L"-BSPIntrActiveIrq(%d)\r\n", irq));
return irq;
}
static UINT32 opTASI(v60_state *cpustate)
{
UINT8 appb;
cpustate->modadd = cpustate->PC + 1;
cpustate->moddim = 0;
// Load the address of the operand
cpustate->amlength1 = ReadAMAddress(cpustate);
// Load UINT8 from the address
if (cpustate->amflag)
appb = (UINT8)cpustate->reg[cpustate->amout & 0x1F];
else
appb = cpustate->program->read_byte(cpustate->amout);
// Set the flags for SUB appb, FF
SUBB(appb, 0xff);
// Write FF in the operand
if (cpustate->amflag)
SETREG8(cpustate->reg[cpustate->amout & 0x1F], 0xFF);
else
cpustate->program->write_byte(cpustate->amout, 0xFF);
return cpustate->amlength1 + 1;
}
UINT32 opTASI(void)
{
UINT8 appb;
modAdd=PC + 1;
modDim=0;
/* Load the address of the operand */
amLength1=ReadAMAddress();
/* Load UINT8 from the address */
if (amFlag)
appb=(UINT8)v60.reg[amOut&0x1F];
else
appb=MemRead8(amOut);
/* Set the flags for SUB appb,FF */
SUBB(appb, 0xff);
/* Write FF in the operand */
if (amFlag)
SETREG8(v60.reg[amOut&0x1F], 0xFF);
else
MemWrite8(amOut,0xFF);
return amLength1 + 1;
}
void serial_setbrg (void)
{
unsigned short UART_DIVISOR_LATCH = DEVICE_CLOCK / 16 / DEBUG_UART_BAUDRATE;
SETREG8( (DEBUG_UART_BASE + UART_ULCR_OFFSET), ULCR_DLAB );
OUTREG8( (DEBUG_UART_BASE + UART_UDLLR_OFFSET), UART_DIVISOR_LATCH & 0xFF );
OUTREG8( (DEBUG_UART_BASE + UART_UDLHR_OFFSET), (UART_DIVISOR_LATCH >> 8) & 0xFF );
CLRREG8( (DEBUG_UART_BASE + UART_ULCR_OFFSET), ULCR_DLAB );
}
void hw_reset(void)
{
printf("hw_reset\n");
OUTREG16(A_WDT_TCSR, WDT_CLK_EXTAL);
SETREG16(A_WDT_TCSR, WDT_CLK_PRESCALE_CLK1024);
OUTREG16(A_WDT_TDR, 3);
OUTREG16(A_WDT_TCNT, 0);
SETREG8(A_WDT_TCER, WDT_ENABLE);
while (1);
}
//------------------------------------------------------------------------------
//
// Function: BSPIntrDisableIrq
//
// This function is called from OALIntrDisableIrq to disable interrupt on
// secondary interrupt controller.
//
UINT32 BSPIntrDisableIrq(UINT32 irq)
{
OALMSG(OAL_INTR&&OAL_VERBOSE, (L"+BSPIntrDisableIrq(%d)\r\n", irq));
// Secondary IRQ are using IRQ_GPIO16 and above
if (irq < IRQ_PIC_0) goto cleanUp;
// Disable interrupt on appropriate PIC
if (irq < IRQ_PIC_8) {
SETREG8(&g_pPIC1Regs->mask, 1 << (irq - IRQ_PIC_0));
} else {
SETREG8(&g_pPIC2Regs->mask, 1 << (irq - IRQ_PIC_8));
}
// We are done....
irq = OAL_INTR_IRQ_UNDEFINED;
cleanUp:
OALMSG(OAL_INTR&&OAL_VERBOSE, (L"-BSPIntrDisableIrq(irq = %d\r\n", irq));
return irq;
}
static UINT32 am3Register(void)
{
switch (modDim)
{
case 0:
SETREG8(v60.reg[modVal&0x1F], modWriteValB);
break;
case 1:
SETREG16(v60.reg[modVal&0x1F], modWriteValH);
break;
case 2:
v60.reg[modVal&0x1F] = modWriteValW;
break;
}
return 1;
}
static UINT32 am3Register(v60_state *cpustate)
{
switch (cpustate->moddim)
{
case 0:
SETREG8(cpustate->reg[cpustate->modval & 0x1F], cpustate->modwritevalb);
break;
case 1:
SETREG16(cpustate->reg[cpustate->modval & 0x1F], cpustate->modwritevalh);
break;
case 2:
cpustate->reg[cpustate->modval & 0x1F] = cpustate->modwritevalw;
break;
}
return 1;
}
static UINT32 opDECB(v60_state *cpustate) /* TRUSTED */
{
UINT8 appb;
cpustate->modadd = cpustate->PC + 1;
cpustate->moddim = 0;
cpustate->amlength1 = ReadAMAddress(cpustate);
if (cpustate->amflag)
appb = (UINT8)cpustate->reg[cpustate->amout];
else
appb = cpustate->program->read_byte(cpustate->amout);
SUBB(appb, 1);
if (cpustate->amflag)
SETREG8(cpustate->reg[cpustate->amout], appb);
else
cpustate->program->write_byte(cpustate->amout, appb);
return cpustate->amlength1 + 1;
}
UINT32 opDECB(void) /* TRUSTED */
{
UINT8 appb;
modAdd=PC+1;
modDim=0;
amLength1=ReadAMAddress();
if (amFlag)
appb=(UINT8)v60.reg[amOut];
else
appb=MemRead8(amOut);
SUBB(appb, 1);
if (amFlag)
SETREG8(v60.reg[amOut], appb);
else
MemWrite8(amOut, appb);
return amLength1+1;
}
void mini_ispv1_hw_3a_switch(u8 on)
{
u8 win_top_h,win_top_l;
u8 win_left_h,win_left_l;
u8 win_height;
u8 win_width;
u32 data_count = 0;
#if 0
u8 hdr_movie_on = 0;
#endif
print_info(" %s on = %d",__func__,on);
if(on == HW_3A_ON)
{
#if 0
if (mini_this_ispdata->sensor->sensor_hdr_movie.set_hdr_movie_switch)
{
hdr_movie_on = mini_this_ispdata->sensor->sensor_hdr_movie.get_hdr_movie_switch();
if(hdr_movie_on)
GETREG16(REG_ROI_MEM_WIDTH_3A,data_count);
}
#endif
data_count = data_count + mini_hw_3a_data.data_count;
SETREG16(REG_ROI_MEM_WIDTH_3A,data_count);
win_top_l = mini_hw_3a_data.ae_param.ae_win_top;
win_top_h = mini_hw_3a_data.ae_param.ae_win_top >> 8;
win_left_l = mini_hw_3a_data.ae_param.ae_win_left;
win_left_h = mini_hw_3a_data.ae_param.ae_win_left >> 8;
win_height = mini_hw_3a_data.ae_param.ae_win_height;
win_width = mini_hw_3a_data.ae_param.ae_win_width;
SETREG8(HW_3A_HIST_SHIFT_REG,mini_hw_3a_data.ae_param.ae_hist_shift);//r_hist_shift
SETREG8(HW_3A_MEAN_SHIFT_REG,mini_hw_3a_data.ae_param.ae_mean_shift);//r_mean_shift
//aec agc awb:hist&mean
SETREG8(HW_3A_WIN_TOP_REG_H,win_top_h);//r_window_top[11:8]
SETREG8(HW_3A_WIN_TOP_REG_L,win_top_l);//r_window_top[7:0]
SETREG8(HW_3A_WIN_LEFT_REG_H,win_left_h);//r_window_left[12:8]
SETREG8(HW_3A_WIN_LEFT_REG_L,win_left_l);//r_window_left[7:0]
SETREG8(HW_3A_WIN_HEIGHT_REG,win_height);//r_window_height
SETREG8(HW_3A_WIN_WIDTH_REG,win_width);//r_window_width
SETREG8(HW_3A_BLC_ENABLE_REG, mini_hw_3a_data.blc_enable); //BLC enable
SETREG8(HW_3A_AECAGC_MODEL, mini_hw_3a_data.ae_param.ae_win_model);//aec agc &awb mode 0:16x16;1:8x8
SETREG8(HW_3A_AF_ENABLE_REG, mini_hw_3a_data.af_param.af_enable); //AF stat enable
SETREG8(HW_3A_AECAGC_ENABLE, mini_hw_3a_data.ae_param.ae_enable); //AEC&AGC&AWB stat enable
SETREG8(HW_3A_ROI_ENABLE_REG,0x4);
//SETREG8(HW_3A_FRAME_CTRL_REG,0x05);//ROI smode enable, dual source enable
/* HW_3A_FRAME_CTRL_REG:bit[0 ] ROI smode enable, dual source enable*/
SETREG8(HW_3A_FRAME_CTRL_REG,GETREG8(HW_3A_FRAME_CTRL_REG) | SHIFT_BIT_0);
/*HW_3A_ENABLE bit[7][6]:gamma&tonemapping combined , bit[1]:3A enalbe */
SETREG8(HW_3A_ENABLE, GETREG8(HW_3A_ENABLE) |SHIFT_BIT_1);
//SETREG8(HW_3A_RAM_ACCESS_ENABLE, 0x8);
}
else
{
