extern int stx7108_usb_init(int port, int over_current, int power_ctrl)
{
#ifdef QQQ /* QQQ - DELETE */
unsigned long reg;
const unsigned char oc_pins[2] = {4, 6}; /* PIO4 */
const unsigned char power_pins[2] = {5, 7}; /* PIO4 */
if (port >= sizeof(oc_pins)) /* invalid port number ? */
return -1; /* failed to initialize! */
/* Power on the USB */
reg = readl(STX7105_SYSCONF_SYS_CFG32);
/* Power up USB host controller */
/* USBn_HC_POWER_DOWN_REQ = 0 = Powered Up */
reg &= ~(1ul<<(4+port));
/* Power up USB PHY */
/* USBn_PHY_POWER_DOWN_REQ = 0 = Powered Up */
reg &= ~(1ul<<(6+port));
writel(reg, STX7105_SYSCONF_SYS_CFG32);
if (over_current) {
/* USB overcurrent enable */
reg = readl(STX7105_SYSCONF_SYS_CFG04);
/* USB0_PRT_OVCURR_POL = 0 = Active Low */
reg &= ~(1ul<<(3+port));
/* USBn_PRT_OVCURR_IN = 0 = PIO4[oc_pins[port]] */
reg &= ~(1ul<<(5+port));
/* CFG_USBn_OVRCURR_ENABLE = 1 = OC Enabled */
reg |= 1ul<<(11+port);
writel(reg, STX7105_SYSCONF_SYS_CFG04);
/* Route USBn OC Routing via PIO4[oc_pins[port]] */
reg = readl(STX7105_SYSCONF_SYS_CFG34);
/* PIO4[oc_pins[port]] CFG34[8+oc_pins[port],oc_pins[port]] = Alternate4 */
reg &= ~(0x0101ul<<(oc_pins[port])); /* Mask=3 */
reg |= 0x0101ul<<(oc_pins[port]); /* OR=3 */
writel(reg, STX7105_SYSCONF_SYS_CFG34);
/* set PIO directionality, for OC as IN */
SET_PIO_PIN(ST40_PIO_BASE(4), oc_pins[port], STPIO_IN);
}
if (power_ctrl) {
/* Route USBn POWER Routing via PIO4[power_pins[port]] */
reg = readl(STX7105_SYSCONF_SYS_CFG34);
/* PIO4[power_pins[port]] CFG34[8+power_pins[port],power_pins[port]] = Alternate4 */
reg &= ~(0x0101ul<<(power_pins[port])); /* Mask=3 */
reg |= 0x0101ul<<(power_pins[port]); /* OR=3 */
writel(reg, STX7105_SYSCONF_SYS_CFG34);
/* set PIO directionality, for POWER as ALT_OUT */
SET_PIO_PIN(ST40_PIO_BASE(4), power_pins[port], STPIO_ALT_OUT);
}
/* start the USB Wrapper Host Controller */
ST40_start_host_control(
USB_FLAGS_STRAP_8BIT |
USB_FLAGS_STBUS_CONFIG_THRESHOLD128);
return 0;
#endif /* QQQ - DELETE */
}
extern void stx7108_configure_i2c(void)
{
/*
* The I2C busses are routed as follows:
*
* Bus SCL SDA
* --- --- ---
* 0 PIO1[6] PIO1[7] SSC #0
* 1 PIO9[6] PIO9[7] SSC #1
* 2 PIO1[3] PIO1[4] SSC #2, Variant A
* 2 PIO14[4] PIO14[5] SSC #2, Variant B
* 3 PIO5[2] PIO5[3] SSC #3
* 4 PIO13[6] PIO13[7] SSC #4
* 5 PIO5[6] PIO5[7] SSC #5
* 6 PIO15[2] PIO15[3] SSC #6
*/
const int scl_port = ssc_pios[CONFIG_I2C_BUS].pio[0].port;
const int scl_pin = ssc_pios[CONFIG_I2C_BUS].pio[0].pin;
const int sda_port = ssc_pios[CONFIG_I2C_BUS].pio[1].port;
const int sda_pin = ssc_pios[CONFIG_I2C_BUS].pio[1].pin;
if (CONFIG_I2C_BUS >= ARRAY_SIZE(ssc_pios)) BUG();
SET_PIO_PIN(ST40_PIO_BASE(scl_port), scl_pin, STPIO_BIDIR); /* I2C_SCL */
SET_PIO_PIN(ST40_PIO_BASE(sda_port), sda_pin, STPIO_BIDIR); /* I2C_SDA */
}
extern void stx7108_configure_spi(void)
{
/*
* We set up the PIO pins correctly for SPI
*/
#if defined(CONFIG_SOFT_SPI) /* Use "bit-banging" for SPI */
/* route PIO (alternate #0) */
stx7108_pioalt_select(2, 1, 0); /* SPI_MISO */
stx7108_pioalt_select(2, 0, 0); /* SPI_MOSI */
stx7108_pioalt_select(1, 7, 0); /* SPI_notCS */
stx7108_pioalt_select(1, 6, 0); /* SPI_CLK */
/* set PIO directionality */
SET_PIO_PIN(ST40_PIO_BASE(2), 1, STPIO_IN); /* SPI_MISO */
SET_PIO_PIN(ST40_PIO_BASE(2), 0, STPIO_OUT); /* SPI_MOSI */
SET_PIO_PIN(ST40_PIO_BASE(1), 7, STPIO_OUT); /* SPI_notCS */
SET_PIO_PIN(ST40_PIO_BASE(1), 6, STPIO_OUT); /* SPI_CLK */
/* drive outputs with sensible initial values */
STPIO_SET_PIN(ST40_PIO_BASE(2), 0, 0); /* deassert SPI_MOSI */
STPIO_SET_PIN(ST40_PIO_BASE(1), 7, 1); /* deassert SPI_notCS */
STPIO_SET_PIN(ST40_PIO_BASE(1), 6, 1); /* assert SPI_CLK */
#else
#error Currently only S/W bit-banging for SPI is supported.
#endif /* CONFIG_SOFT_SPI */
}
extern void stx7141_usb_init(void)
{
#ifdef QQQ /* QQQ - TO DO */
unsigned long reg, req_reg;
/* Power on the USB */
reg = readl(STX7141_SYSCONF_SYS_CFG32);
reg &= ~(1ul<<4); /* USB_POWER_DOWN_REQ = 0 */
writel(reg, STX7141_SYSCONF_SYS_CFG32);
/* Work around for USB over-current detection chip being
* active low, and the 7141 being active high.
* Note this is an undocumented bit, which apparently enables
* an inverter on the overcurrent signal.
*/
reg = readl(STX7141_SYSCONF_SYS_CFG06);
reg |= 1ul<<29;
writel(reg, STX7141_SYSCONF_SYS_CFG06);
/* USB oc */
SET_PIO_PIN(PIO_PORT(5), 6, STPIO_IN);
/* USB power */
SET_PIO_PIN(PIO_PORT(5), 7, STPIO_ALT_OUT);
STPIO_SET_PIN(PIO_PORT(5), 7, 1);
/* Set strap mode */
#define STRAP_MODE AHB2STBUS_STRAP_16_BIT
reg = readl(AHB2STBUS_STRAP);
#if STRAP_MODE == 0
reg &= ~AHB2STBUS_STRAP_16_BIT;
#else
reg |= STRAP_MODE;
#endif
writel(reg, AHB2STBUS_STRAP);
/* Start PLL */
reg = readl(AHB2STBUS_STRAP);
writel(reg | AHB2STBUS_STRAP_PLL, AHB2STBUS_STRAP);
udelay(100000); /* QQQ: can this delay be shorter ? */
writel(reg & (~AHB2STBUS_STRAP_PLL), AHB2STBUS_STRAP);
udelay(100000); /* QQQ: can this delay be shorter ? */
req_reg =
(1<<21) | /* Turn on read-ahead */
(5<<16) | /* Opcode is store/load 32 */
(0<<15) | /* Turn off write posting */
(1<<14) | /* Enable threshold */
(3<<9) | /* 2**3 Packets in a chunk */
(0<<4) | /* No messages */
(8<<0); /* Threshold is 256 */
do {
writel(req_reg, AHB2STBUS_STBUS_CONFIG);
reg = readl(AHB2STBUS_STBUS_CONFIG);
} while ((reg & 0x7FFFFFFF) != req_reg);
#endif /* QQQ - TO DO */
}
extern void fli7510_usb_init(const enum fli7510_usb_ovrcur_mode ovrcur_mode)
{
unsigned long sysconf;
switch (ovrcur_mode) {
case fli7510_usb_ovrcur_disabled:
/* CONFIG_SYS_COMMS_CONFIG_1[12] = usba_enable_pad_override */
sysconf = readl(CONFIG_SYS_COMMS_CONFIG_1);
SET_SYSCONF_BIT(sysconf, 1, USBA_ENABLE_PAD_OVERRIDE);
writel(sysconf, CONFIG_SYS_COMMS_CONFIG_1);
/* CONFIG_SYS_COMMS_CONFIG_1[13] = usba_ovrcur */
sysconf = readl(CONFIG_SYS_COMMS_CONFIG_1);
SET_SYSCONF_BIT(sysconf, 1, USBA_OVRCUR);
writel(sysconf, CONFIG_SYS_COMMS_CONFIG_1);
break;
default:
/* CONFIG_SYS_COMMS_CONFIG_1[12] = usba_enable_pad_override */
sysconf = readl(CONFIG_SYS_COMMS_CONFIG_1);
SET_SYSCONF_BIT(sysconf, 0, USBA_ENABLE_PAD_OVERRIDE);
writel(sysconf, CONFIG_SYS_COMMS_CONFIG_1);
/* CONFIG_SYS_COMMS_CONFIG_1[11] = usba_ovrcur_polarity */
switch (ovrcur_mode) {
case fli7510_usb_ovrcur_active_high:
sysconf = readl(CONFIG_SYS_COMMS_CONFIG_1);
SET_SYSCONF_BIT(sysconf, 0, USBA_OVRCUR_POLARITY);
writel(sysconf, CONFIG_SYS_COMMS_CONFIG_1);
break;
case fli7510_usb_ovrcur_active_low:
sysconf = readl(CONFIG_SYS_COMMS_CONFIG_1);
SET_SYSCONF_BIT(sysconf, 1, USBA_OVRCUR_POLARITY);
writel(sysconf, CONFIG_SYS_COMMS_CONFIG_1);
break;
default:
BUG();
break;
}
break;
}
/* now route the PIOs corectly */
SET_PIO_PIN(ST40_PIO_BASE(27), 1, STPIO_IN); /* USB_A_OVRCUR */
SET_PIO_PIN(ST40_PIO_BASE(27), 2, STPIO_ALT_OUT); /* USB_A_PWREN */
/* start the USB Wrapper Host Controller */
ST40_start_host_control(
USB_FLAGS_STRAP_16BIT |
USB_FLAGS_STRAP_PLL |
USB_FLAGS_STBUS_CONFIG_THRESHOLD256);
}
static void configPIO(void)
{
/* Setup PIO of ASC device */
SET_PIO_ASC(PIO_PORT(4), 3, 2, 4, 5);
/* Setup up ethernet reset */
SET_PIO_PIN(PIO_PORT(2), 6, STPIO_OUT);
}
static void configPIO(void)
{
/* Setup PIOs for ASC device */
#if CFG_STM_ASC_BASE == ST40_ASC3_REGS_BASE
/*
* Route UART3 via PIO24/25 for TX, RX, RTS & CTS (Alternative #1).
*
* Note: on the MB903A, RS232_RTS is connected (incorrectly)
* to PIO24[6], this is corrected in MB903B.
*/
PIOALT(24, 4, 1, &stx7108_pioalt_pad_out); /* UART3-TX */
PIOALT(24, 5, 1, &stx7108_pioalt_pad_in); /* UART3-RX */
PIOALT(24, 7, 1, &stx7108_pioalt_pad_out); /* UART3-RTS */
PIOALT(25, 0, 1, &stx7108_pioalt_pad_in); /* UART3-CTS */
#else
#error Unknown ASC port selected!
#endif /* CFG_STM_ASC_BASE == ST40_ASCx_REGS_BASE */
#ifdef CONFIG_DRIVER_NET_STM_GMAC
/*
* Configure the Ethernet PHY Reset signal
* PIO20[0] == GMII0_notRESET
* PIO15[4] == GMII1_notRESET
*/
SET_PIO_PIN(ST40_PIO_BASE(15), 4, STPIO_OUT);
#endif /* CONFIG_DRIVER_NET_STM_GMAC */
}
static void configEthernet(void)
{
/* Setup PIO for the PHY's reset */
SET_PIO_PIN(PIO_PORT(1),6,STPIO_OUT); /* PHY_RES is on PIO1[6] */
/* Finally, just toggle the PHY Reset pin */
STPIO_SET_PIN(PIO_PORT(1), 6, 0); /* Assert PHY_RES */
udelay(100); /* small delay (100us) */
STPIO_SET_PIN(PIO_PORT(1), 6, 1); /* de-assert PHY_RES */
}
static void configSpi(void)
{
#if defined(CONFIG_SOFT_SPI)
/* Configure SPI Serial Flash for PIO "bit-banging" */
/* SPI is on PIO2[2:0], with CS on PIO6[7] */
SET_PIO_PIN(PIO_PORT(2),0,STPIO_OUT); /* SPI_CLK */
SET_PIO_PIN(PIO_PORT(2),1,STPIO_OUT); /* SPI_DOUT */
SET_PIO_PIN(PIO_PORT(2),2,STPIO_IN); /* SPI_DIN */
SET_PIO_PIN(PIO_PORT(6),7,STPIO_OUT); /* SPI_NOTCS */
/* drive outputs with sensible initial values */
STPIO_SET_PIN(PIO_PORT(6), 7, 1); /* deassert SPI_NOCS */
STPIO_SET_PIN(PIO_PORT(2), 0, 1); /* assert SPI_CLK */
STPIO_SET_PIN(PIO_PORT(2), 1, 0); /* deassert SPI_DOUT */
#else
#error Still to impliment SPI via SSC for the STx7111.
#endif /* CONFIG_SOFT_SPI */
}
static void configPIO(void)
{
/* Setup PIO of ASC device */
SET_PIO_ASC(PIO_PORT(4), 3, 2, 4, 5); /* UART2 - AS0 */
SET_PIO_ASC(PIO_PORT(5), 4, 3, 5, 6); /* UART3 - AS1 */
#ifdef CONFIG_DRIVER_NETSTMAC
/* Reset the on-board STe101P PHY */
SET_PIO_PIN(PIO_PORT(4), 7, STPIO_OUT);
STPIO_SET_PIN(PIO_PORT(4), 7, 1);
udelay(1);
STPIO_SET_PIN(PIO_PORT(4), 7, 0);
udelay(1);
STPIO_SET_PIN(PIO_PORT(4), 7, 1);
#endif /* CONFIG_DRIVER_NETSTMAC */
#if defined(CONFIG_CMD_NAND)
/* Setup PIO for NAND FLASH devices: Ready/Not_Busy */
SET_PIO_PIN(PIO_PORT(2), 7, STPIO_IN);
#endif /* CONFIG_CMD_NAND */
}
static void configPIO(void)
{
/* Setup PIOs for ASC device */
#if CONFIG_SYS_STM_ASC_BASE == ST40_ASC1_REGS_BASE
/* Route UART1 via PIO5 for TX, RX, CTS & RTS (Alternative #1) */
PIOALT(5, 1, 1, stm_pad_direction_output); /* UART1-TX */
PIOALT(5, 2, 1, stm_pad_direction_input); /* UART1-RX */
PIOALT(5, 4, 1, stm_pad_direction_output); /* UART1-RTS */
PIOALT(5, 3, 1, stm_pad_direction_input); /* UART1-CTS */
#elif CONFIG_SYS_STM_ASC_BASE == ST40_ASC3_REGS_BASE
/* Route UART3 via PIO24/25 for TX, RX (Alternative #1) */
PIOALT(24, 4, 1, stm_pad_direction_output); /* UART3-TX */
PIOALT(24, 5, 1, stm_pad_direction_input); /* UART3-RX */
// PIOALT(24, 7, 1, stm_pad_direction_output); /* UART3-RTS */
// PIOALT(25, 0, 1, stm_pad_direction_input); /* UART3-CTS */
#else
#error Unknown ASC port selected!
#endif /* CONFIG_SYS_STM_ASC_BASE == ST40_ASCx_REGS_BASE */
#ifdef CONFIG_DRIVER_NET_STM_GMAC
/*
* Configure the Ethernet PHY Reset signal
* PIO15[4] == POWER_ON_ETH (a.k.a. ETH_RESET)
*/
SET_PIO_PIN(ST40_PIO_BASE(15), 4, STPIO_OUT);
#endif /* CONFIG_DRIVER_NET_STM_GMAC */
/*
* Some of the peripherals are powered by regulators
* controlled by the following PIO line...
* PIO5[0] == POWER_ON
*/
SET_PIO_PIN(ST40_PIO_BASE(5), 0, STPIO_OUT);
STPIO_SET_PIN(ST40_PIO_BASE(5), 0, 1);
}
static void configSpi(void)
{
unsigned long sysconf;
/*
* CONFIG_SYS_COMMS_CONFIG_2[13] = spi_enable = 0
* i.e. disable the SPI boot-controller.
*/
sysconf = readl(CONFIG_SYS_COMMS_CONFIG_2);
sysconf &= ~(1ul<<13);
writel(sysconf, CONFIG_SYS_COMMS_CONFIG_2);
/*
* For both S/W "bit-banging" and H/W SSC, the SPI is on PIO17[5:0].
* Now, we set up the PIO pins correctly.
*/
SET_PIO_PIN(PIO_PORT(17),5,STPIO_IN); /* SPI_MISO */
SET_PIO_PIN(PIO_PORT(17),4,STPIO_OUT); /* SPI_CSN */
#if defined(CONFIG_SOFT_SPI) /* Configure SPI Serial Flash for PIO "bit-banging" */
SET_PIO_PIN(PIO_PORT(17),2,STPIO_OUT); /* SPI_CLK */
SET_PIO_PIN(PIO_PORT(17),3,STPIO_OUT); /* SPI_MOSI */
#elif defined(CONFIG_STM_SSC_SPI) /* Use the H/W SSC for SPI */
SET_PIO_PIN(PIO_PORT(17),2,STPIO_ALT_OUT);/* SPI_CLK */
SET_PIO_PIN(PIO_PORT(17),3,STPIO_ALT_OUT);/* SPI_MOSI */
#endif /* CONFIG_SOFT_SPI */
/* drive (non-SSC) outputs with sensible initial values */
STPIO_SET_PIN(PIO_PORT(17), 4, 1); /* deassert SPI_CSN */
#if defined(CONFIG_SOFT_SPI)
STPIO_SET_PIN(PIO_PORT(17), 2, 1); /* assert SPI_CLK */
STPIO_SET_PIN(PIO_PORT(17), 3, 0); /* deassert SPI_MOSI */
#endif /* CONFIG_SOFT_SPI */
}
static void configI2c(void)
{
/*
* The I2C busses are routed as follows:
*
* Bus SCL SDA
* --- --- ---
* 1 PIO10[2] PIO10[3]
* 2 PIO9[4] PIO9[5]
* 3 PIO9[6] PIO9[7]
*/
#if defined(CONFIG_I2C_BUS_1) /* Use I2C Bus "1" */
SET_PIO_PIN(PIO_PORT(10),2,STPIO_BIDIR);/* I2C1_SCL */
SET_PIO_PIN(PIO_PORT(10),3,STPIO_BIDIR);/* I2C1_SDA */
#elif defined(CONFIG_I2C_BUS_2) /* Use I2C Bus "2" */
SET_PIO_PIN(PIO_PORT(9),4,STPIO_BIDIR); /* I2C2_SCL */
SET_PIO_PIN(PIO_PORT(9),5,STPIO_BIDIR); /* I2C2_SDA */
#elif defined(CONFIG_I2C_BUS_3) /* Use I2C Bus "3" */
SET_PIO_PIN(PIO_PORT(9),6,STPIO_BIDIR); /* I2C3_SCL */
SET_PIO_PIN(PIO_PORT(9),7,STPIO_BIDIR); /* I2C3_SDA */
#else
#error Unknown I2C Bus!
#endif
}
/*
* ETH GMAC PIO configuration
*/
extern void fli7540_configure_ethernet(
const enum fli7540_ethernet_mode mode,
const int ext_clk,
const int phy_bus)
{
struct fli7540_gmac_pin *pins;
int pins_num;
unsigned char phy_sel, enmii;
int i;
unsigned long sysconf;
/* Ethernet interface on */
/* CONFIG_SYS_COMMS_CONFIG_2[24] = gmac_enable */
sysconf = readl(CONFIG_SYS_COMMS_CONFIG_2);
SET_SYSCONF_BIT(sysconf, 1, GMAC_ENABLE);
writel(sysconf, CONFIG_SYS_COMMS_CONFIG_2);
switch (mode) {
case fli7540_ethernet_mii:
phy_sel = 0;
enmii = 1;
pins = fli7540_gmac_mii_pins;
pins_num = ARRAY_SIZE(fli7540_gmac_mii_pins);
break;
case fli7540_ethernet_rmii:
phy_sel = 4;
enmii = 1;
pins = fli7540_gmac_rmii_pins;
pins_num = ARRAY_SIZE(fli7540_gmac_rmii_pins);
break;
case fli7540_ethernet_gmii:
phy_sel = 0;
enmii = 1;
pins = fli7540_gmac_gmii_pins;
pins_num = ARRAY_SIZE(fli7540_gmac_gmii_pins);
/* CONFIG_SYS_COMMS_CONFIG_1[18:17] = conf_pio24_alternate */
sysconf = readl(CONFIG_SYS_COMMS_CONFIG_1);
sysconf &= ~(0x3ul<<CONF_PIO24_ALTERNATE);
sysconf |= (0x2ul<<CONF_PIO24_ALTERNATE);
writel(sysconf, CONFIG_SYS_COMMS_CONFIG_1);
break;
case fli7540_ethernet_reverse_mii:
phy_sel = 0;
enmii = 0;
pins = fli7540_gmac_reverse_mii_pins;
pins_num = ARRAY_SIZE(fli7540_gmac_reverse_mii_pins);
break;
default:
BUG();
return;
}
/* CONFIG_SYS_COMMS_CONFIG_2[28:26] = phy_intf_sel */
sysconf = readl(CONFIG_SYS_COMMS_CONFIG_2);
sysconf &= ~(0x7ul<<PHY_INTF_SEL);
sysconf |= (phy_sel<<PHY_INTF_SEL);
// writel(sysconf, CONFIG_SYS_COMMS_CONFIG_2);
/* CONFIG_SYS_COMMS_CONFIG_2[8] = gmac_mii_enable */
// sysconf = readl(CONFIG_SYS_COMMS_CONFIG_2);
SET_SYSCONF_BIT(sysconf, enmii, GMAC_MII_ENABLE);
// writel(sysconf, CONFIG_SYS_COMMS_CONFIG_2);
/* CONFIG_SYS_COMMS_CONFIG_2[9] = gmac_phy_clock_sel */
// sysconf = readl(CONFIG_SYS_COMMS_CONFIG_2);
SET_SYSCONF_BIT(sysconf, ext_clk, GMAC_PHY_CLOCK_SEL);
writel(sysconf, CONFIG_SYS_COMMS_CONFIG_2);
/* choose the correct direction for PHYCLK */
pins[0].dir = (ext_clk) ? STPIO_IN : STPIO_ALT_OUT;
/* set all the PIOs correctly */
for (i = 0; i < pins_num; i++)
{
SET_PIO_PIN(ST40_PIO_BASE(pins[i].port), pins[i].pin, pins[i].dir);
}
}
/* ETH MAC pad configuration */
static void stmac_eth_hw_setup( int reverse_mii, int rmii_mode, int mode,
int ext_mdio, int ext_clk, int phy_bus)
{
unsigned long sysconf;
sysconf = *STX7105_SYSCONF_SYS_CFG07;
/* Ethernet ON */
sysconf |= (ETHERNET_INTERFACE_ON);
/* MII M-DIO select: 1: miim_dio from external input, 0: from GMAC */
if (ext_mdio)
sysconf |= (EXT_MDIO);
else
sysconf &= ~(EXT_MDIO);
/* RMII pin multiplexing: 0: MII interface active, 1: RMII interface */
/* cut 1: This register was not connected, so only MII available */
if (rmii_mode)
sysconf |= (RMII_MODE);
else
sysconf &= ~(RMII_MODE);
/*
* PHY EXT CLOCK: 0: provided by STx7105; 1: external
* cut 1: sysconf7[19], however this was not connected, so only
* input supported.
* cut 2: direction now based on PIO direction, so this code removed.
*/
/* Default GMII/MII selection */
sysconf &= ~(PHY_INTF_SEL_MASK);
sysconf |= ((mode&3ul)<<25);
/* MII mode */
if (reverse_mii)
sysconf &= ~(ENMII);
else
sysconf |= (ENMII);
*STX7105_SYSCONF_SYS_CFG07 = sysconf;
/* Pin configuration... */
/* PIO7[4] CFG37[8+4,4] = Alternate1 = MIIRX_DV/MII_EXCRS */
/* PIO7[5] CFG37[8+5,5] = Alternate1 = MIIRX_ER/MII_EXCOL */
/* PIO7[6] CFG37[8+6,6] = Alternate1 = MIITXD[0] */
/* PIO7[7] CFG37[8+7,7] = Alternate1 = MIITXD[1] */
sysconf = *STX7105_SYSCONF_SYS_CFG37;
sysconf &= ~(0xf0f0ul); /* Mask=3,3,3,3 */
sysconf |= 0x0000ul; /* OR =0,0,0,0 */
*STX7105_SYSCONF_SYS_CFG37 = sysconf;
SET_PIO_PIN(PIO_PORT(7), 4, STPIO_IN);
SET_PIO_PIN(PIO_PORT(7), 5, STPIO_IN);
SET_PIO_PIN(PIO_PORT(7), 6, STPIO_ALT_OUT);
SET_PIO_PIN(PIO_PORT(7), 7, STPIO_ALT_OUT);
/* PIO8[0] CFG46[8+0,0] = Alternate1 = MIITXD[2] */
/* PIO8[1] CFG46[8+1,1] = Alternate1 = MIITXD[3] */
/* PIO8[2] CFG46[8+2,2] = Alternate1 = MIITX_EN */
/* PIO8[3] CFG46[8+3,3] = Alternate1 = MIIMDIO */
/* PIO8[4] CFG46[8+4,4] = Alternate1 = MIIMDC */
/* PIO8[5] CFG46[8+5,5] = Alternate1 = MIIRXCLK */
/* PIO8[6] CFG46[8+6,6] = Alternate1 = MIIRXD[0] */
/* PIO8[7] CFG46[8+7,7] = Alternate1 = MIIRXD[1] */
sysconf = *STX7105_SYSCONF_SYS_CFG46;
sysconf &= ~(0xfffful); /* Mask=3,3,3,3,3,3,3,3 */
sysconf |= 0x0000ul; /* OR =0,0,0,0,0,0,0,0 */
*STX7105_SYSCONF_SYS_CFG46 = sysconf;
SET_PIO_PIN(PIO_PORT(8), 0, STPIO_ALT_OUT);
SET_PIO_PIN(PIO_PORT(8), 1, STPIO_ALT_OUT);
SET_PIO_PIN(PIO_PORT(8), 2, STPIO_ALT_OUT);
SET_PIO_PIN(PIO_PORT(8), 3, STPIO_ALT_BIDIR);
SET_PIO_PIN(PIO_PORT(8), 4, STPIO_ALT_OUT);
SET_PIO_PIN(PIO_PORT(8), 5, STPIO_IN);
SET_PIO_PIN(PIO_PORT(8), 6, STPIO_IN);
SET_PIO_PIN(PIO_PORT(8), 7, STPIO_IN);
/* PIO9[0] CFG47[8+0,0] = Alternate1 = MIIRXD[2] */
/* PIO9[1] CFG47[8+1,1] = Alternate1 = MIIRXD[3] */
/* PIO9[2] CFG47[8+2,2] = Alternate1 = MIITXCLK */
/* PIO9[3] CFG47[8+3,3] = Alternate1 = MIICOL */
/* PIO9[4] CFG47[8+4,4] = Alternate1 = MIICRS */
/* PIO9[5] CFG47[8+5,5] = Alternate1 = MIIPHYCLK */
/* PIO9[6] CFG47[8+6,6] = Alternate1 = MIIMDINT */
sysconf = *STX7105_SYSCONF_SYS_CFG47;
sysconf &= ~(0x7f7ful); /* Mask=3,3,3,3,3,3,3 */
sysconf |= 0x0000ul; /* OR =0,0,0,0,0,0,0 */
*STX7105_SYSCONF_SYS_CFG47 = sysconf;
SET_PIO_PIN(PIO_PORT(9), 0, STPIO_IN);
SET_PIO_PIN(PIO_PORT(9), 1, STPIO_IN);
SET_PIO_PIN(PIO_PORT(9), 2, STPIO_IN);
SET_PIO_PIN(PIO_PORT(9), 3, STPIO_IN);
SET_PIO_PIN(PIO_PORT(9), 4, STPIO_IN);
/* MIIPHYCLK */
/* Not implemented in cut 1 (DDTS GNBvd69906) - clock never output */
/* In cut 2 PIO direction used to control input or output. */
if (ext_clk)
SET_PIO_PIN(PIO_PORT(9), 5, STPIO_IN);
else
SET_PIO_PIN(PIO_PORT(9), 5, STPIO_ALT_OUT);
SET_PIO_PIN(PIO_PORT(9), 6, STPIO_IN);
}
extern void stx7200_usb_init(void)
{
const bd_t * const bd = gd->bd;
unsigned long reg;
const unsigned char power_pins[3] = {1, 3, 4};
const unsigned char oc_pins[3] = {0, 2, 5};
#if CONFIG_SYS_USB_BASE == CONFIG_SYS_USB0_BASE
const size_t port = 0;
#elif CONFIG_SYS_USB_BASE == CONFIG_SYS_USB1_BASE
const size_t port = 1;
#elif CONFIG_SYS_USB_BASE == CONFIG_SYS_USB2_BASE
const size_t port = 2;
#else
#error Unknown USB Host Controller Base Address
#endif
/* ClockgenB powers up with all the frequency synths bypassed.
* Enable them all here. Without this, USB 1.1 doesn't work,
* as it needs a 48MHz clock which is separate from the USB 2
* clock which is derived from the SATA clock. */
writel(0, STX7200_CLOCKGENB_OUT_MUX_CFG);
/* route USB and parts of MAFE instead of DVO.*/
/* DVO output selection (probably ignored). */
reg = readl(STX7200_SYSCONF_SYS_CFG07);
reg &= ~(1ul<<26); /* conf_pad_pio[2] = 0 */
reg &= ~(1ul<<27); /* conf_pad_pio[3] = 0 */
writel(reg, STX7200_SYSCONF_SYS_CFG07);
/* Enable soft JTAG mode for USB and SATA */
reg = readl(STX7200_SYSCONF_SYS_CFG33);
reg |= (1ul<<6); /* soft_jtag_en = 1 */
reg &= ~(0xful<<0); /* tck = tdi = trstn_usb = tms_usb = 0 */
writel(reg, STX7200_SYSCONF_SYS_CFG33);
#ifdef CONFIG_USB_STI7200_CUT1_SOFT_JTAG_RESET_WORKAROUND
/* reset USB HC via the JTAG scan path */
usb_soft_jtag_reset();
#endif
/* USB power */
SET_PIO_PIN(PIO_PORT(7), power_pins[port], STPIO_ALT_OUT);
STPIO_SET_PIN(PIO_PORT(7), power_pins[port], 1);
/* USB Over-Current */
if (STX7200_DEVICEID_CUT(bd->bi_devid) < 2)
SET_PIO_PIN(PIO_PORT(7), oc_pins[port], STPIO_ALT_BIDIR);
else
SET_PIO_PIN(PIO_PORT(7), oc_pins[port], STPIO_IN);
/* tusb_powerdown_req[port] = 0 */
reg = readl(STX7200_SYSCONF_SYS_CFG22);
reg &= ~(1ul<<(port+3));
writel(reg, STX7200_SYSCONF_SYS_CFG22);
/* Set strap mode */
#define STRAP_MODE AHB2STBUS_STRAP_16_BIT
reg = readl(AHB2STBUS_STRAP);
#if STRAP_MODE == 0
reg &= ~AHB2STBUS_STRAP_16_BIT;
#else
reg |= STRAP_MODE;
#endif
writel(reg, AHB2STBUS_STRAP);
/* Start PLL */
reg = readl(AHB2STBUS_STRAP);
writel(reg | AHB2STBUS_STRAP_PLL, AHB2STBUS_STRAP);
udelay(100000); /* QQQ: can this delay be shorter ? */
writel(reg & (~AHB2STBUS_STRAP_PLL), AHB2STBUS_STRAP);
udelay(100000); /* QQQ: can this delay be shorter ? */
/* Set the STBus Opcode Config for 32-bit access */
writel(AHB2STBUS_STBUS_OPC_32BIT, AHB2STBUS_STBUS_OPC);
/* Set the Message Size Config to 4 packets per message */
writel(AHB2STBUS_MSGSIZE_4, AHB2STBUS_MSGSIZE);
/* Set the Chunk Size Config to 4 packets per chunk */
writel(AHB2STBUS_CHUNKSIZE_4, AHB2STBUS_CHUNKSIZE);
}
extern void fli7540_usb_init(
const int port,
const enum fli7540_usb_ovrcur_mode ovrcur_mode)
{
static int xtal_initialized;
int clken, rstn;
int override, ovrcur, polarity;
unsigned long sysconf;
if (!xtal_initialized++)
{
sysconf = readl(CONFIG_SYS_SPARE_1);
#if defined(CONFIG_ST40_FLI7510)
SET_SYSCONF_BIT(sysconf, 0, USB_XTAL_VALID);
#else
SET_SYSCONF_BIT(sysconf, 1, USB_XTAL_VALID);
#endif /* CONFIG_ST40_FLI7510 */
writel(sysconf, CONFIG_SYS_SPARE_1);
}
switch (port) {
case 0:
clken = 21;
rstn = 23;
override = 12;
ovrcur = 13;
polarity = 11;
#if defined(CONFIG_ST40_FLI7510)
SET_PIO_PIN(ST40_PIO_BASE(27), 1, STPIO_IN); /* USB_A_OVRCUR */
SET_PIO_PIN(ST40_PIO_BASE(27), 2, STPIO_ALT_OUT); /* USB_A_PWREN */
#else
SET_PIO_PIN(ST40_PIO_BASE(26), 3, STPIO_IN); /* USB_A_OVRCUR */
SET_PIO_PIN(ST40_PIO_BASE(26), 4, STPIO_ALT_OUT); /* USB_A_PWREN */
#endif /* CONFIG_ST40_FLI7510 */
break;
case 1:
clken = 22;
rstn = 24;
override = 15;
