static void ecc_perform(int setting, int sectors, uint8_t* sectorData, uint8_t* eccData) { SET_REG(NANDECC + NANDECC_CLEARINT, 1); SET_REG(NANDECC + NANDECC_SETUP, ((sectors - 1) & 0x3) | setting); SET_REG(NANDECC + NANDECC_DATA, (uint32_t) sectorData); SET_REG(NANDECC + NANDECC_ECC, (uint32_t) eccData); CleanCPUDataCache(); SET_REG(NANDECC + NANDECC_START, 1); }
static void ecc_generate(int setting, int sectors, uint8_t* sectorData, uint8_t* eccData) { SET_REG(NANDECC + NANDECC_CLEARINT, 1); SET_REG(NANDECC + NANDECC_SETUP, ((sectors - 1) & 0x3) | setting); SET_REG(NANDECC + NANDECC_DATA, (uint32_t) sectorData); SET_REG(NANDECC + NANDECC_ECC, (uint32_t) eccData); CleanAndInvalidateCPUDataCache(); SET_REG(NANDECC + NANDECC_START, 2); }
void usb_phy_shutdown() { SET_REG(USB_PHY + OPHYPWR, OPHYPWR_FORCESUSPEND | OPHYPWR_PLLPOWERDOWN | OPHYPWR_XOPOWERDOWN | OPHYPWR_ANALOGPOWERDOWN | OPHYPWR_UNKNOWNPOWERDOWN); // power down phy SET_REG(USB_PHY + ORSTCON, ORSTCON_PHYSWRESET); // reset phy/link // reset unknown register SET_REG(USB_PHY + OPHYUNK1, GET_REG(USB_PHY + OPHYUNK1) & (~OPHYUNK1_STOP_MASK)); udelay(USB_RESET_DELAYUS); // wait a millisecond for the changes to stick }
//----------------------------------------------- //выключение SPI1 void spi1_unconfig(void) { SET_REG( LPC_PINCON->PINSEL0, 0, 15*2, 2); SET_REG( LPC_PINCON->PINSEL1, 0, (16-16)*2, 2); SET_REG( LPC_PINCON->PINSEL1, 0, (17-16)*2, 2); SET_REG( LPC_PINCON->PINSEL1, 0, (18-16)*2, 2); LPC_SPI->SPCR=0x00; }
void gpio_interrupt_enable(uint32_t interrupt) { int group = interrupt >> 5; int index = interrupt & 0x1f; EnterCriticalSection(); SET_REG(GPIOIC + GPIO_INTSTAT + (0x4 * group), 1 << index); SET_REG(GPIOIC + GPIO_INTEN + (0x4 * group), GET_REG(GPIOIC + GPIO_INTEN + (0x4 * group)) | (1 << index)); LeaveCriticalSection(); }
int dma_request(int Source, int SourceTransferWidth, int SourceBurstSize, int Destination, int DestinationTransferWidth, int DestinationBurstSize, int* controller, int* channel, DMAHandler handler) { if(*controller == 0) { *controller = ControllerLookupTable[Source] & ControllerLookupTable[Destination]; if(*controller == 0) { return ERROR_DMA; } while(getFreeChannel(controller, channel) == ERROR_BUSY); requests[*controller - 1][*channel].started = TRUE; requests[*controller - 1][*channel].done = FALSE; requests[*controller - 1][*channel].handler = handler; } uint32_t DMACControl; uint32_t DMACConfig; if(*controller == 1) { DMACControl = DMAC0 + DMAC0Control0 + (*channel * DMAChannelRegSize); DMACConfig = DMAC0 + DMACConfiguration; } else if(*controller == 2) { DMACControl = DMAC1 + DMAC0Control0 + (*channel * DMAChannelRegSize); DMACConfig = DMAC1 + DMACConfiguration; } else { return ERROR_DMA; } uint32_t config = 0; SET_REG(DMACConfig, DMACConfiguration_ENABLE); config |= (SourceTransferWidth / 2) << DMAC0Control0_SWIDTHSHIFT; // 4 -> 2, 2 -> 1, 1 -> 0 config |= (DestinationTransferWidth / 2) << DMAC0Control0_DWIDTHSHIFT; // 4 -> 2, 2 -> 1, 1 -> 0 int x; for(x = 0; x < 7; x++) { if((1 << (x + 1)) >= SourceBurstSize) { config |= x << DMAC0Control0_SBSIZESHIFT; break; } } for(x = 0; x < 7; x++) { if((1 << (x + 1)) >= DestinationBurstSize) { config |= x << DMAC0Control0_DBSIZESHIFT; break; } } config |= 1 << DMAC0Control0_TERMINALCOUNTINTERRUPTENABLE; config |= 1 << DMAC0Control0_SOURCEAHBMASTERSELECT; SET_REG(DMACControl, config); return 0; }
static int si3054_switch_put(snd_kcontrol_t *kcontrol, snd_ctl_elem_value_t *uvalue) { struct hda_codec *codec = snd_kcontrol_chip(kcontrol); u16 reg = PRIVATE_REG(kcontrol->private_value); u16 mask = PRIVATE_MASK(kcontrol->private_value); if (uvalue->value.integer.value[0]) SET_REG(codec, reg, (GET_REG(codec, reg)) | mask); else SET_REG(codec, reg, (GET_REG(codec, reg)) & ~mask); return 0; }
int power_ctrl(uint32_t device, OnOff on_off) { if(on_off == ON) { SET_REG(POWER + POWER_ONCTRL, device); } else { SET_REG(POWER + POWER_OFFCTRL, device); } /* wait for the new state to take effect */ while((GET_REG(POWER + POWER_SETSTATE) & device) != (GET_REG(POWER + POWER_STATE) & device)); return 0; }
int gpio_set_irq_type(rt_uint32_t gpio, rt_uint32_t type) { rt_uint32_t int_type, int_polarity; rt_uint32_t bit = gpio % 32; rt_uint32_t base; if (!gpio_available[gpio]) { rt_kprintf("ERROR: %s, GPIO %d is not available\n", __func__, gpio); return -RT_EBUSY; } base = gpio_to_base(gpio); int_type = GET_REG(base + REG_GPIO_INTTYPE_LEVEL); int_polarity = GET_REG(base + REG_GPIO_INT_POLARITY); switch (type & IRQ_TYPE_TRIGGER_MASK) { case IRQ_TYPE_EDGE_BOTH: int_type |= BIT(bit); // toggle trigger if (gpio_get_value(gpio)) int_polarity &= ~BIT(bit); else int_polarity |= BIT(bit); break; case IRQ_TYPE_EDGE_RISING: int_type |= BIT(bit); int_polarity |= BIT(bit); break; case IRQ_TYPE_EDGE_FALLING: int_type |= BIT(bit); int_polarity &= ~BIT(bit); break; case IRQ_TYPE_LEVEL_HIGH: int_type &= ~BIT(bit); int_polarity |= BIT(bit); break; case IRQ_TYPE_LEVEL_LOW: int_type &= ~BIT(bit); int_polarity &= ~BIT(bit); break; case IRQ_TYPE_NONE: return 0; default: return -RT_ERROR; } SET_REG(base + REG_GPIO_INTTYPE_LEVEL, int_type); SET_REG(base + REG_GPIO_INT_POLARITY, int_polarity); return 0; }
int interrupt_enable(int irq_no) { if(irq_no >= VIC_MaxInterrupt) { return -1; } EnterCriticalSection(); if(irq_no < VIC_InterruptSeparator) { SET_REG(VIC0 + VICINTENABLE, GET_REG(VIC0 + VICINTENABLE) | (1 << irq_no)); #ifndef CONFIG_IPHONE_4 } else { SET_REG(VIC1 + VICINTENABLE, GET_REG(VIC1 + VICINTENABLE) | (1 << (irq_no - VIC_InterruptSeparator))); #else } else if(irq_no < VIC_InterruptSeparator*2) {
/** Initialize the USB device controller hardware of the STM32. */ static usbd_device *st_usbfs_v2_usbd_init(void) { rcc_periph_clock_enable(RCC_USB); SET_REG(USB_CNTR_REG, 0); SET_REG(USB_BTABLE_REG, 0); SET_REG(USB_ISTR_REG, 0); /* Enable RESET, SUSPEND, RESUME and CTR interrupts. */ SET_REG(USB_CNTR_REG, USB_CNTR_RESETM | USB_CNTR_CTRM | USB_CNTR_SUSPM | USB_CNTR_WKUPM); SET_REG(USB_BCDR_REG, USB_BCDR_DPPU); return &st_usbfs_dev; }
// Configure fifo settings // i2c_slv_addr: 0xN // clkout_en: (on|off) // aux_burst_addr: 0xN uint8_t itg_config_aux(Sensor *s, KeyVal * pairs) { // Fetch the current register value uint8_t byte = FETCH_REG(ITG_AUX_SLV_ADDR), reg_val = byte; // Keep track of register changes int applied = 0; // Iterate through the settings do { if (!pairs->applied) { pairs->applied = 1; // If the i2c_slv_addr key if (!strcmp(pairs->key, "i2c_slv_addr")) { // Configure the aux i2c slave addr process_i2c_slv_addr_key(®_val, pairs->val); } // Else if the clkout_en key else if (!strcmp(pairs->key, "clkout_en")) { // Configure the reference clock out process_clkout_en_key(®_val, pairs->val); } // Else if the burst addr else if (!strcmp(pairs->key, "aux_burst_addr")) { // Configure the auxiliary device burst address uint8_t addr = 0xff & DEX_TO_INT(pairs->val); SET_REG(ITG_AUX_ADDR, addr); applied++; } // Else not supported key else { // So set applied to false pairs->applied = 0; } } } while ((pairs = pairs->next)); // If the new reg val is different from the current if (reg_val != byte) { // Set the register value to reg_val SET_REG(ITG_AUX_SLV_ADDR, reg_val); // Return 1 to signify applied change applied++; } // Return number of applied changes return applied; }
static void usb_set_global_out_nak() { usb_global_out_nak++; if(usb_global_out_nak > 1) return; //bufferPrintf("USB: SGOUTNAK\n"); SET_REG(USB + GINTSTS, GINTMSK_GOUTNAKEFF); SET_REG(USB + DCTL, GET_REG(USB + DCTL) | DCTL_SGOUTNAK); while ((GET_REG(USB + GINTSTS) & GINTMSK_GOUTNAKEFF) != GINTMSK_GOUTNAKEFF); SET_REG(USB + GINTSTS, GINTMSK_GOUTNAKEFF); }
void usb_phy_init() { // power on PHY SET_REG(USB_PHY + OPHYPWR, OPHYPWR_POWERON); udelay(USB_PHYPWRPOWERON_DELAYUS); // select clock SET_REG(USB_PHY + OPHYCLK, (GET_REG(USB_PHY + OPHYCLK) & (~OPHYCLK_CLKSEL_MASK)) | OPHYCLK_CLKSEL_48MHZ); // reset phy SET_REG(USB_PHY + ORSTCON, GET_REG(USB_PHY + ORSTCON) | ORSTCON_PHYSWRESET); udelay(USB_RESET2_DELAYUS); SET_REG(USB_PHY + ORSTCON, GET_REG(USB_PHY + ORSTCON) & (~ORSTCON_PHYSWRESET)); udelay(USB_RESET_DELAYUS); }
/********************************************************************************************************* ** 函数名称: sio16c550Hup ** 功能描述: 串口接口挂起 ** 输 入 : psiochan SIO CHAN ** 输 出 : ERROR or OK ** 全局变量: ** 调用模块: *********************************************************************************************************/ static INT sio16c550Hup (SIO16C550_CHAN *psiochan) { INTREG intreg; intreg = KN_INT_DISABLE(); psiochan->mcr &= (~(MCR_RTS | MCR_DTR)); SET_REG(psiochan, MCR, psiochan->mcr); SET_REG(psiochan, FCR, (RxCLEAR | TxCLEAR)); KN_INT_ENABLE(intreg); return (ERROR_NONE); }
/********************************************************************************************************* ** 函数名称: sio16550SetMode ** 功能描述: 串口接口设置模式 ** 输 入 : psiochan SIO CHAN ** newmode 新的模式 SIO_MODE_INT / SIO_MODE_POLL ** 输 出 : ERROR or OK ** 全局变量: ** 调用模块: *********************************************************************************************************/ static INT sio16c550SetMode (SIO16C550_CHAN *psiochan, INT newmode) { INTREG intreg; UINT8 mask; if ((newmode != SIO_MODE_POLL) && (newmode != SIO_MODE_INT)) { _ErrorHandle(EINVAL); return (PX_ERROR); } if (psiochan->channel_mode == newmode) { return (ERROR_NONE); } intreg = KN_INT_DISABLE(); if (newmode == SIO_MODE_INT) { /* * Enable appropriate interrupts */ if (psiochan->hw_option & CLOCAL) { SET_REG(psiochan, IER, (psiochan->ier | RxFIFO_BIT | TxFIFO_BIT)); } else { mask = (UINT8)(GET_REG(psiochan, MSR) & MSR_CTS); /* * if the CTS is asserted enable Tx interrupt */ if (mask & MSR_CTS) { psiochan->ier |= TxFIFO_BIT; /* enable Tx interrupt */ } else { psiochan->ier &= (~TxFIFO_BIT); /* disable Tx interrupt */ } SET_REG(psiochan, IER, psiochan->ier); } } else { /* * disable all ns16550 interrupts */ SET_REG(psiochan, IER, 0); } psiochan->channel_mode = newmode; KN_INT_ENABLE(intreg); return (ERROR_NONE); }
//----------------------------------------------- //настройка SPI1 void spi1_config(void) { SET_REG( LPC_PINCON->PINSEL0, 3, 15*2, 2); SET_REG( LPC_PINCON->PINSEL1, 0, (16-16)*2, 2); SET_REG( LPC_PINCON->PINSEL1, 3, (17-16)*2, 2); SET_REG( LPC_PINCON->PINSEL1, 3, (18-16)*2, 2); /* S1SPCCR=100; S1SPCR=0x3f; */ LPC_SPI->SPCCR=8; LPC_SPI->SPCR=0x20; }
int uart_setup() { int i; if(UartHasInit) { return 0; } clock_gate_switch(UART_CLOCKGATE, ON); for(i = 0; i < NUM_UARTS; i++) { // set all uarts to transmit 8 bit frames, one stop bit per frame, no parity, no infrared mode SET_REG(HWUarts[i].ULCON, UART_8BITS); // set all uarts to use polling for rx/tx, no breaks, no loopback, no error status interrupts, // no timeouts, pulse interrupts for rx/tx, peripheral clock. Basically, the defaults. SET_REG(HWUarts[i].UCON, (UART_UCON_MODE_IRQORPOLL << UART_UCON_RXMODE_SHIFT) | (UART_UCON_MODE_IRQORPOLL << UART_UCON_TXMODE_SHIFT)); // Initialize the settings array a bit so the helper functions can be used properly UARTs[i].ureg = i; UARTs[i].baud = 115200; uart_set_clk(i, UART_CLOCK_EXT_UCLK0); uart_set_sample_rate(i, 16); } // Set flow control uart_set_flow_control(0, OFF); uart_set_flow_control(1, ON); uart_set_flow_control(2, ON); uart_set_flow_control(3, ON); uart_set_flow_control(4, OFF); // Reset and enable fifo for(i = 0; i < NUM_UARTS; i++) { SET_REG(HWUarts[i].UFCON, UART_FIFO_RESET_TX | UART_FIFO_RESET_RX); SET_REG(HWUarts[i].UFCON, UART_FIFO_ENABLE); UARTs[i].fifo = ON; } for(i = 0; i < NUM_UARTS; i++) { uart_set_mode(i, UART_POLL_MODE); } uart_set_mode(0, UART_POLL_MODE); UartHasInit = TRUE; return 0; }
void spi_set_baud(int _bus, int _baud, SPIWordSize _wordSize, int _isMaster, int cpol, int cpha) { if(_bus < 0 || _bus >= SPICount) return; uint32_t wordSize; switch(_wordSize) { case 8: wordSize = 0; break; case 16: wordSize = 1; break; case 32: wordSize = 2; break; default: return; } SPIStruct *spi = &SPIData[_bus]; spi->wordSize = wordSize; SET_REG(spi->registers->control, 0); spi->config = (_isMaster)? 0x18 : 0; uint32_t freq = clock_get_frequency(spi->clockSource == NCLK? FrequencyBaseFixed: FrequencyBasePeripheral); uint32_t div = 1; if(_baud > 0) div = freq/_baud; spi->config |= (cpha << 1) | (cpol << 2) | (wordSize << SPISETUP_WORDSIZE_SHIFT) | (0x20); // or 0x40, (but this never arises in iBoot). if(spi->clockSource == NCLK) spi->config |= SPISETUP_CLOCKSOURCE; //bufferPrintf("spi: set_baud(%d) isMaster=%d, config=0x%08x, div=%d.\n", _bus, _isMaster, spi->config, div); SET_REG(spi->registers->clkDiv, div); SET_REG(spi->registers->config, spi->config); SET_REG(spi->registers->pin, 2); SET_REG(spi->registers->control, 1); }
/********************************************************************************************************* ** 函数名称: sio16c550Isr ** 功能描述: 16C550 中断服务函数 ** 输 入 : psiochan SIO CHAN ** 输 出 : ERROR or OK ** 全局变量: ** 调用模块: *********************************************************************************************************/ VOID sio16c550Isr (SIO16C550_CHAN *psiochan) { volatile UINT8 iir; UINT8 msr; UINT8 ucRd; UINT8 ucTx; INT i; psiochan->int_ctx = 1; KN_SMP_MB(); iir = (UINT8)(GET_REG(psiochan, IIR) & 0x0f); while (GET_REG(psiochan, LSR) & RxCHAR_AVAIL) { /* receive data */ ucRd = GET_REG(psiochan, RBR); psiochan->pcbPutRcvChar(psiochan->putRcvArg, ucRd); } if ((psiochan->ier & TxFIFO_BIT) && (GET_REG(psiochan, LSR) & LSR_THRE)) { /* transmit data */ for (i = 0; i < psiochan->fifo_len; i++) { if (psiochan->pcbGetTxChar(psiochan->getTxArg, &ucTx) < 0) { psiochan->ier &= (~TxFIFO_BIT); break; } else { SET_REG(psiochan, THR, ucTx); /* char to Transmit Holding Reg */ } } } if (iir == IIR_MSTAT) { /* modem status changed */ msr = GET_REG(psiochan, MSR); if (msr & MSR_DCTS) { if (msr & MSR_CTS) { psiochan->ier |= TxFIFO_BIT; /* CTS was turned on */ } else { psiochan->ier &= (~TxFIFO_BIT); /* CTS was turned off */ } } } KN_SMP_MB(); psiochan->int_ctx = 0; KN_SMP_MB(); SET_REG(psiochan, IER, psiochan->ier); /* update ier */ }
int interrupt_disable(int irq_no) { if(irq_no >= VIC_MaxInterrupt) { return -1; } EnterCriticalSection(); if(irq_no < VIC_InterruptSeparator) { SET_REG(VIC0 + VICINTENABLE, GET_REG(VIC0 + VICINTENABLE) & ~(1 << irq_no)); } else { SET_REG(VIC1 + VICINTENABLE, GET_REG(VIC1 + VICINTENABLE) & ~(1 << (irq_no - VIC_InterruptSeparator))); } LeaveCriticalSection(); return 0; }
int power_setup() { SET_REG(POWER + POWER_CONFIG0, POWER_CONFIG0_RESET); SET_REG(POWER + POWER_CONFIG1, POWER_CONFIG1_RESET); SET_REG(POWER + POWER_CONFIG2, POWER_CONFIG2_RESET); /* turn off everything */ int toReset = POWER_DEFAULT_DEVICES | POWER_VROM | POWER_LCD; SET_REG(POWER + POWER_OFFCTRL, toReset); /* wait for the new state to take effect */ while((GET_REG(POWER + POWER_SETSTATE) & toReset) != (GET_REG(POWER + POWER_STATE) & toReset)); return 0; }
void gpio_register_interrupt(uint32_t interrupt, int type, int level, int autoflip, InterruptServiceRoutine handler, uint32_t token) { uint8_t mode; if(autoflip) mode = 0xC; else if(type) { if(level) mode = 0x4; else mode = 0x6; } else { if(level) mode = 0x8; else mode = 0xa; } gpio_interrupts[interrupt].token = token; gpio_interrupts[interrupt].func = handler; EnterCriticalSection(); reg32_t reg = GPIO + sizeof(uint32_t)*interrupt; SET_REG(reg, (GET_REG(reg) &~ 0xE) | mode | 0x200); LeaveCriticalSection(); }
int gpio_direction_input(rt_uint32_t gpio) { rt_uint32_t reg, base; if (gpio > NUM_OF_GPIO) { rt_kprintf("ERROR: %s, incorrect GPIO num\n", __func__); return -RT_ERROR; } if (!gpio_available[gpio]) { rt_kprintf("ERROR: %s, GPIO %d is not available\n", __func__, gpio); return -RT_EBUSY; } base = gpio_to_base(gpio); gpio = gpio % 32; // fixme: lock // spin_lock_irqsave(&chip->lock, flags); reg = GET_REG(base + REG_GPIO_SWPORTA_DDR); reg &= ~(1 << gpio); SET_REG(base + REG_GPIO_SWPORTA_DDR, reg); // spin_unlock_irqrestore(&chip->lock, flags); return 0; }
int uart_set_sample_rate(int ureg, int rate) { if(ureg > 4) return -1; // Invalid ureg uint32_t newSampleRate; switch(rate) { case 4: newSampleRate = UART_SAMPLERATE_4; break; case 8: newSampleRate = UART_SAMPLERATE_8; break; case 16: newSampleRate = UART_SAMPLERATE_16; break; default: return -1; // Invalid sample rate } SET_REG(HWUarts[ureg].UBAUD, (GET_REG(HWUarts[ureg].UBAUD) & (~UART_SAMPLERATE_MASK)) | (newSampleRate << UART_SAMPLERATE_SHIFT)); UARTs[ureg].sample_rate = rate; uart_set_baud_rate(ureg, UARTs[ureg].baud); return 0; }
static void setupBUTTON (void) { // todo, swap out hardcoded pin/bank with macro u32 rwmVal; /* read-write-modify place holder var */ /* Setup APB2 (GPIOC) */ rwmVal = GET_REG(RCC_APB2ENR); rwmVal |= 0x00000010; SET_REG(RCC_APB2ENR,rwmVal); /* Setup GPIOC Pin 9 as PP Out */ rwmVal = GET_REG(GPIO_CRH(GPIOC)); rwmVal &= 0xFFFFFF0F; rwmVal |= 0x00000040; SET_REG(GPIO_CRH(GPIOC),rwmVal); }
void clock_gate_switch(uint32_t gate, OnOff on_off) { #if !defined(CONFIG_IPHONE_4) && !defined(CONFIG_IPAD) uint32_t gate_register; uint32_t gate_flag; if(gate < CLOCK1_Separator) { gate_register = CLOCK1 + CLOCK1_CL2_GATES; gate_flag = gate; } else { gate_register = CLOCK1 + CLOCK1_CL3_GATES; gate_flag = gate - CLOCK1_Separator; } uint32_t gates = GET_REG(gate_register); if(on_off == ON) { gates &= ~(1 << gate_flag); } else { gates |= 1 << gate_flag; } SET_REG(gate_register, gates); #else power_ctrl(gate, on_off); #endif }
int spi_setup() { int i; for(i = 0; i < SPICount; i++) { // Only enable SPIs 1-3. if(((0x7 >> i) & 1) == 0) continue; SPIRegisters *regs = &SPIRegs[i]; SPIStruct *data = &SPIData[i]; memset(data, 0, sizeof(*data)); data->registers = regs; data->clockSource = NCLK; clock_gate_switch(regs->gate, ON); SET_REG(data->registers->control, 0); interrupt_install(regs->irq, spi_irq_handler, i); interrupt_enable(regs->irq); } return 0; }
static void eventTimerHandler() { uint64_t curTime; Event* event; #if defined(CONFIG_IPHONE_4) || defined(CONFIG_IPAD) SET_REG(TIMER_REGISTER_TICK, TIMER_STATE_MANUALUPDATE); #endif curTime = timer_get_system_microtime(); while(EventList.list.next != &EventList) { // Just keep checking the first event on the list until the list is empty // This works because we remove events as we dispatch them event = EventList.list.next; if(event == NULL) { break; } if(curTime >= event->deadline) { // take it off the list and dispatch it ((Event*)(event->list.next))->list.prev = event->list.prev; ((Event*)(event->list.prev))->list.next = event->list.next; event->list.next = NULL; event->list.prev = NULL; event->handler(event, event->opaque); } else { // The event queue is sorted, so we can just stop looping on the first // event that hasn't been triggered break; } } }
static void sparc_push_lfun(unsigned int no) { LOAD_PIKE_FP(); LOAD_PIKE_SP(); /* lduw [ %pike_fp, %offset(pike_frame, current_object) ], %pike_obj */ PIKE_LDPTR(SPARC_REG_PIKE_OBJ, SPARC_REG_PIKE_FP, OFFSETOF(pike_frame, current_object), 1); /* stw %pike_obj, [ %pike_sp, %offset(svalue, u.object) ] */ PIKE_STPTR(SPARC_REG_PIKE_OBJ, SPARC_REG_PIKE_SP, sparc_pike_sp_bias + OFFSETOF(svalue, u.object), 1); /* lduw [ %pike_obj, %offset(object, refs) ], %i0 */ SPARC_LDUW(SPARC_REG_I0, SPARC_REG_PIKE_OBJ, OFFSETOF(object, refs), 1); /* add %i0, 1, %i0 */ SPARC_ADD(SPARC_REG_I0, SPARC_REG_I0, 1, 1); /* lduw [ %pike_fp, %offset(pike_frame, context) ], %i1 */ PIKE_LDPTR(SPARC_REG_I1, SPARC_REG_PIKE_FP, OFFSETOF(pike_frame, context), 1); /* stw %i0, [ %pike_obj, %offset(object, refs) ] */ SPARC_STW(SPARC_REG_I0, SPARC_REG_PIKE_OBJ, OFFSETOF(object, refs), 1); /* lduh [ %i1, %offset(inherit, identifier_level ], %i1 */ SPARC_LDUH(SPARC_REG_I1, SPARC_REG_I1, OFFSETOF(inherit, identifier_level), 1); SET_REG(SPARC_REG_I2, (no & 0xffff) | (PIKE_T_FUNCTION << 16)); /* add %i1, %i2, %i1 */ SPARC_ADD(SPARC_REG_I1, SPARC_REG_I1, SPARC_REG_I2, 0); /* stw %i1, [ %pike_sp, %g0 ] */ SPARC_STW(SPARC_REG_I1, SPARC_REG_PIKE_SP, sparc_pike_sp_bias, 1); sparc_pike_sp_bias += sizeof(struct svalue); sparc_codegen_state |= SPARC_CODEGEN_SP_NEEDS_STORE; }