void rtl92se_tx_fill_cmddesc(struct ieee80211_hw *hw, u8 *pdesc, bool firstseg, bool lastseg, struct sk_buff *skb) { struct rtl_priv *rtlpriv = rtl_priv(hw); struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); struct rtl_tcb_desc *tcb_desc = (struct rtl_tcb_desc *)(skb->cb); dma_addr_t mapping = pci_map_single(rtlpci->pdev, skb->data, skb->len, PCI_DMA_TODEVICE); if (pci_dma_mapping_error(rtlpci->pdev, mapping)) { RT_TRACE(rtlpriv, COMP_SEND, DBG_TRACE, "DMA mapping error\n"); return; } /* Clear all status */ CLEAR_PCI_TX_DESC_CONTENT(pdesc, TX_CMDDESC_SIZE_RTL8192S); /* This bit indicate this packet is used for FW download. */ if (tcb_desc->cmd_or_init == DESC_PACKET_TYPE_INIT) { /* For firmware downlaod we only need to set LINIP */ SET_TX_DESC_LINIP(pdesc, tcb_desc->last_inipkt); /* 92SE must set as 1 for firmware download HW DMA error */ SET_TX_DESC_FIRST_SEG(pdesc, 1); SET_TX_DESC_LAST_SEG(pdesc, 1); /* 92SE need not to set TX packet size when firmware download */ SET_TX_DESC_PKT_SIZE(pdesc, (u16)(skb->len)); SET_TX_DESC_TX_BUFFER_SIZE(pdesc, (u16)(skb->len)); SET_TX_DESC_TX_BUFFER_ADDRESS(pdesc, mapping); wmb(); SET_TX_DESC_OWN(pdesc, 1); } else { /* H2C Command Desc format (Host TXCMD) */ /* 92SE must set as 1 for firmware download HW DMA error */ SET_TX_DESC_FIRST_SEG(pdesc, 1); SET_TX_DESC_LAST_SEG(pdesc, 1); SET_TX_DESC_OFFSET(pdesc, 0x20); /* Buffer size + command header */ SET_TX_DESC_PKT_SIZE(pdesc, (u16)(skb->len)); /* Fixed queue of H2C command */ SET_TX_DESC_QUEUE_SEL(pdesc, 0x13); SET_BITS_TO_LE_4BYTE(skb->data, 24, 7, rtlhal->h2c_txcmd_seq); SET_TX_DESC_TX_BUFFER_SIZE(pdesc, (u16)(skb->len)); SET_TX_DESC_TX_BUFFER_ADDRESS(pdesc, mapping); wmb(); SET_TX_DESC_OWN(pdesc, 1); } }
static void __r92su_tx_fill_header(tx_hdr *tx_hdr, unsigned int len, bool first, bool last, unsigned int qsel) { SET_TX_DESC_PKT_SIZE(tx_hdr, len); SET_TX_DESC_OFFSET(tx_hdr, TX_DESC_SIZE); SET_TX_DESC_LAST_SEG(tx_hdr, last); SET_TX_DESC_FIRST_SEG(tx_hdr, first); SET_TX_DESC_OWN(tx_hdr, 1); SET_TX_DESC_QUEUE_SEL(tx_hdr, qsel); }
void rtl92se_set_desc(struct ieee80211_hw *hw, u8 *pdesc, bool istx, u8 desc_name, u8 *val) { if (istx) { switch (desc_name) { case HW_DESC_OWN: wmb(); SET_TX_DESC_OWN(pdesc, 1); break; case HW_DESC_TX_NEXTDESC_ADDR: SET_TX_DESC_NEXT_DESC_ADDRESS(pdesc, *(u32 *) val); break; default: RT_ASSERT(false, "ERR txdesc :%d not process\n", desc_name); break; } } else { switch (desc_name) { case HW_DESC_RXOWN: wmb(); SET_RX_STATUS_DESC_OWN(pdesc, 1); break; case HW_DESC_RXBUFF_ADDR: SET_RX_STATUS__DESC_BUFF_ADDR(pdesc, *(u32 *) val); break; case HW_DESC_RXPKT_LEN: SET_RX_STATUS_DESC_PKT_LEN(pdesc, *(u32 *) val); break; case HW_DESC_RXERO: SET_RX_STATUS_DESC_EOR(pdesc, 1); break; default: RT_ASSERT(false, "ERR rxdesc :%d not process\n", desc_name); break; } } }